Black Phosphores

Black phosphorus eld-effect transistorsLikai Li1, Yijun Yu1, Guo Jun Ye2, Qingqin Ge1, Xuedong Ou1, Hua Wu1, Donglai Feng1, Xian Hui Chen2*and Yuanbo Zhang1*

Two-dimensional crystals have emerged as a class of materials that may impact future electronic technologies. Experimentallyidentifying and characterizing new functional two-dimensional materials is challenging, but also potentially rewarding.Here, we fabricate eld-effect transistors based on few-layer black phosphorus crystals with thickness down to a fewnanometres. Reliable transistor performance is achieved at room temperature in samples thinner than 7.5 nm, with draincurrent modulation on the order of 105 and well-developed current saturation in the IV characteristics. The charge-carriermobility is found to be thickness-dependent, with the highest values up to 1,000 cm2 V21 s21 obtained for a thickness of10 nm. Our results demonstrate the potential of black phosphorus thin crystals as a new two-dimensional material forapplications in nanoelectronic devices.

Black phosphorus is a layered material in which individualatomic layers are stacked together by van der Waals inter-actions, much like bulk graphite1. Inside a single layer, each

phosphorus atom is covalently bonded with three adjacent phos-phorus atoms to form a puckered honeycomb structure24

(Fig. 1a). The three bonds take up all three valence electrons ofphosphorus, so, unlike graphene5,6, monolayer black phosphorus(termed phosphorene) is a semiconductor with a predicteddirect bandgap of 2 eV at the G point of the rst Brillouinzone7. For few-layer phosphorene, interlayer interactions reducethe bandgap for each layer added, and eventually reach 0.3 eV(refs 812) for bulk black phosphorus. The direct gap alsomoves to the Z point as a consequence7,13. Such a band structureprovides a much needed gap for the eld-effect transistor (FET)application of two-dimensional materials such as graphene, andthe thickness-dependent direct bandgap may lead to potentialapplications in optoelectronics, especially in the infrared regime.In addition, observations of a phase transition from semiconduc-tor to metal14,15 and superconductor under high pressure16,17 indi-cate correlated phenomena play an important role in blackphosphorus under extreme conditions. We fabricated few-layerphosphorene devices and studied their electronic properties modu-lated by the electric eld effect. Excellent transistor performanceswere achieved at room temperature. In particular, importantmetrics of our devices such as drain current modulation andmobility are either better or comparable to FETs based on otherlayered materials18,19.

Few-layer phosphorene FET device fabricationBulk black phosphorus crystals were grown under high pressureand high temperature (see Methods). The band structure of thebulk black phosphorus was veried by angle-resolved photo-emission spectroscopy (ARPES) measurements, as well asab initio calculations. The lled bands of freshly cleaved bulkcrystal measured by ARPES are shown in Fig. 1b, and largelyagree with screened hybrid functional calculations with nomaterial-dependent empirical parameters (Fig. 1b, dashed andsolid lines for lled and empty bands, respectively). The calculatedbandgap (0.2 eV) also agrees reasonably well with previousmeasurements811, taking into account that screened hybrid

functional calculations tend to slightly underestimate the size ofthe bandgap in semiconductors2022.

We next fabricated few-layer phosphorene FETs with a backgateelectrode (Fig. 2a). A scotch tape-based mechanical exfoliationmethod was used to peel thin akes from bulk crystal onto degen-erately doped silicon wafer covered with a layer of thermallygrown silicon dioxide. Optical microscopy and atomic forcemicroscopy (AFM) were used to nd thin ake samples and deter-mine their thickness (Fig. 2a). Metal contacts were then depositedon black phosphorus thin akes by sequential electron-beamevaporation of chromium and gold (typically 5 nm and 60 nm,respectively) through a stencil mask aligned with the sample. Astandard electron-beam lithography process and other contactmetals such as titanium/gold were also used to fabricate few-layerphosphorene FETs, and similar results were obtained in terms ofdevice performance.

FET characteristics of few-layer phosphorene devicesThe switching behaviour of our few-layer phosphorene transistor atroom temperature was characterized in vacuum (1 1025 mbar),in the conguration presented in Fig. 2a. We swept the backgatevoltage Vg, applied to the degenerated doped silicon, with thesourcedrain bias Vds across the black phosphorus conductivechannel held at xed values. The results obtained from a devicewith a 5-nm-thick channel on top of a 90 nm SiO2 gate dielectricare shown in Fig. 2b. When the gate voltage was varied from230 V to 0 V, the channel switched from the on state to the offstate and a drop in drain current by a factor of 105 was observed.The measured drain current modulation is four orders of magnitudelarger than that in graphene (due to its lack of a bandgap) andapproaches the value recently reported in MoS2 devices

18. Such ahigh drain current modulation makes black phosphorus thin lma promising material for applications in digital electronics23.Similar switching behaviour (with varying drain current modu-lation) is observed on all black phosphorous thin-lm transistorswith thicknesses up to 50 nm. We note that the on state currentof our devices has not yet reached saturation due to the fact thatthe doping level is limited by the breakdown electric eld of theSiO2 backgate dielectric. It is therefore possible to achieve evenhigher drain current modulation by using high-k materials as gate

1State Key Laboratory of Surface Physics and Department of Physics, Fudan University, Shanghai 200433, China, 2Hefei National Laboratory for PhysicalScience at Microscale and Department of Physics, University of Science and Technology of China, Hefei, Anhui 230026, China. *e-mail: [email protected];[email protected]

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2014 Macmillan Publishers Limited. All rights reserved.

dielectrics for higher doping. Meanwhile, a subthreshold swing of5 V per decade is observed, which is much larger than the sub-threshold swing in commercial silicon-based devices (70 mVper decade). We note that the subthreshold swing in our devicesvaries from sample to sample (from 3.7 V per decade to13.3 V per decade) and is of the same order of magnitude asreported in multilayer MoS2 devices with a similar backgateconguration24,25. The rather big subthreshold swing is mainlyattributed to the large thickness of the SiO2 backgate dielectricthat we use, and multiple factors such as insulator layer thickness26,the Schottky barrier at the subthreshold region25 and samplesubstrate interface state may also have an inuence.

The switching off at the negative side of the Vg sweep isaccompanied by a slight turn-on at positive gate voltages, asshown in Fig. 2b. To further explore this ambipolar behaviour, wefabricated few-layer phosphorene devices with multiple electricalcontacts (Fig. 2c, inset) and performed Hall measurements usingtwo opposing contacts (V2 and V4, for example) perpendicular tothe drainsource current path to measure the transverse resistanceRxy. The Hall coefcient RH, dened as the slope of Rxy as a function

of external magnetic eld B, reects both the sign and density of thecharge carriers in the sample. As shown in Fig. 2c, a carrier signinversion is clearly observed in the on states, with positive andnegative gate voltages corresponding to hole and electron conduc-tion, respectively. This unambiguously shows that the ambipolarswitching of the devices is caused by Fermi level shifting from thevalence band into the conduction band.

The nature of the electrical conduction was probed further byperforming IV measurements in a two-terminal conguration(Fig. 2a). As shown in Fig. 2d, the sourcedrain current Ids varieslinearly with Vds in the on state of the hole side, indicating anohmic contact in this region. Meanwhile, Ids versus Vds is stronglynonlinear on the electron side (Fig. 2d, inset), as is typical for semi-conducting channels with Schottky barriers at the contacts. Theobserved IV characteristics can be readily explained by workfunc-tion mismatch between the metal contacts and few-layer phosphor-ene; the high workfunction of the metal electrodes causes holeaccumulation at the metalsemiconductor interface, which formsa low-resistance ohmic contact for the p-doped sample, while forthe n-doped sample a depletion region is formed at the interface,leading to Schottky barriers and thus nonlinear conduction. Thismodel also explains the observed disparity between conduction atthe electron and hole sides in all our samples (Fig. 2b) and iswidely accepted to describe the contact behaviour in MoS2 devices

27.For potential applications in digital and radiofrequency devices,

saturation of the drain current is crucial in order to reach maximumpossible operation speeds23. By carefully choosing the ratio betweenchannel length and SiO2 layer thickness, a well-dened current sat-uration can be achieved in the high drainsource bias region(Fig. 3a). Meanwhile, the electrical contacts remain ohmic in thelinear region at low drainsource biases. The results shown inFig. 3a were obtained in the on state of the hole side of the conduc-tion in a 5 nm sample with a 4.5-mm-long channel on the 90 nmSiO2 gate dielectric. Such a well-developed saturation behaviour,which is absent in graphene-based FET devices23, is crucial forachieving high power gains. Coupled with the fact that ourchannel thickness is on the order of nanometres and thus robustagainst short-channel effects when the channel length is shrunkto the nanometre scale, our results suggest the high potential ofblack phosphorus in high-speed eld-effect device applications.We note that the on state conductance of our device is relativelylow and the threshold sourcedrain bias is relatively high comparedto typical silicon-based devices. Both factors are attributed to thelong channel length in our current device. Better device perform-ance, that is, larger saturation current and lower threshold bias, isexpected if the channel length and the gate oxide thickness arereduced. Further investigations are needed to test the limit of thedevice performances of black phosphorus FETs.

Charge transport mechanism in black phosphorus thin akeWe now turn to the characterization of eld-effect mobility in few-layer phosphorene devices. Conductance G was measured as afunction of Vg and we extracted the eld-effect mobility mFE inthe linear region of the transfer characteristics28:

mFE =LW

1Cg

dGd(Vg Vth)

(1)

where L andW are the length and width of the channel, respectively,Cg is the capacitance per unit area, and Vth is the thresholdgate voltage. A hole mobility as high as 984 cm2 V21 s21 is obtainedon a 10 nm sample, as shown in Fig. 3b, and is found to be stronglythickness-dependent. Transfer characteristics of two other typicalsamples of different thicknesses (8 nm and 5 nm, with the 5 nmsample the same as measured in Fig. 3a) are also shown inFig. 3b. The conductance was measured in a four-terminal

a

b

5

k (1)

E

E f (e

V)

0.6 0.4 0.2 0 0.2 0.4 0.6 0.8

0

2

4

6

2

4

L ZU T

L

TU

Z

Figure 1 | Crystal and electronic structure of bulk black phosphorus.

a, Atomic structure of black phosphorus. b, Band structure of bulk black

phosphorus mapped out by ARPES measurements. A bandgap is clearly

observed. Superimposed on top are calculated bands of the bulk crystal.

Blue solid and red dashed lines denote empty and lled bands, respectively.

The directions of the ARPES mapping are along U (LZ) and T, as indicatedin the rst Brillion zone shown in the inset. Ef is the Fermi energy.

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conguration to avoid complications from electrical contacts25. Atwo-terminal conductance measurement set-up was also used onsome of our devices. This was found to overestimate hole mobility,but still yielded values of the same order of magnitude (Fig. 3b,inset). Such mobility values, although still much lower than in gra-phene2931, compare favorably with MoS2 samples

18,19,25 and arealready much higher than values found in typical silicon-baseddevices that are commercially available (500 cm2 V21 s21)23.

The thickness dependence of the two key metrics of materialperformancedrain current modulation and mobilitywasfurther explored to elucidate the transport mechanism of few-layer phosphorene FETs. The experimental results are summarizedin the inset of Fig. 3b. The drain current modulation decreasesmonotonically as sample thickness is increased, while the mobilitypeaks at 10 nm and decreases slightly above this. A similarthickness dependence of carrier mobility has been reported in

other two-dimensional FETs such as few-layer graphene andMoS2, where models taking into account the screening of thegate electric eld were invoked to account for the observed behav-iour32,33. Simply speaking, the gate electric eld only induces freecarriers in the bottom layers as a result of charge screening. So,the top layers still provide nite conduction in the off state, redu-cing the drain current modulation. The eld-effect mobility is alsodominated by the contribution from layers at the bottom. Thinnersamples are more susceptible to charge impurities at the interface(thus their lower mobilities) that are otherwise screened by theinduced charge in thicker samples. This explains the sharp increasein the eld-effect mobility below 10 nm. As the samples becomethicker, however, another factor has to be taken into accountbecause the current is injected from electrical contacts on thetop surface, the nite interlayer resistance forces the current toow in the top layers, which are not gated by the backgate. This

Vds (mV)

I ds (

nA)

I ds (

nA)

Vds (V)8 4 0 4

20

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20

100 80 60 40 20 0 20 40 60 60 40 20 0 20 40 6080 100

300

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100200

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Hal

l coe

ffici

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m2 C

1)

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5 m

Source

Drain

V1 V2

V3 V4

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I ds (A

m

1)

100

102

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Vg (V)

5 m

Si

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Vg

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0 1 2 3 4 5

0246

Hei

ght (

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a

c d

b

A

Figure 2 | Few-layer phosphorene FET and its device characteristics. a, Top: Schematic of device structure of a few-layer phosphorene FET. The device

prole shown here is the three-dimensional rendering of the AFM data. Electrodes and a few-layer phosphorene crystal are false-coloured to match how they

appear under the microscope. Bottom: Cross-section of device along the white dashed line in the schematic. b, Sourcedrain current (on a logarithmic scale)

as a function of gate voltage obtained from a 5-nm-thick device on a silicon substrate with 90 nm SiO2 at room temperature, with drainsource voltages of

10 mV (red curve) and 100 mV (green curve). Channel length and width of the device are 1.6mm and 4.8mm, respectively. Drain current modulation up to105 is observed for both drainsource biases on the hole side of the gate doping, with a subthreshold swing (the slope of the black dashed line) of 4.6 Vper decade. A slight turn-on at the electron side is also observed. c, Hall coefcient (blue curve) and conductance (red curve) as a function of gate voltage

collected from a 8-nm-thick sample on a silicon substrate with 285 nm SiO2. Carrier type inversion, signied by the sign change of the Hall coefcient, is

observed when the polarity of the gate is reversed. Inset: Optical image of a typical multi-terminal few-layer phosphorene device. d, IV characteristics of the

device in Fig. 2b. Linear behaviour is seen at Vg230 V, 225 V, 220 V and 215 V (black, red, green and blue curves, respectively), indicating ohmiccontact on the hole side of the gate doping. Inset: Nonlinear behaviour on the electron side (Vg 30 V, 25 V and 20 V; black, red and green curves,respectively) of the gate doping indicates the formation of a Schottky barrier at the contacts.

ARTICLES NATURE NANOTECHNOLOGY DOI: 10.1038/NNANO.2014.35



effect depresses the eld-effect mobility for samples thicker than10 nm. Based on the above arguments, we modelled the electricalconduction in our samples using a self-consistently obtainedcarrier distribution (for more details see Supplementary Section 7),and our calculation ts well with the experimental data shown inthe inset of Fig. 3b. The model also suggests a way to achievehigher mobility without sacricing drain current modulation. Byusing a topgate device structure with a layer of high-k dielectric

material as the gate dielectric, one could effectively screen thecharge impurities, but leave the drain current modulation intact.In addition, because the top layers where the current ows arenow gated by the topgate, the mobility is no longer affected bythe interlayer resistance. Such a method has been proven towork in MoS2 FETs

18,19.Finally, we examined the temperature dependence of the carrier

mobility to uncover various factors that limit the mobility in ourFETs. Two types of carrier mobility were measured in the samedevice, for comparison: the mFE extracted from the linear part ofthe gate-dependent conductance (Fig. 4a) according to equation(1), and the Hall mobility mH obtained from

mH =LW

Gne

(2)

where e is the charge of an electron and n is the two-dimensionalcharge density determined from gate capacitance, n Cg(Vg2Vth),which is equal to the density extracted from Hall measurement

30 20 10 0 100

50

100

150

Normalized gate voltage (V)

Shee

t con

duct

ivity

(S)

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101102103104105

0D

rain current modulation

FE (

cm2 V

1s

1 )

101

102

103

10 8 6 4 2 01.2

1.0

0.8

0.6

0.4

0.2

0.0 5 V13 V15 V17 V

19 V21 V

23 V

25 V

I ds (A

m

1)

Vds (V)

Vga

b

Figure 3 | Current saturation and mobility of a few-layer phosphorene FET.

a, Drainsource current Ids as a function of bias Vds at different gate voltages

collected from a 5-nm-thick device on a silicon substrate with 90 nm SiO2.

Channel length and width are 4.5mm and 2.3mm, respectively. A saturationregion is observed for all applied gate voltages. b, Sheet conductivity

measured as a function of gate voltage for devices with different

thicknesses: 10 nm (black solid line), 8 nm (red solid line) and 5 nm (green

solid line), with eld-effect mobility values of 984, 197 and 55 cm2 V21 s21,

respectively. Field-effect mobilities were extracted from the line t of the

linear region of the conductivity (dashed lines). The 5-nm-thick device is the

same as measured in a. All gate voltages are normalized to 90 nm gate

oxide for easy comparison. Inset: Summary of drain current modulation

(lled blue triangles) and carrier mobility (open circles) of black phosphorus

FETs of varying thicknesses. Mobilities measured in four-terminal and two-

terminal conguration are denoted by black and red open circles,

respectively. Error bars result from uncertainties in determining the carrier

density, due to hysteresis of the conductance during gate sweep, and the

irregular shape of our samples. The upper bound of the those uncertainties

is used to estimate the error bars. Dashed lines indicate the models

described in the main text.

Mob

ility

(cm

2 V1

s1 )

100

200

300

400

500

600

Temperature (K)10 1002

0

200

400

600

800

1,000

Con

duct

ance

(S)

80 60 40 20 0 20

Gate voltage (V)

a

b

2 K 20 K 60 K 100 K 150 K 180 K

200 K 220 K 300 K

Temperature

n = 5.5 1012 cm2

n = 4.0 1012 cm2

n = 2.5 1012 cm2

Figure 4 | Temperature-dependent behaviour of a few-layer phosphorene

FET. a, Four-terminal conductance as a function of gate voltage measured in

an 8-nm-thick sample at different temperatures. Channel length and width

are 2.6mm and 8.6mm, respectively. b, Field-effect mobility (red opencircles) and Hall mobility (lled squares, three different values of n) as a

function of temperature on a logarithmic scale. Data are extracted from the

same sample as in a. Error bars for eld-effect mobility are dened the

same way as in Fig. 3b inset. Error bars for Hall mobility represent the

uncertainties coming from irregular shape of the sample. A power-law

dependence m T20.5 (black dashed line) is plotted in the high-temperatureregion as a guide to the eye.




n 1/eRH if the sample geometry permits an accurate determi-nation of Hall coefcient RH (Supplementary Fig. 7). The two mobi-lities in an 8-nm-thick sample as a function of temperature areshown in Fig. 4b. They fall in the vicinity of each other and showa similar trend as the temperature is varied: both decrease at temp-eratures higher than 100 K, and saturate (or decrease slightly forlow carrier densities) at lower temperatures. The behaviour of themobility as the temperature is lowered to 2 K is consistent with scat-tering from charged impurities32. We note that in this temperaturerange the Hall mobility increases as the gate-induced carrierdensity becomes larger (Fig. 4b). The reduced scattering in thesample points to the diminished disorder potential as a result ofscreening by free charge carriers. This further corroborates ourmodel in which the charged impurity at the sample/substrate inter-face is a limiting factor for carrier mobility. On the other hand, thedrop in mobility from 100 K up to 300 K can be attributed to theelectronphonon scattering that dominates at high temperatures32,and the temperature dependence roughly follows the power lawm/ T2g, as seen in Fig. 4b. The exponent g depends on elec-tronphonon coupling in the sample, and is found to be close to0.5 in our 8-nm-thick device (as a guide to the eye, m T20.5 isplotted in Fig. 4b as a dashed line). This g value for few-layer phos-phorene is notably smaller than values in other two-dimensionalmaterials33 and bulk black phosphorus11, but agrees with that inmonolayer MoS2 covered by a layer of high-k dielectric

19. Theexact mechanism of the suppression of phonon scattering in few-layer phosphorene is not clear at this moment and warrantsfurther study.

ConclusionWe have succeeded in fabricating p-type FETs based on few-layerphosphorene. Our samples exhibit ambipolar behaviour withdrain current modulation up to 105, and a eld-effect mobilityvalue up to 1,000 cm2 V21 s21 at room temperature. The carriermobility is limited by charge impurity scattering at low temperaturesand electronphonon scattering at high temperatures. The oncurrent is low and subthreshold swing is high, but optimizationof the gate dielectric should improve these characteristics. Theability to fabricate transistors, combined with the fact that few-layer phosphorene has a direct bandgap in the infrared regime,makes black phosphorus a candidate for future nanoelectronicand optoelectronic applications.

MethodsSample growth. Black phosphorus was synthesized under a constant pressure of10 kbar by heating red phosphorus to 1,000 8C and slowly cooling to 600 8C at acooling rate of 100 8C per hour. Red phosphorus was purchased from AladdinIndustrial Corporation with 99.999% metals basis. The high-pressure environmentwas provided by a cubic-anvil-type apparatus (Riken CAP-07). X-ray diffraction(XRD) was performed on a Smartlab-9 diffractometer (Rikagu) using Cu Karadiation (Supplementary Fig. 1).

Measurements. ARPES measurements were performed at BaDElPh beamline at theElettra synchrotron radiation facility with a Specs Phoibos 150 electron analyser.34

The overall energy resolution was set to 20 meV or better and the typical angularresolution was 0.58. During measurements the temperature was kept at 60 K to avoidthe onset of charging. The data shown in Fig. 1b were taken with s-polarized 20 eVphotons; no obvious polarization dependence was seen, but a noticeable intensityvariation was observed for observed bands.

Transport measurements were mainly performed in an Oxford InstrumentsOptistat AC-V12 cryostat with samples in vacuum (1 1025 mbar), with somemeasurements carried out in an Oxford Instruments Integra a.c. cryostat andQuantum Design Physical Property Measurement System (PPMS) when a magneticeld was required. Data were collected in a d.c. set-up using a DL 1211 currentpreamplier with a voltage source, or a Keithley 6220 current source combined witha Keithley 2182 nanovoltmeter. Some Hall measurements were carried out using anSRS 830 lock-in amplier.

Band structure calculation. Our ab initio band structure calculations, based ondensity functional theory, were performed using the projector augmented wavemethod35,36, as implemented in the Vienna ab initio Simulation Package (VASP)

code37. The crystal structure data of black phosphorus were taken from refs 2 and 7.For the exchange-correlation energy, we used the screened hybrid density functionalof the HeydScuseriaErnzerhof type (HSE06)38. Details of the calculation areprovided in Supplementary Section 5.

Received 12 September 2013; accepted 3 February 2014;published online 2 March 2014

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AcknowledgementsThe authors thank R. Tao, F. Wang, Y. Wu, L. Ma, M. Sui, G. Chen and F. Yang fordiscussions and F. Xiu, Y. Liu and C. Zhang for assistance with measurements in PPMS.Q.G. and D.F. acknowledge support from L. Petaccia, D. Lonza and the ICTP-ElettraUsers Support Programme. Part of the sample fabrication was performed at FudanNano-fabrication Laboratory. L.L., Y.Y., Q.G., D.F. and Y.Z. acknowledge nancial supportfrom the National Basic Research Program of China (973 Program) under grant nos2011CB921802, 2012CB921400 and 2013CB921902, and from the NSF of China undergrant no. 11034001. G.J.Y. and X.H.C. acknowledge support from the Strategic Priority

Research Program of the Chinese Academy of Sciences under grant no. XDB04040100 andthe National Basic Research Program of China (973 Program) under grant no.2012CB922002. X.O. and H.W. are supported by the Pu Jiang Program of Shanghai undergrant no. 12PJ1401000.

Author contributionsX.H.C. and Y.Z. conceived the project. G.J.Y. and X.H.C. grew bulk black phosphoruscrystal. L.L. fabricated black phosphorus thin-lm devices and performed electricmeasurements, and L.L., Y.Y. and Y.Z. analysed the data. Q.G. and D.F. carried out ARPESmeasurements on bulk black phosphorus crystal. X.O. and H.W. performed ab initio bandstructure calculations. L.L. and Y.Z. wrote the paper and all authors commented on it.

Additional informationSupplementary information is available in the online version of the paper. Reprints andpermissions information is available online at www.nature.com/reprints. Correspondence andrequests for materials should be addressed to X.H.C. and Y.Z.

Competing nancial interestsThe authors declare no competing nancial interests.




Black phosphorus field-effect transistorsFew-layer phosphorene FET device fabricationFET characteristics of few-layer phosphorene devicesCharge transport mechanism in black phosphorus thin flakeConclusionMethodsSample growthMeasurementsBand structure calculation

Figure 1 Crystal and electronic structure of bulk black phosphorus.Figure 2 Few-layer phosphorene FET and its device characteristics.Figure 3 Current saturation and mobility of a few-layer phosphorene FET.Figure 4 Temperature-dependent behaviour of a few-layer phosphorene FET.ReferencesAcknowledgementsAuthor contributionsAdditional informationCompeting financial interests

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