Block Diagram of 8051 Microcontroller

Introduction to 8051

The 8051 microcontroller is a very popular 8-bit microcontroller introduced by Intel in the year 1981 and it has become almost the academic standard now a days. The 8051 is based on an 8-bit CISC core with Harvard architecture. Its 8-bit architecture is optimized for control applications with extensive Boolean processing. It is available as a 40-pin DIP chip and works at +5 Volts DC.

Salient Features of 8051

1. 4 KB on chip program memory (ROM or EPROM) 2. 128 bytes on chip data memory (RAM) 3. 8-bit data bus 4. 16-bit address bus 5. 32 general purpose registers each of 8 bits 6. Two - 16 bit timers T0 and T1 7. Five Interrupts (3 internal and 2 external) 8. Four Parallel ports each of 8-bits (PORT0, PORT1, PORT2, PORT3) with a total of 32 I/O lines 9. One 16-bit program counter and One 16-bit DPTR ( data pointer) 10. One 8-bit stack pointer 11. One Microsecond instruction cycle with 12 MHz Crystal 12. One full duplex serial communication port

Architecture Diagram

The architecture of the 8051 microcontroller can be understood from the block diagram. It has Harward architecture with RISC (Reduced Instruction Set Computer) concept. The block diagram of 8051 microcontroller is shown. It consists of:

an 8-bit ALU one 8-bit PSW (Program Status Register) A and B registers one 16-bit Program counter

one 16-bit Data Pointer Register (DPTR) 128 bytes of RAM and 4kB of ROM and four parallel I/O ports each of 8-bit width

Architecture Explained Arithmetic Logic Unit (ALU)

8-bit ALU can perform all the 8-bit arithmetic and logical operations in one machine cycle The ALU is associated with two registers A & B which are special function registers which

hold the results of many arithmetic and logical operations. A Register

It is also called the Accumulator and as it’s name suggests, it is used as a general register to accumulate the results of a large number of instructions.

By default it is used for all mathematical operations and also data transfer operations between CPU and any external memory.

B Register It is mainly used for multiplication (MUL AB) and division ( DIV AB) operations along with A

register. It has no other function other than as a location where data may be stored.

The R registers The "R" registers are a set of eight registers that are named R0, R1 up to and R7. These registers are used as auxillary registers in many operations. These registers are also used to temporarily store values.

Program Counter (PC) 16-bit program counter It always points to the address of the next instruction to be executed. After execution of one

instruction the program counter is incremented to point to the address of the next instruction to be executed.

Contents of PC are placed on address bus to find and fetch the desired instruction. Since the PC is 16-bit width, 8051 can access program addresses from 0000H to FFFFH, a total

of 6kB of code.

Stack Pointer Register (SP) 8-bit register which stores the address of stack top. i.e the Stack Pointer is used to indicate

where the next value to be removed from the stack should be taken from. When a value is pushed onto the stack, the 8051 first increments the value of SP and then

stores the value at the resulting memory location. Similarly when a value is popped off the stack, the 8051 returns the value from the memory location indicated by SP, and then decrements the value of SP. Since the SP is only 8-bit wide it is incremented or decremented by two.

SP is modified directly by six instructions: PUSH, POP, ACALL, LCALL, RET, and RETI. It is also used intrinsically whenever an interrupt is triggered.

Stack The CPU needs this storage area as there are only limited number of registers. It is a part of RAM used by the CPU to store information temporarily. This information may

be either data or address. The register used to access the stack is called the Stack Pointer which is an 8-bit register.

So,it can take values of 00 to FF H. When the 8051 is powered up, the SP register contains the value 07. It means the RAM

location value 08 is the first location being used for the stack by the 8051 controller. There are two important instructions to handle this stack.

1. PUSH: The loading of data from CPU registers to the stack is done by PUSH 2. POP: The loading of contents of the stack back into aCPU register is done by POP

In the above instructions the contents of the Registers R6 and R1 are moved to stack and they occupy the 08 and 09 locations of the stack. Now the contents of the SP are incremented by two and it is 0A.

Similarly POP 3 instruction pops the contents of stack into R3 register. Now the contents of the SP is decremented by 1.

In 8051 the RAM locations 08 to 1F (24 bytes) can be used for the Stack. In any program if we need more than 24 bytes of stack, we can change the SP point to RAM locations 30 - 7F H. This can be done with the instruction MOV SP , # XX.

Data Pointer Register (DPTR) It is a 16-bit register which is the only user-accessible. As the name suggests, DPTR is used to point to data. It is used by a number of commands which allow the 8051 to access external memory. When

the 8051 accesses external memory it will access external memory at the address indicated by DPTR.

DPTR can also be used as two 8-registers DPH and DPL.

Program Status Register (PSW) The 8051 has a 8-bit PSW register which is also known as Flag register. In the 8-bit

register only 6-bits are used by 8051. Two unused bits are user definable bits. In the 6-bits four of them are conditional flags. They are Carry - CY, Auxiliary Carry - AC,

Parity - P and Overflow - OV. These flag bits indicate some conditions that resulted after an instruction was executed.

The meaning of various bits of PSW register is shown below:

Bit Designation Bit Number Bit Function CY PSW.7 Carry Flag AC PSW.6 Auxiliary Carry Flag FO PSW.5 Flag 0 available for general purpose RS1 PSW.4 Register Bank select bit 1 RS0 PSW.3 Register bank select bit 0 OV PSW.2 Overflow flag --- PSW.1 User difinable flag P PSW.0 Parity flag; set/cleared by hardware The selection of the register Banks and their addresses are given below.

RS1 RS0 Register Bank Address

0 0 0 00H-07H

0 1 1 08H-0FH

1 0 2 10H-17H

1 1 3 18H-1FH

Special Function Registers (SFRs) Certain registers which use RAM addresses from 80h to FF H and they are meant for

certain specific operations. These registers are called Special Function Registers (SFRs). Some of these registers are bit addressable. Some of them are related to I/O ports (P0, P1, P2 and P3). Some of them are meant for control operations (TCON, SCON, PCON) Remaining are the auxillary SFRs, in the sense that they don't directly configure the 8051.

The list of SFRs and their functional names are given below. Sr. No. Symbol Name of SFR Address (Hex) 1 ACC* Accumulator 0E0 2 B* B-Register 0F0 3 PSW* Program Status word register 0DO 4 SP Stack Pointer Register 81 5 DPL Data Pointer - low byte 82

DPTR DPH Data Pointer - high byte 83 6 P0* Port 0 80 7 P1* Port 1 90 8 P2* Port 2 0A 9 P3* Port 3 0B 10 IP* Interrupt Priority control 0B8 11 IE* Interrupt Enable control 0A8 12 TMOD Timer Mode Register 89 13 TCON* Timer Control Register 88 14 TH0 Timer 0 - Higher byte 8C 15 TL0 Timer 0 - Lower byte 8A 16 TH1 Timer 1 - Higher byte 8D 17 TL1 Timer 1 - Lower byte 8B 18 SCON* Serial Control Register 98 19 SBUF Serial Buffer Register 99 20 PCON Power Control Register 87 The * indicates the bit addressable SFRs.

Ports of 8051 There are four ports P0, P1, P2, and P3. Each port uses 8 pins. All I/O pins are bi-directional. The four I/O ports:

o Port 0 (Pins 32-39): P0（P0.0~P0.7）

o Port 1 (Pins 1-8): P1（P1.0~P1.7）

o Port 2 (Pins 21-28): P2（P2.0~P2.7）

o Port 3 (pins 10-17): P3（P3.0~P3.7)

Each port has 8 pins. Named P0.X, P1.X, P2.X, P3.X; where (X=0,1,...,7)

o Ex: P0.0 is the bit 0 (LSB) of P0 o Ex: P0.7 is the bit 7 (MSB) of P0

These 8 bits form a byte. Each port can be used as input or output (bi-direction)

Port-0

Port-0 can be used as a normal bidirectional I/O port or it can be used for address/data interfacing for accessing external memory.

When control is '1', the port is used for address/data interfacing. When the control is '0', the port can be used as a bidirectional I/O port.

Port-0 as Normal Input Port Case I: Reading "High" on Pin P0.X (Control Pin=0) Internal CPU Bus (D Latch input)= 1 Output of D latch

Q=1 Q=0 which turns 'off' the lower FET while due to '0' control signal upper FET

also turns off Hence the output pin have floats hence "HIGH" data written on pin is directly read by read pin. Case II: Reading "LOW" on Pin P0.X (Control Pin=0) Internal CPU Bus(D Latch input)= 1 Output of D latch

Q=0 Q=1 which turns 'ON' the lower FET while due to '0' control signal upper FET is

turned off. Hence the output pin have floats hence "LOW" data written on pin is directly read by read pin.

PORT-0 as Normal Output Port Case I: Writing "High" on Pin P0.X (Control Pin=0) Internal CPU Bus(D Latch input)= 1 Output of D latch

Q=1 Q=0 which turns 'off' the lower FET while due to '0' control signal upper FET

also turns off. Here we want logic '1' on pin but we getting floating value so to convert that floating value into logic '1' we need to connect the pull up resistor parallel to upper FET. This is the reason why we needed to connect pull up resistor to port 0 when we want to initialize port 0 as an output port . Case II: Writing "LOW" on Pin P0.X (Control Pin=0) Internal CPU Bus(D Latch input)= 0 Output of D latch

Q=0 Q=1 which turns 'ON' the lower FET while due to '0' control signal upper FET is

turn off The pin is pulled down by the lower FET. Hence the output becomes zero.

PORT-0 as Address or Data Bus (When the control pin=1, address/data bus controls the output driver FETs.) Case I: Writing "LOW" on Pin P0.X If the address/data bus (internal) is '0',

Upper FET = OFF. Lower FET =ON. The output becomes '0'.

Case II: Writing "High" on Pin P0.X If the address/data bus (internal) is '0',

Upper FET = ON. The output becomes '1'. Lower FET = OFF.

Hence for normal address/data interfacing (for external memory access) no pull-up resistors are required. Port-0 latch is written to with 1's when used for external memory access.

PORT-1 The structure of a port-1 pin is shown in fig below.It has 8 pins (P1.1-P1.7).

PORT-1 as Normal Input Port Case I: Reading "High" on Pin P1.X Internal CPU Bus(D Latch input)= 1 Output of D latch

Q=1 Q=0 which turns 'off' the FET

Hence the output pin have floats hence "HIGH" data written on pin is directly read by read pin. Case II: Reading "LOW" on Pin P1.X

Internal CPU Bus(D Latch input)= 1 Output of D latch

Q=0 Q=1 which turns 'off' the FET.

Hence the output pins have floats and "LOW" data written on pin is directly read by read pin.

PORT-1 as Normal Output Port Case I: Writing "High" on Pin P1.X Internal CPU Bus(D Latch input)= 1 Output of D latch

Q=1 Q=0 which turns 'off' the lower FET

Hence at P1.X=VCC or logic '1' on pin . Case II: Writing "LOW" on Pin P0.X (Control Pin=0) Internal CPU Bus(D Latch input)= 0 Output of D latch

Q=0 Q=1 which turns 'ON' the lower FET

The pin is pulled down by the lower FET. Hence at P1.X = Ground or logic '0' on pin. Hence the output becomes zero.

PORT-2 The structure of a port-2 pin is shown in fig. below. It has 8-pins (P2.0-P2.7)

Port-2 we use for higher external address byte or a normal input/output port. The I/O operation is similar to Port-1. Port-2 latch remains stable when Port-2 pin are used for external memory access. Here again due to internal pull-up there is limited current driving capability.

PORT-3 Port-3 (P3.0-P3.7) has alternate functions to each pin. The internal structure of a port-3 pin is shown in figure below.

Alternate Functions of Port 3:

Bits P3.0 and P3.1 are used for the RxD (Receive Data) and TxD (Transmit Data) serial communications signals.

Bits P3.2 and P3.3 are meant for external interrupts. Bits P3.4 and P3.5 are used for Timers 0 and 1. Bits P3.6 and P3.7 are used to provide the write and read signals of external

memories connected in 8031 based systems Sr. No. Port 3 bit Pin No Function

1 P3.0 10 RxD 2 P3.1 11 TxD 3 P3.2 12 INT0

4 P3.3 13 INT1

5 P3.4 14 T0 6 P3.5 15 T1 7 P3.6 16 WR

8 P3.7 17 RD

Internal RAM Oganization This Internal RAM is found on-chip on the 8051 .So it is the fastest RAM available, and it is also the most flexible in terms of reading, writing, and modifying it’s contents. Internal RAM is volatile, so when the 8051 is reset this memory is cleared. The 128 bytes of internal RAM is organized as below.

1. Four register banks (Bank0,Bank1, Bank2 and Bank3) each of 8-bits (total 32 bytes). The default bank register is Bank0. The remaining Banks are selected with the help of RS0 and RS1 bits of PSW Register.

2. 16 bytes of bit addressable area and 3. 80 bytes of general purpose area (Scratch pad memory) as shown in the diagram

below. This area is also utilized by the microcontroller as a storage area for the operating stack.

The 32 bytes of RAM from address 00 H to 1FH are used as working registers organized as four banks of eight registers each.The registers are named as R0-R7 .Each register can be addressed by its name or by its RAM address. For EX : MOV A, R7 or MOV R7,#05H

Register bank to be selected using RS1,RS0 bits from Program status word register

Internal ROM:

Internal ROM occupies the code address space from 0000H to 0FFFH (Size = 4K byte)

Program addresses higher than 0FFFH will automatically fetch code bytes from external program memory

Code bytes can also be fetched exclusively from an external memory by connecting the external access pin (EA) to ground

External program memory interfacing with 8051

RS1 RS0 Register Bank RAM Address

0 0 Register Bank 0 (Slected as by default) 00H-07H

0 1 Register Bank 1 (Stack memory) 08H-0FH

1 0 Register Bank 2 10H-17H

1 1 Register Bank 3 18H-1FH

EA pin is active low input pin so if EA=0 or connected to ground the code bytes will be fetched from External Program memory

ALE(Address Latch Enable)= indicates the Adress Latch is enabled

External Data memory interfacing with 8051

EA pin is active low input pin so if EA=1 the code bytes will be fetched from External Data memory

ALE(Address Latch Enable)=1 indicates the Adress Latch is enabled

Interrupt Structure in 8051 Interrupts Programming

An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service.

Interrupts verses Polling: A single microcontroller can serve several devices. There are two ways to do that:

o Interrupts o Polling

The program which is associated with the interrupt is called the interrupt service routine (ISR) or interrupt handler

Steps in Executing an Interrupt

1. Finishes current instruction and saves the PC on stack. 2. Jumps to a fixed location in memory depending on the type of interrupt.

3. Starts to execute the interrupt service routine until RETI (return from interrupt) 4. Upon executing the RETI the microcontroller returns to the place where it was

interrupted. Get POP PC from stack.

Interrupt Vector Table

Each interrupt has a specific place in code memory where program execution (interrupt service routine) begins.

It is the set of memory locations set aside in the program memory which points at the ISR of different interrupts

Interrupt Service Routine

It is the program associated with the perticular interrupt whose starting memory location is pointed by IVT table address.

The following table shows interrupt vector table:

Interrupt Enable (IE) register All interrupt are disabled after reset. We can enable and disable them by Interrupt Enable (IE) register.

IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0

EA - ET2 ES ET1 EX1 ET0 EX0

Functional name Bit number Function

EA IE.7 Disables all interrupts

- IE.6 No implemented,Reserve for future

ET2 IE.5 Enables or disables Timer 2 overflow flag interrupt

ES IE.4 Enables or disables Serial communication interrupt

ET1 IE.3 Enables or disables Timer 1 overflow flag interrupt

EX1 IE.2 Enables or disables Timer 2 overflow flag interrupt

ET0 IE.1 Enables or disables Timer 2 overflow flag interrupt

EX0 IE.0 Enables or disables Timer 2 overflow flag interrupt

Enabling and disabling an interrupt

By bit operation; recommended in the middle of program. SETB EA ;Enable All SETB ET0 ;Enable Timer0 ovrflow

Type of Interrupt PROM location

Reset 0000H

External Interrupt 0 0003H

Timer 0 Overflow 000BH

External Interrupt 1 0013H

Timer 1 Overflow 001BH

Serial Communication Interrupt 0023H

Timer 2 Overflow (8052+) 002BH

Note: That there are only 8 memory locations between vectors.

SETB ET1 ;Enable Timer1 ovrflow SETB EX0 ;Enable INT0 SETB EX1 ;Enable INT1 SETB ES ;Enable Serial port

By mov instruction; recommended in the initial section of program. MOV IE, #10010110B

Example A 10 KHz square wave with 50% duty cycle: ORG 0 ;Reset entry poit LJMP MAIN ;Jump above interrupt ORG 000BH ;Timer 0 interrupt vector T0ISR:CPL P1.0 ;Toggle port bit RETI ;Return from ISR to Main program ORG 0030H ;Main Program entry point MAIN: MOV TMOD,#02H ;Timer 0, mode 2 MOV TH0,#-50 ;50 us delay SETB TR0 ;Start timer MOV IE,#82H ;Enable timer 0 interrupt SJMP $ ;Do nothing just wait Write a program using interrupts to simultaneously create 7 kHz and 500 Hz square waves on P1.7 and P1.6.

ORG 0 LJMP MAIN ORG 000BH LJMP T0ISR ORG 001BH LJMP T1ISR ORG 0030H MAIN: MOV TMOD,#12H MOV TH0,#-71 SETB TR0 SETB TF1 MOV IE,#8AH MOV IE,#8AH SJMP $ T0ISR: CPL P1.7 RETI T1ISR: CLR TR1 MOV TH1,#HIGH(-1000) MOV TL1,#LOW(-1000) SETB TR1 CPL P1.6

RETI END

Timer ISR

There is no need for a “CLR TFx” instruction in timer ISR. 8051 clears the TF internally upon jumping to ISR. We must reload timer in mode 1. There is no need on mode 2 (timer auto reload)

Interrupt Priorities What if two interrupt sources interrupt at the same time?

The interrupt with the highest PRIORITY gets serviced first. All interrupts have a power on default priority order.

External interrupt 0 (INT0) Timer interrupt0 (TF0) External interrupt 1 (INT1) Timer interrupt1 (TF1) Serial communication (RI+TI)

Priority can also be set to “high” or “low” by IP reg.

Interrupt Priorities (IP) Register IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0

- - PT2 PS PT1 PX1 PT0 PX0

Bit Designation Bit Number Function

- IP.7 reserved

- IP.6 reserved

PT2 IP.5 timer 2 interrupt priority bit (8052 only)

PS IP.4 serial port interrupt priority bit

PT1 IP.3 timer 1 interrupt priority bit

PX1 IP.2 external interrupt 1 priority bit

PT0 IP.1 timer 0 interrupt priority bit

PX0 IP.0 external interrupt 0 priority bit

Timers/Counters Specifications

Two 16 bit timers/counters, which can be programmed independently as - timer or event counter.

Four-SFRs connected with TIMER/COUNTER operation 1. TMOD - Timer Mode Register 2. TCON - Timer Control Register 3. TH0, TL0 - Timer/Counter - 0 4. TH1, TL1 - Timer/Counter - 1

Two pins of 8051 connected with Timer/counter. 1. T0 - Timer 0 external input - P3.4 2. T1 - Timer 1 external input - P3.5

INT0 and INT1 are also used for controlling the timers/counters.

Timer Operation

Timer Register (TH0, TL0 or TH1, TL1) incremented every m/c cycle. Thus working at increment frequency of 1/12 of oscillator frequency (for 12 oscillator machine cycle).

Any preset value i.e. initial count can be loaded to TH0, TL0 or TH1, TL1. Example:

Clock frequency = 11.0592 MHz, Clock period = 1/12 µ sec, Machine cycle time = 1.08 µ sec Thus timer register will be incremented every microsecond. If timer is initialized to 0000H; max. count = FFFFH and max. time measured = 65536 * 1.08 µ sec= 70.77 milliseconds

Counter Operation Counts pulses occurring at T0 pin (Timer/Counter 0) and/or T1 pin (Timer/Counter 1). May correspond to event like

Passing of railway coach from a point - axle counter Rotation of speedometer cable

o speedometer of vehicle Number of persons visiting exhibition.

T0, T1 scanned every m/c cycle nth m/c cycle – T1 or T0 = High (n+1)th m/c – T1 or T0 = Low Timer 0 or timer 1 incremented in (n+1)th m/c cycle Count frequency = min 2 m/c cycle per count T0- P3.4, T1- P3.5

Timer Mode Control Register - TMOD 7 6 5 4 3 2 1 0

G C/T M1 M0 G C/T M1 M0

M1 and M0 specify the mode as follows: M1 M0 Mode Description in brief

0 0 Timer in mode0 13-bit Timer/counter

0 1 Timer in mode1 16-bit Timer/counter

1 0 Timer in mode2 8-bit Timer/counter with autoreload

1 1 Timer in mode3 Split Timer 0 into two 8-bit counters or to stop Timer 1

If C/T = 1, the timers function as counters to count the negative transitions at T0 or T1 pins.

If C/T = 0, the timers function as timers, that is, they basically count the number of machine cycles.

Gate = 0 means that the timer is controlled by TR1 or TR0 only, irrespective of INT0 or INT1.

Gate = 1 means that the timer control will depend on INT0 or INT1 and also on TR0 or TR1 bits

When data is written it gets latched. TMOD is used for setting mode bits M1, M0, Gate bit and C/T for Timer 0 and Timer 1.

Bit 0 to 3 for Timer 0. Bit 4 to 7 for Timer 1.

Timer Control Register - TCON 7 6 5 4 3 2 1 0

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Bit 0 to 3 – used for interrupt functions Bit 4 to 7 – used for setting TR0, TR1 by software Setting TF0, TF1 by counter i.e. hardware When count rolls from all 1’s to all 0’s.

TF1: Timer 1 overflow flag. Set by hardware when the timer/counter overflows. Cleared by hardware when the processor vectors to the interrupt routine.

TR1: Timer 1 run control bit. Set/cleared by software to turn the timer/counter on/off.

TF0: Timer 0 overflow flag. Set by hardware when the timer/counter overflows. Cleared by hardware when the processor vectors to the interrupt routine.

TR0: Timer 0 run control bit. Set/cleared by software to turn the timer/counter on/off.

As value in Timer register rolls from all ones (i.e. FFFFH) to all zero’s (i.e. 0000H) interrupt flag (TF0 or TF1) will be set.

TF0 (for Timer 0) and TF1 (for Timer 1) are bits of TCON SFR. IF Timer 0 or Timer 1 interrupt is enabled then program control will branch to

interrupt servicing routine as shown in figure below

Modes are set by M1 M0 bits of TMOD register.

Mode 0: 13 bit Timer/Counter operation

TH0, TL0 (for Timer 0) or TH1, TL1 (for Timer 1) used as 13 bit counter. o All 8 bits of TH0 or TH1 o 5 lower bits of TL0 or TL1 are used, for counting.

When count rolls over from all 1’s to all 0’s, - interrupt flag TF0 or TF1 is set.

In above figure when C/T = 0 - timer operation count incremented every m/c cycle.

o Case I: TR0 (TCON. 4) or TR1 (TCON. 6) = 1 and Gate (TMOD. 3) or (TMOD. 7) = 0

o Case II: TR0 or TR1 =1 and Gate = 1 and INT0 or INT1 = 1 Thus by sending Logic High signal on INT0 (or INT1) pins.Timer 0 or Timer 1 can

be started. Example: This can be used for finding pulse width in the following way.

C/T = 0 – Timer operation TR0 or TR1 = 1 Gate = 1 Source of pulse connected to INT0 or INT1 pin

When pulse goes high: timer starts counting at the rate 1/12 clock frequency. When pulse goes low: Timer stops. INT0 or INT1 = Low: causes interrupt.

ISR can read the timer value. ISR can store the timer value and process it as required by the application

Mode 1: 16 bit Timer/Counter operation

Operation same as mode 0 except that all bits of TH0, TL0 or TH1, TL1 are used. When count rolls over from all 1’s to all 0’s – TF0 or TF1 interrupt flag is set. Causes interrupt if enabled.

Mode 2: 8 bit auto-reload Timer/Counter

Only TL0 or TL1 are used. That is 8 bit counting. Initial preset value is loaded to TH0 or TH1 by software. The value is loaded to TL0 or TL1 by hardware automatically before it starts

counting. When count rolls from all 1’s (i.e. FFH) to all 0’s (i.e. 00H)

o TF0 or TF1 flag is set o Preset value in TH0 or TH1 is reloaded to TL0 or TL1 o Operation i.e. Counting starts automatically.

Mode 3: Split Timer/Counter operation

When Timer 0 is put in mode 3:

It acts as two 8 bit counters, i.e. TL0 and TH0 become two separate counter. TL0: 8 bit operation in mode 0 or mode 1 (Timer or Counter); controlled by C/T, TR0, Gate, INT0.

Sets TF0 when count rolls to all 0’s from all 1’s. TH0: Timer function only.

Controlled by TR1 i.e. starts when TR1 = 1. When count rolls to all 0’s from all 1’s – TF1 flag is set. Note: TR1 and TF1 are used in Timer 0 (TH0) even though they are bits for Timer 1. When Timer 1 is put in mode 3 it just holds the preset count same as TR0 = 0, i.e. opening the switch. [Modes 0, 1 and 2 are mostly used.]

Steps for Timer Programming

I. Load the TMOD register indicating which timer is to be used II. Load the timer register TLx and THx with initial count values

III. Start timer using instruction SETB TRX or SETB TCON.6 or SETB TCON.4 IV. Keep monitoring Timer flag with the instruction Here: JNB TFx, Here V. Get out of loop when TFx becomes high

VI. Stop the timer VII. Clear the Timer overflow flag

Example: a. Configuring Timer/Counter using TMOD

7 6 5 4 3 2 1 0

G C/T M1 M0 G C/T M1 M0

TMOD = 0000 0101 = 05H, hence:

MOV TMOD, #05H Timer 1: TIMER Mode = 00 (13 bit operation) Timer 0: Counter Mode = 01 (16 bit operation)

b. To load initial count as preset value Work out the preset value = ABCDH - Timer 0 Load the preset value = 0000H - Timer 1 MOV TL0, #CDH MOV TH0, #ABH MOV TL1, #00H MOV TH1, #00H c. Start Timer/Counter through TR0, TR1 bits from TCON

7 6 5 4 3 2 1 0

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Make TR0 = 1, TR1 = 1 TCON = 0101 0000 = 50 H MOV TCON, #50H or SETB TCON.4 or SETB TCON.6 d. When count value in Timer Register transits from all 1’s to all 0’s Following tasks need to be done.

Preset value to be loaded to Timer Register Timer interrupt flag (TF0 or TF1) to be cleared

Example 1: Generate a square wave of 50% duty cycle at pin p1.7. Use Timer 1 to generate time delay. Clock frequency = 12 MHz, 12 oscillator clock. Pulse width = 50 millisecond. Solution: Let us work out the initial preset value.

1 m/c cycle = 1 microsecond 50 millisecond = 50,000 m/c cycle FFFF = 65535 Difference = 65535 - 50000 = 15535 m/c cycle

Since count will roll from FFFF to 0000 additional m/c cycle will be required to set TF0 or TF1.

Thus initial count must be 15536 = 3CB0H By putting initial preset count of 3CB0H (or 15536 decimal), the register will

reach FFFF in 49999 m/c cycle and roll over to 0000 in 50,000th m/c cycle accounting for 50 millisecond

a. Configure Timer 1 using TMOD register

G C/T M1 M0 G C/T M1 M0 0 0 0 1 0 0 0 0

Gate = 0, C/T = 0, Mode = 01 (16 bit timer operation) MOV TMOD , # 10H Make P1.7 = Low initially CLR P1.7

b. Load Preset Value KK: MOV TL1, #B0H MOV TH1, #3CH c. Complement P1.7 CPL P1.7 d. Start Timer 1 (TR1 = 1) using instruction SETB TCON.6 or SETB TR1 e. Check for TF1=1 in loop using instruction JNB TCON.7, $ f. TF1=1, Make TF1=0 using instruction CLR TCON.7 g. Stop Timer 1 Make TR1=0 using instruction CLR TCON.6 h. SJMP KK

Program ORG 00H MOV TMOD,#10H CLR P1.7 BACK:MOV TL1,#B0H MOV TH1, #3CH CPL P1.7 ACALL TDELY SJMP BACK TDELY: SETB TCON.6 JNB TCON.7, $ CLR TCON.7 CLR TCON.6 RET

Example 2: Write an ALP to generate delay of 3 ms using timer 0. Clock frequency = 16 MHz.Also find out the value to be loaded in TH0,TL0 register. Solution:

1 m/c cycle frequency = 16MHz/12 = 1.33 MHz 1 m/c cycle time period = 1/f = 0.75 µ sec Time Delay required = 3milli seconds 1 m/c generates delay of ----- 0.75 µsec How many machine cycles(x) required to generate delay of 3 millisec

=

We will assume Timer0 in mode1 (16 -bit timer) TMOD = 01H Initial Value = 65536 - 4000 = 62536 whose Hexadecimal value is F448H.

Hence TH0 and TL0 becomes: TH0 = 0F4H and TL0 = 48H. ORG 00H MOV TMOD,#01H BACK:MOV TL0,#0F4H MOV TH1, #48H

ACALL TDELY SJMP BACK TDELY: SETB TR0 Here:JNB TF0,Here CLR TF0 CLR TR0 RET

Serial Communication in 8051 Basics of Serial Communication

Computers transfer data in two ways:

Serial data communication uses two methods

Synchronous method transfers a block of data at a time

Asynchronous – Start & Stop Bit

Asynchronous serial data communication is widely used for character-

oriented transmissions o Each character is placed in between start and stop bits, this is

called framing. The start bit is always one bit, but the stop bit can be one or two bits The start bit is always a 0 (low) and the stop bit(s) is 1 (high)

Data Transfer RateThere are special IC’s made by many manufacturers for serial

communications. o UART (universal asynchronous Receiver transmitter) o USART (universal synchronous-asynchronous Receiver-transmitter)

The rate of data transfer in serial data communication is stated in bps (bits per second).

Another widely used terminology for bps is baud rate. Serial port of 8051 is full duplex, means it can transmit and receive

simultaneously.

Interfacing of 8051 to PC using Serial communication A personal computer has a serial port known as communication port or COM Port used to

connect a modem for example or any other device, there could be more then one COM Port in a PC. Serial ports are controlled by a special chip called UART (Universal Asynchronous Receiver Transmitter). RS 232 standard describes a communication method where information is sent bit by bit on a physical channel. The RS stands for Recommended Standard.The information must be broken up in data words. The length of a data word is variable. It is one of the popularly known interface standard for serial communication between DTE & DCE. This RS-232-C is the commonly used standard when data are transmitted as voltage .This standard was first developed by Electronic industries association(EIA). For the RS-232C, a 25 pin D type connector is used . DB-25P male and DB-25S female. RS-232 standard was first introduced in 1960’s by Telecommunications Industry Association(TIA). As the RS-232 standard is developed earlier to TTL devices ,a USART such as 8251 is not directly compatible with these signal levels .Because of this ,voltage transistors called line drivers and line receivers are used to interface TTL logic with RS-232 signals . The line driver MC 1488 is used to convert RS-232 to TTL.The microcontroller is connected to the PC using the DB9 connector.

The TxD and Rx D pins are connected to the TI in and RI in pins of the MAX 232 IC and the TI out and RI in pins of the MAX IC are connected to the RxD and TxD pins of the DB9 connector as shown in the interface diagram

Baud Rate:-The rate at which the number of bits are transmitted PC and microcontroller supports various types of Baud rates eg. 19200,9600,4800,2400,1200 etc

where

TH1=Value to be loaded in TH1 register k=1 when SMOD=0 from PCON register

k=2 when SMOD=1 from PCON register o XTAL freq=11.0592 MHz

8051 Registers related to Serial Communication 1. SBUF Register -- to hold data 2. SCON Register -- controls data communication 3. PCON Register -- controls data rates

SBUF Register SBUF is an 8-bit register used for serial communication. For a byte data to be transferred via the TxD line, it must be placed in the SBUF

register. The moment a byte is written into SBUF, it is framed with the start and stop bits

and transferred serially via the TxD line. SBUF holds the byte of data when it is received by 8051 RxD line. When the bits are received serially via RxD, the 8051 deframes it by eliminating

the stop and start bits, making a byte out of the data received, and then placing it in SBUF.

NOTE: SBUF is physically two registers . one is write only and is used to hold data to be transmitted out of the 8051 via TXD. The other is read only and holds received data from external sources via RXD. Both mutually exclusive registers use address 99h.

Serial Port Control (SCON) Register Structure

Description

SMO,SM1 bits

8051 Serial Port – Mode 0 The Serial Port in Mode-0 has the following features:

1. Serial data enters and exits through RXD 2. TXD outputs the clock 3. 8 bits are transmitted / received 4. The baud rate is fixed at (1/12) of the oscillator frequency

8051 Serial Port – Mode 1 The Serial Port in Mode-1 has the following features: Serial data enters through RXD Serial data exits through TXD On receive, the stop bit goes into RB8 in SCON 10 bits are transmitted / received

1. Start bit 2. Data bits (8) 3. Stop Bit

Baud rate is determined by the Timer 1 over flow rate. Standard UART data word under mode-1

8051 Serial Port – Mode 2 The Serial Port in Mode-2 has the following features:

1. Serial data enters through RXD 2. Serial data exits through TXD 3. 9th data bit (TB8) can be assign value 0 or 1 4. On receive, the 9th data bit goes into RB8 in SCON 5. 11 bits are transmitted / received

1. Start bit 2. Data bits (9) 3. Stop Bit

6. Baud rate is programmable

8051 Serial Port – Mode 3 The Serial Port in Mode-3 has the following features:

1. Serial data enters through RXD 2. Serial data exits through TXD 3. 9th data bit (TB8) can be assign value 0 or 1 4. On receive, the 9th data bit goes into RB8 in SCON 5. 11 bits are transmitted / received

1. Start bit 2. Data bits (9) 3. Stop Bit

6. Baud rate is determined by Timer 1 overflow rate.

Programming 8051 to transmit/receive data serially Step I: The TMOD register is loaded with value=20H indicating Use of Timer1 in mode 2 i.e 8-bit Auto-reload Step II: TH1 register is loaded with one of the values to set the baud rate for serial

communication Step III: The SCON register is loaded with the value

MOV SCON, #40H ;indicating serial mode 1 MOV SCON, #50H ;indicating serial mode 1, Reception enable

Step IV: Start timer1 with instruction setb TR1 Step V:

Here: JNB TI, Here ;The TI flag bit is monitored with the use of instruction Here: JNB RI, Here ;The RI flag bit is monitored with the use of instruction

Step VI: Clear TI flag before transmission of next character

Write an ALP for 8051 to transmit letter 'A' serially at the baud rate 4800 continuosly org 00H MOV TMOD,#20H MOV TH1,#-6 MOV SCON,#40H SETB TR1 Again: MOV SBUF,#'A' Here:JNB TI,Here clr TI sjmp Again

Doubling Baud Rate There are two ways to increase the baud rate of data transfer

1. By using a higher frequency crystal 2. By changing a bit in the PCON register

Power Mode Control (PCON) Register PCON register is an 8-bit SFR. It is byte addressable register.

SMOD: double baud rate bit. When 8051 is powered up, SMOD bit is at zero value. To double the baud rate SMOD to be set to 1.

Structure of SCON Register

Description

Significance of SMOD bit from PCON Register