Block-SubSystem-OVM_ver2

8/7/2019 Block-SubSystem-OVM_ver2

1/11

Integrating OVM Components

into Testbenchs

Best Practices for Vertical

Integrations


2/11

Integration Pitfalls

Duplication of interface related logic could result indoubling (or worse) our samples per clock edge.

Multiple OVM Toplevels within a given architecturecan lead to multiple ovm_top instances potentially

confusing the set_config process Having OVM instantiated in the same hierarchy as the

DUT means that any change in OVM code results inunnecessarily recompiling the DUT code as well


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class w_block_test1 extends ovm_test;

w_block_tb1 w_tb;

...

virtual function connect();

w_tb.a_ovc.assign_vi();w_tb.b_ovc.assign_vi();

w_tb.c_ovc.assign_vi();

endfunction : connect

endclass : w_block_tb1

DUT ToplevelOVM Test (OVM Toplevel)

class w_block_tb1 extends ovm_env;

interface_a_ovc a_ovc;

interface_b_ovc b_ovc;

interface_c_ovc c_ovc;

module_w_ovc w_ovc;

...


a_ovc.analysis_port.connect(w_ovc.a_imp);

b_ovc.analysis_port.connect(w_ovc.b_imp);

c_ovc.analysis_port.connect(w_ovc.c_imp);



Block W OVM Testbench

Interface A OVC

Module W OVC

Interface B OVC

Interface C OVC

DUT WA

B

C

Interface

Registry

NEED DEMO CODE HERE FOR DUT Top Level!!!

BlockW

Ar

chitecture


4/11

class x_block_test1 extends ovm_test;

x_block_tb1 x_tb;

...


x_tb.a_ovc.assign_vi();x_tb.b_ovc.assign_vi();

x_tb.c_ovc.assign_vi();


endclass : x_block_tb1


class x_block_tb1 extends ovm_env;




module_w_ovc w_ovc;

...







Block X OVM Testbench

Interface B OVC

Module X OVC

Interface D OVC

Interface C OVC

DUT XD

B

C

Interface

Registry

NEED DEMO CODE HERE FOR DUT Top Level!!!

BlockX

Architecture


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OVM Test (OVM Toplevel)


Interface B OVC

Module X OVC

Interface D OVC

Interface C OVC


Interface A OVC

Module W OVC

Interface B OVC

Interface C OVC

DUT Toplevel

DUT WA

B

C

Interface

Registry

Sub-Sy

stem

Architect u

re

DUT XD

B

CTHE

WRON

G

WAY


6/11

Unnecessary Duplication

By copying the block level testbench

OVCs into the Sub-System environment,

weve duplicated the shared interface

OVCs

Every sample is now doubled

BOTH interface OVCs need to be connected

to the interface registry


7/11


DUT WA

B

C

Interface

Registry

Sub-Sy

stem

Architect u

re

DUT XD

B

C

THE RIGHT WAY

Sub-System OVM Testbench

Sub-System OVC

Module X OVC

Interface D OVC

Interface A OVC

Module W OVC

Interface B OVC

Interface C OVC


8/11

class subsystem_ovc extends ovm_env;



module_w_ovc w_ovc;

module_x_ovc x_ovc;

ovm_analysis_export #(A_SEQ_ITEM) a_export;

ovm_analysis_export #(D_SEQ_ITEM) d_export;

...



b_ovc.analysis_port.connect(x_ovc.b_imp);


c_ovc.analysis_port.connect(x_ovc.c_imp);

a_export.connect(w_ovc.a_imp);

d_export.connect(x_ovc.d_imp);


endclass : subsystem_ovc

class subsystem_tb extends ovm_env;


interface_f_ovc f_ovc;

subsystem_ovc sub_ovc;

...


a_ovc.analysis_port(sub_ovc.a_export);

f_ovc.analysis_port(sub_ovc.f_export);


endclass : subsystem_tb

You can avoid burrowing into an ovc

by using TLM exports

Sub-System OVC


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OLD SLIDES

AFTER THIS ONE


10/11

class w_block_tb1 extends ???;




module_w_ovc w_ovc;

...







class x_block_tb1 extends ???;


interface_d_ovc b_ovc;

module_x_ovc x_ovc;

...



d_ovc.analysis_port.connect(w_ovc.d_imp);




Interface A OVC

Module W OVC

Interface B OVC

Interface C OVC


Interface B OVC

Module X OVC

Interface D OVC

DUT WA

B

C

DUT XB D

C

Interface C OVC


11/11

Sub-System DUTSub-System OVM Testbench

Sub-System Level OVC Instantiation

DUT WA

B

C

DUT XB D

Sub-System OVC

Module W OVC

Interface B OVC

Interface C OVC

Module X OVC

Interface A OVC

Interface D OVC

Documents

Block-SubSystem-OVM_ver2