Bob Hirosky, UVa 7/27/01 Level 2 Processor Status Bob Hirosky The University of Virginia

Bob Hirosky, UVa 7/27/01

Level 2 Processor StatusLevel 2 Processor Status

Bob Hirosky

The University of Virginia


L2 Alpha BoardL2 Alpha BoardCommissioningCommissioning

• First Production2/2 pre-production work7/24 production came up (~9 months effort

UIC/UM/FNAL)– Most: multiple vias fixed and a

BGA replaced

– 17 abandoned• Broken CIA BGA not

replaceable (center of board)

– DMA patches (wires, pin lifting) performed

– PIO to Alpha not working (firmware)Aug/Sept

• concentrate on 1 Alpha/crate

Today’s score

6 up; 3 down (2 in ICU)

But 2 are pre-pro!6/7 “good” production boards are fragile


L2 Alpha BoardL2 Alpha BoardCommissioningCommissioning

•Second Production ( 2 samples ):•DMA fixes incorporated in layout

•Moved CIA BGA to a socket

–Risky, but can’t replace this BGA if it fails

•new supplier for raw boards

•better assembly (failures diagnosed; site visits)

–DØ pre-production at FNAL – no prompt

–UM board up/down CIA SOCKET PROBLEMS

–11 to follow: earliest mid-SeptemberProbable

decisi

on:

Drop sock

et, ris

k

Mountin

g CIA


I !like Ike!


baseline 1st year "minimum" min commissionTest Stand Crate 1 2 2 2 2 "global"Test Stand Crate 2 3 3 3 3 "multiprocessor"Test Stand Crate 3 2 2 0 0 2nd preprocessor testTest Stand Crate 4 0 0 0 0 data source uses prototypesGlobal 2 2 2 2Cal 4 4 4 0 OctPS 3 3 2 0 Sept?CTT 4 2 2 0 min is no stt; L1 in Sept?Mu 4 4 2 2 one crate; L1 in Junetotal 24 22 17 9 imaginable partial production

spare/extra power 14 16 21 2938 38 38 38

pre-production 2 2 2 2 as good as final cardsspare parts 10 10 10 10 but some needed by CDF tooold prototypes 2 2 2 2 useable for testing

We don't have enough parts to build the system twice.Could build all baseline workers twice

Administrators:test stand 3real system 6

total admin 9 9 7 4workers 15 13 10 5

How many Alphas?15 + test stand in 2001

•Need 15 for nominal system (+7 for test stand)

Min. Commissioning~ 9 boards


Where do we put our Alphas?Staging; rotating tests

Aug-Sept (6 to 10 s)• 1 Maryland• 2 Test Stand/UIC• 2 Global• 2 Mu/Cal (turns?)

• 3 in dry dock

Oct (6 to20 s) 2 Test stand 2 Global 2-4 Mu 2-4 Cal 2-5 CTT,PS

1-4 UIC/Test Stand


Online Software ( & to do) • Alpha:

– Much of structural software exists in simulation• Control/data flow for preprocessor and global

– Loader and modified Linux kernel– Hardware drivers in EBSDK / Linux– Draft drivers/setup for MBT and event loop testing

• Some alpha firmware problems?• SCL_INIT, and DAQ interface

– VME driver, buffer allocation • VBD/L3 readout works at test stand; need real SCL/MCH

– Error logging and beginnings of monitoring: testing– Downloading, release to Worker – Admin/Worker control; data flow

• Due to dearth of Alphas, concentrate on 1-alpha crate


Not all bad news:

Alphas supplies are tight, but the system is coming together

Online software is a big job and we have dug up enough boards to allow progress in this area.


DMA/PIO

ECL drivers 500 MHz SBC

VME Interface

L2 Alpha Board

Biggest difficulties inSBC section of board

Mfg. ProblemsObsolete partsDebugging difficulty

Separate SBC and IO


Initially proposed Oct 2000 Baden/Hirosky

-Minimize exposure to SBC difficulties-Remove dependence on short lifetime products-Maintain compatibility w/ Alpha

B. Hirosky 10/17/00

‘L2ßeta’ CPU Concept Commercial6U CPUCardW/ UII on board

FPGAMBUS P I/O + DMAECL Latch Driver

MBUSStraight pass to VME

Latches + ECL Drivers

Cable to PMC/PCI


L2eta people:Bob Hirosky: UVa (Management, specs., device software Alpha transparency)Pierre Petroff, Philippe Cros, Bernard Lavigne: ORSAY(Management, engineering, 9U board production, prototype$)Drew Baden: UMD (Functional reqs., 1st round designs)

Initially proposed Oct 2000 Baden/Hirosky

-Minimize exposure to SBC difficulties-Remove dependence on short lifetime products-Maintain compatibility w/ Alpha

B. Hirosky 10/17/00

‘L2ßeta’ CPU Concept Commercial6U CPUCardW/ UII on board

FPGAMBUS P I/O + DMAECL Latch Driver

MBUSStraight pass to VME

Latches + ECL Drivers

Cable to PMC/PCI

L2eta “group” formed in Jan 2001


6U boardCompact PCI

9U board64 bit

<2MHzVME

FPGA

EC

L D

rive

rs

128 bits~20 MHzMBus

32 bits66 MHz (max)Local bus64 bits

33 MHzPCI

J1

J2

J3

J5

J4

PLX9656

UII

Dri

vers

Dri

vers

Clk(s)/roms

•PIII Compact PCI card

•9U card with “custom” devices (3 BGA’s)

–Universe Chip VME interface

–commercial 64-bit PCI interface chip

–MBus and other logic in FPGA

Basic Idea


SBC •Single/Dual PIII up to 933MHz•64-bit, 66MHz PCI•Mech. shock tolerance 50g for transit (immune to ‘Eisenhower effect’?)


6U boardCompact PCI

9U board64 bit

<2MHzVME

FPGA

EC

L D

rive

rs

128 bits~20 MHzMBus

32 bits66 MHz (max)Local bus64 bits

33 MHzPCI

J1

J2

J3

J5

J4

PLX9656

UII

Dri

vers

Dri

vers

Clk(s)/roms

IDE

Mechanical view of a L2eta processor

SPY


•3x CPU performance + >2x on chip cache•DMA BIST•Additional P2 I/O pins available (~8)•More control in interrupt/reset logic

CPU/MHz Specint95 Specfp95

Alpha/500 ~15 ~21

PIII/850 ~41 ~35

PIII/933 ~45 ~39

I/O Performance

Alpha ~100 MB/s

MBT ~160 MB/s

L2eta ~200 MB/s

SBC ~500 MB/s

New/Improved features:

Cheap upgrade = add 2nd CPU


PLX9656

ECL

Secondary PCI BUS

J1

UII PIO DMA TSI

pcidev

API

HardwareInterface

Tundra

UIIB

J2

J3

PCI Front End64bit Master/Target

Add-on Bus

MDusAD/DA

VMEnode

FIFOsMBus

A/D + Control

Bridgedevice

Scalernode

Add-onBus Interface

Linux

-software compatibility!-programmer conservation

PLX CFG ROM

Xilinx FPGA/Veralog


Schematics delivered July 24

Layout starts now

Full mechanical designs in September

Fulltime firmware development starts September


Production/Assembly

Assembly by Thomson (Thales) of France• produce PCB (subcontract)• assemble components• component acquisition under study• design/manufacture of mechanical components

• rails for 6U card• stiffeners for 9U card• front panel (ORSAY design)(Mech. drawings in early September)

• electrical testing (JTAG scans)•Xilinx / PLX / UII support interface


Cost to build L2eta system

9U PCB + Mech. $1200

9U Components $1050

9U Assembly $200

9U Total $2450

SBC $3000

Production prototypes (2)

$12,500

30 boards ~$165,000

~$5450/board


Schematics - NowLayout – October 2001Device driver API – November 2001Firmware – December 2001Prototypes – December 2001 Hardware Integration – Feb 2002System Integration - March 2002Begin production – March 2002

Schedule

L2beta web site from L2 HARDWARE pageorhttp://galileo.phys.virginia.edu/~rjh2j/l2beta

Documents

Bob Hirosky, UVa 7/27/01 Level 2 Processor Status Bob Hirosky The University of Virginia