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VRM Modeling: A Strategy to Survive the Collision of Three Worlds Steve Sandler, Picotest, Larry Smith, Eric Bogatin, Teledyne LeCroy
An Overall Perspective The typically overstressed product manager is ultimately responsible for ensuring the final product works. Just engineering the power distribution network (PDN) can be a challenge when the three elements of the PDN have to be integrated together: the voltage regulator module (VRM), the interconnects and passive elements, and the power consuming elements. How can the product manager be confident, before the product is built, that all the PDN elements will play well together and meet the product performance specs, margin tests, and cost targets in all operating conditions?
One practical approach is to use some level of modeling for each element. This allows analysis of nominal and worst-case situations and, if necessary, exploration of alternative designs before final design decisions are made. An added benefit of this approach is that each design group can examine the models of the other elements and gain an understanding of how their element might interact with the rest of the system.
Selecting a model to use for each element in the PDN requires establishing a dynamic balance between acceptable simulation accuracy and the costs in effort, expertise, time, risk, and dollars required to attain that accuracy.
Although more detailed and accurate models of each element may increase the accuracy of the simulations, higher accuracy comes at some cost. Generally, the more accurate the model, the more complex it is, the more expertise is required to use it correctly, the more time it might take to run through scenarios, and the more difficult it might be to debug the results and build confidence in their accuracy.
If the model is so complex that only a few experts can understand it and use it without introducing artifacts, the risk of generating inaccurate results is high when less-experienced engineers use the model. On the other hand, if the model is so simple that it does not include features that might affect performance dramatically, it would have little value.
This paper reviews four levels of VRM models that VRM designers, board level interconnect designers, semiconductor designers, and product managers often use to explore design tradeoffs throughout the PDN system. The choice of which one to use involves considering engineers’ levels of expertise and what problems they expect to analyze. Some tradeoffs and relative merits of the models are described.
The Simplest VRM Model: An Ideal Voltage Source The simplest VRM model is an ideal voltage source. This model has zero output resistance and is the worst model to use in any context because it does not predict any of the most important PDN noise behaviors.
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Unfortunately, an ideal voltage source is used to represent the VRM in many time domain power integrity (PI) simulations. The problem with the ideal voltage source is that it has zero impedance and shorts out (DC and AC) any PI component it is across.
We have attended many design reviews and found that this tendency of attaching an ideal voltage source as the VRM to the rest of the PDN is all too common. It is an unfortunate mistake made by many PI engineers. It is very important that ideal voltage sources are never used alone as the VRM model in PDN simulations, especially when impedance or transient responses to fast step current loads are being evaluated.
A First-Order Linear RL Model for a VRM The simplest linear model that represents the VRM output impedance behavior, and is commonly used for frequency domain simulations, is a series RL model. This model has the advantage of being easy to implement and accounts for some of the interactions of the VRM with the rest of the PDN, from the die’s perspective, when simulating Vdd self-aggression noise. Of course, this simple model cannot begin to address the non-linear, stability, noise ripple, and saturation properties of a real VRM.
Figure 1: RL model for VRM.
As illustrated in Figure 1, the output impedance rise of the VRM due to the internal feedback response bandwidth, is well represented by an inductor and resistor. The resistor represents the VRM voltage drop that is proportional to DC current. The inductor provides an increasing impedance with frequency beyond some corner frequency.
The inductance value is calculated from the current ramp response time or by matching the resonant frequency between the VRM inductance and bulk (output) capacitance. Note that the inductance value for the simple linear model is not related to the inductor value in the SMPS model. The inductor of the linear RL model simply captures the behavior of the regulation loop (either SMPS or LDO), and does not represent any physical element. The resistance value (R) in the VRM model (R_VRM) is simply the resistance at DC or some very low frequency (100 Hz) at which the impedance curve bottoms out.
The R in the RL model needs to satisfy two properties: provide the correct damping for the parallel resonant peak and provide the correct DC output impedance. One single value can rarely do this. A more
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accurate model must include two values of resistance, and to be effective in the circuit, two series inductor values. This is a 4-element RL model.
Second Order Model of the VRM: A 4-element RL Model Modeling the VRM as the parallel combination of two series RL circuits, as shown in Figure 2, offers a simple, linear circuit model for a VRM that includes a more accurate representation of the DC or low frequency impedance, the equivalent inductance of the feedback loop, and the damping resistance needed to account for the first parallel resonant peak.
Figure 2: A simple, linear, 4-element VRM model isolates the ideal voltage source from the rest of the PDN components and produces the red impedance curve. The impedance peak at about 300 kHz is due to the VRM output inductance interacting with the on-board bulk capacitor. The impedance peak between on-die capacitance and bump-package loop inductance appears at about 100 MHz as it should.
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This 4-element RL model has little impact on the higher frequency Bandini Mountain peak but will affect the lower frequency parallel resonance between the VRM and the bulk capacitor. This model is useful when analyzing on-die Vdd self-aggression noise. The element parameters can be chosen to give reasonably accurate simulation results in both frequency and time domains with this linear model.
The second resistor (R_damp) is used to independently damp the impedance peak while the first resistor is used to set the proper DC IR drop. A good starting value for R_damp is the target impedance, which would result in a q-factor of 1. This can be refined by PDN measurement of an active VRM with a VNA.
The VRM will not deliver significant current at high frequency, so a second inductor with a value of approximately L_VRM/10 is used to model the blocked high frequency current. The 4-element VRM model provides the damping that brings the VRM impedance peak down to the target impedance without impacting the DC IR drop at low frequency. This is illustrated in Figure 3.
Figure 3: Proper DC IR drop and damping for the VRM peak is achieved at the same time by adding an additional R and L to the 2-element model.
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Modeling Other Noise Sources using an Active Model None of these linear models can account for any of the noise on the Vdd rail from VRM-aggression, which can be caused by an inadequate PSRR and noise on the primary power source, switching noise from the internal VRM operation, or nonlinear transient response from changing current loads.
Any of these effects will generate more noise on the pins of the VRM and appear on the Vdd rail pads if their frequency components are below the pole frequency of the Bandini Mountain. These noise sources will add to the Vdd self-aggression noise caused by Vdd transient currents. In extreme cases, VRM and other aggressor noise can exceed the self-aggression noise tolerance and cause larger problems.
The factors that contribute to these noise sources are often not related to the PDN design features that we optimized to reduce the Vdd self-aggression noise. These factors must be analyzed and addressed independently of design features introduced to reduce the Vdd self-aggression noise.
An accurate VRM model reflects the non-linear properties of transistors and feedback loops that occur when load currents transition from very low to very high values and the VRM is at the limit of its current delivery range. An accurate VRM model also takes into account switching noise and PSRR effects, as well as small- and large-signal impedance effects. Accurate models are required for closed loop feedback simulations to determine the best circuit elements and parameters for stability analysis. Accurate VRM models are required for optimal VRM design and integration into the entire PDN system.
As an example, a simple SMPS buck converter schematic is shown in Figure 4. It converts some higher DC voltage to a DC voltage appropriate for CMOS logic, often about 1 V. It involves complex circuitry to sense and regulate the output voltage, monitor current, open and close switches at appropriate times, and maintain stability over different load conditions.
Basically, the top switch remains closed until the working inductor is fully charged with current. The bottom switch is then closed to allow current to continue through the inductor loop while the loop current and energy stored in the working inductor diminishes. Complex circuitry and algorithms enable this class of regulators to function. Simulation and modeling of the SMPS is a major discipline in itself and significant design efforts and computer resources have been dedicated to these efforts. Ultimately, it is with such models that the interactions of the VRM with the rest of the PDN can be analyzed and each element optimized.
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Figure 4: Buck converter active VRM model.
Conclusion It is important to use a proper VRM model in PI simulations. An ideal voltage source should never be attached to a port of an extracted printed circuit board S-parameter model, as is often done, because it shorts out a significant portion of the PDN with zero impedance.
The ideal voltage source must be isolated from the board power planes and discrete capacitors by an impedance that represents the VRM. Preferably, the VRM model is tuned and correlated to regulator spec sheets and actual VRM measurements. If this information is not available, a 4-element RLRL model with an impedance peak at approximately the right magnitude and frequency may be used. The RLRL parameter values may be determined from the properties of the impedance peak. The VRM model affects the PDN impedance curve in a certain frequency band, often 20 kHz to 20 MHz.
Although linear models for the VRM are critical for optimizing the board level PDN to manage Vdd self-aggression noise, they cannot provide any insight into noise that originates with the VRM.
For a complete description of the noise in the PDN, including the VRM self-aggression noise, a non-linear model is needed and can be implemented using a state space model.
Figure 5 compares the measured output impedance of a SMPS VRM with the best fit of an RL model, and RLRL model and a more complex active model. We see the value of the RLRL model for impedance modeling and the same performance of the active model, but the active model has the advantage of modeling other noise sources.
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Idc=1 A
Iout=3 mAIFB=10 nAAVOL=10 kGBW=3 MHz
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Ri=0.135 {t}
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Cramp=150 pF {-t}Fs=Fs
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Figure 5: Comparison of the VRM models for the impedance of a VRM and the measured impedance. The RL model does not predict the peak impedances very well, while the RLRL model and active model match the measurements very well.
References
[1] S. Sandler, How to Design for Power Integrity: DC-DC Converter Modeling and Simulation. 2018.
[2] V. Sriboonlue, L. Smith, J. Mohamed, J. Shin, and T. Michalka, “Novel Parallel Resonance Peak Measurement and Lossy Transmission Line Modeling of 2-T and 3-T MLCC capacitors for PDN Application.”
[3] H. Barnes, J. Carrel, and S. Sandler, “Power Integrity for 32 Gb/s SERDES Transceivers,” in DesignCon, 2018.
[4] L. Smith and E. Bogatin, Principles of Power Integrity for PDN Design. Prentice Hall, 2017.
[5] S. Sun, A. Corp, L. D. Smith, and P. Boyle, “On-Chip PDN Noise Characterization and Modeling,” in Santa Clara, CA, DesignCon, 2010, no. 408, pp. 1–21.
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