Book III

Real-Time Simulation Modelsof

Power Electronics & Drives

Department of Electrical EngineeringIndian Institute of Science

Bangalore 560012

Jayalakshmi KedarisettiDinesh Gopinath

Mridula Jain

December 2, 2006

Contents

1 Real-Time Simulation Of Dynamic Systems 31.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2 Integration Methods . . . . . . . . . . . . . . . . . . . . . . . 41.3 Simulating An RLC Circuit . . . . . . . . . . . . . . . . . . . 81.4 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 91.5 FPGA Design Files . . . . . . . . . . . . . . . . . . . . . . . . 91.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 Real-Time Simulation Of SMPC 132.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.2 Basic Principle of Operation . . . . . . . . . . . . . . . . . . . 132.3 Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.1 Power Circuit Design . . . . . . . . . . . . . . . . . . 152.3.2 Implementation . . . . . . . . . . . . . . . . . . . . . . 162.3.3 Normalized Equations . . . . . . . . . . . . . . . . . . 172.3.4 FPGA Design Files . . . . . . . . . . . . . . . . . . . . 172.3.5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4 Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . 212.4.1 Power Circuit Design . . . . . . . . . . . . . . . . . . 222.4.2 Implementation . . . . . . . . . . . . . . . . . . . . . . 222.4.3 Normalized Equations . . . . . . . . . . . . . . . . . . 232.4.4 FPGA Design Files . . . . . . . . . . . . . . . . . . . . 242.4.5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.5 Buck-Boost Converter . . . . . . . . . . . . . . . . . . . . . . 282.5.1 Power Circuit Design . . . . . . . . . . . . . . . . . . . 292.5.2 Implementation . . . . . . . . . . . . . . . . . . . . . . 292.5.3 Normalized Equations . . . . . . . . . . . . . . . . . . 302.5.4 FPGA Design Files . . . . . . . . . . . . . . . . . . . . 312.5.5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3 Real-Time Simulation of Separately Excited DC Machine 373.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.2 Open Loop Control of DC Machine . . . . . . . . . . . . . . . 37

ii CONTENTS

3.2.1 Implementation . . . . . . . . . . . . . . . . . . . . . . 38

3.2.2 FPGA Design Files . . . . . . . . . . . . . . . . . . . . 39

3.3 Closed Loop Control of DC Machine . . . . . . . . . . . . . . 41

3.4 Transfer Functions Of The Subsystems . . . . . . . . . . . . . 42

3.4.1 DC Motor and Load . . . . . . . . . . . . . . . . . . . 42

3.4.2 Chopper . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.4.3 Current and Speed Controllers . . . . . . . . . . . . . . 43

3.4.4 Current Feedback . . . . . . . . . . . . . . . . . . . . . 43

3.4.5 Speed Feedback . . . . . . . . . . . . . . . . . . . . . . 43

3.5 Simulation of DC Motor Drive . . . . . . . . . . . . . . . . . . 44

3.5.1 DC Motor Equations . . . . . . . . . . . . . . . . . . . 44

3.5.2 Speed-Feedback Filter . . . . . . . . . . . . . . . . . . 44

3.5.3 Current-Feedback Filter . . . . . . . . . . . . . . . . . 44

3.5.4 Speed Controller . . . . . . . . . . . . . . . . . . . . . 46

3.5.5 Current Controller . . . . . . . . . . . . . . . . . . . . 46

3.5.6 Chopper . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.6 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.7 FPGA Design Files . . . . . . . . . . . . . . . . . . . . . . . . 48

3.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4 Real-Time Simulation of Induction Machine 51

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.2 Basic Principle of Operation . . . . . . . . . . . . . . . . . . . 51

4.3 Modelling of Induction Machine using Space Phasors . . . . . 53

4.4 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.5 Normalized Equations . . . . . . . . . . . . . . . . . . . . . . 57

4.6 FPGA Design Files . . . . . . . . . . . . . . . . . . . . . . . . 57

4.7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5 V/F Control of Induction Motor Drive 69

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.2 Basic Principle of V/F operation . . . . . . . . . . . . . . . . 69

5.3 Sine-Triangle Modulation . . . . . . . . . . . . . . . . . . . . . 71

5.4 Implementation of V/F Sine-Triangle Modulator in FPGA . . 72

5.4.1 Generation of V/F sine waves . . . . . . . . . . . . . . 72

5.4.2 Carrier Generation . . . . . . . . . . . . . . . . . . . . 74

5.4.3 Generation of PWM . . . . . . . . . . . . . . . . . . . 76

5.4.4 Slow Start of Induction Motor . . . . . . . . . . . . . . 77

5.5 Open-loop V/F Control of IM - Real-time Simulation . . . . . 77

5.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

CONTENTS iii

6 Real-Time Simulation Of Switched Reluctance Motor 836.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836.2 Basic Principle of Operation . . . . . . . . . . . . . . . . . . . 836.3 Inductance Gradient (L vs θ) . . . . . . . . . . . . . . . . . . 856.4 Flux-Linkage Characterstics . . . . . . . . . . . . . . . . . . . 866.5 Torque Characterstics . . . . . . . . . . . . . . . . . . . . . . 876.6 Position Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . 916.7 Control Strategy . . . . . . . . . . . . . . . . . . . . . . . . . 926.8 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 956.9 Normalized Equations . . . . . . . . . . . . . . . . . . . . . . 976.10 FPGA Design Files . . . . . . . . . . . . . . . . . . . . . . . . 976.11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976.12 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

7 Control and Real-Time Simulation of Matrix Converters 1077.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077.2 Basic Principle of Operation . . . . . . . . . . . . . . . . . . . 1077.3 Direct and Indirect Matrix Converters . . . . . . . . . . . . . 109

7.3.1 Direct Matrix Conversion . . . . . . . . . . . . . . . . 1097.3.2 Indirect Matrix Conversion . . . . . . . . . . . . . . . . 110

7.4 Modulation of Matrix Converters . . . . . . . . . . . . . . . . 1127.4.1 Indirect Converter Modulation . . . . . . . . . . . . . . 1127.4.2 Direct Converter Modulation . . . . . . . . . . . . . . 117

7.5 Implementation of Modulators in FPGA . . . . . . . . . . . . 1187.5.1 Output Modulator . . . . . . . . . . . . . . . . . . . . 119

7.6 Modelling of Direct and Indirect Matrix Converters . . . . . . 1227.6.1 Indirect Converter . . . . . . . . . . . . . . . . . . . . 1247.6.2 Direct Converter . . . . . . . . . . . . . . . . . . . . . 126

7.7 Real-Time Simulation . . . . . . . . . . . . . . . . . . . . . . . 1277.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

iv CONTENTS

List of Figures

1.1 Triggering Timing. . . . . . . . . . . . . . . . . . . . . . . . . 41.2 Zero Order Integrator (Euler’s method). . . . . . . . . . . . . 51.3 First Order Integrator . . . . . . . . . . . . . . . . . . . . . . 61.4 Second Order Integrator . . . . . . . . . . . . . . . . . . . . . 71.5 Series RLC Circuit. . . . . . . . . . . . . . . . . . . . . . . . . 81.6 FPGA Design File for RLC Circuit . . . . . . . . . . . . . . . 101.7 FPGA Design File for Euler’s Integration . . . . . . . . . . . . 111.8 Transient Wave forms of RLC Circuit . . . . . . . . . . . . . . 11

2.1 Basic Switching Converter . . . . . . . . . . . . . . . . . . . . 132.2 Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . 142.3 FPGA Design File of Buck Converter . . . . . . . . . . . . . . 182.4 FPGA Design File of Buck Converter . . . . . . . . . . . . . . 192.5 Buck Converter Off-line Simulation Waveforms . . . . . . . . . 202.6 Buck Converter Real-Time Simulation Waveforms . . . . . . . 202.7 Boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . 212.8 FPGA Design File of Boost Converter . . . . . . . . . . . . . 252.9 FPGA Design File of Boost Converter . . . . . . . . . . . . . 262.10 Boost Converter Off-Line Simulation Waveforms . . . . . . . . 272.11 Boost Converter Real-Time Simulation Waveforms . . . . . . . 272.12 Buck-Boost Converter . . . . . . . . . . . . . . . . . . . . . . 282.13 FPGA Design File of Buck-Boost Converter . . . . . . . . . . 322.14 FPGA Design File of Buck-Boost Converter . . . . . . . . . . 332.15 Buck-Boost Converter Off-Line Simulation Waveforms . . . . . 342.16 Buck-Boost Converter Real-Time Simulation Waveforms . . . 34

3.1 DC Motor Model. . . . . . . . . . . . . . . . . . . . . . . . . . 383.2 Generalized Machine Model. . . . . . . . . . . . . . . . . . . . 383.3 FPGA Design File for DC Machine . . . . . . . . . . . . . . . 403.4 Modelling of DC Machine . . . . . . . . . . . . . . . . . . . . 403.5 Block Diagram of the DC Motor Drive . . . . . . . . . . . . . 413.6 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453.7 PI-Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 473.8 Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

vi LIST OF FIGURES

3.9 DC Motor Drive with Speed and Current Feedback . . . . . . 503.10 DC Motor Drive with Speed and Current Feedback . . . . . . 50

4.1 Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . 524.2 Twophase equivalent of a 3-phase induction motor . . . . . . . 534.3 FPGA Design File for isa . . . . . . . . . . . . . . . . . . . . . 594.4 FPGA Design File for isb . . . . . . . . . . . . . . . . . . . . . 604.5 FPGA Design File for isra . . . . . . . . . . . . . . . . . . . . . 614.6 FPGA Design File for isrb . . . . . . . . . . . . . . . . . . . . . 624.7 FPGA Design File for ωm . . . . . . . . . . . . . . . . . . . . 634.8 FPGA Design File for Eulers Integration . . . . . . . . . . . . 644.9 Vsa*k and Vsb*k waveforms where k=1/(1.5*sqrt(2)) . . . . . 654.10 Vsa and Vsb waveforms . . . . . . . . . . . . . . . . . . . . . 654.11 isa,isb, i

sra and isrb waveforms . . . . . . . . . . . . . . . . . . . 66

4.12 isa,isb, isra and isrb waveforms . . . . . . . . . . . . . . . . . . . 66

4.13 ωm and Mg ∗ 0.2/16 waveforms . . . . . . . . . . . . . . . . . 674.14 ωm and Mg ∗ 0.2 waveforms . . . . . . . . . . . . . . . . . . . 67

5.1 Torque-Speed Characteristics of Induction Motor . . . . . . . 705.2 V/F relation including low frequency voltage boost . . . . . . 705.3 Sine-Triangle PWM . . . . . . . . . . . . . . . . . . . . . . . . 715.4 Three Phase VSI . . . . . . . . . . . . . . . . . . . . . . . . . 725.5 Theta Address Generation Scheme . . . . . . . . . . . . . . . 745.6 p.u Sine wave . . . . . . . . . . . . . . . . . . . . . . . . . . . 745.7 Generation of Three-phase V/F Sine waves . . . . . . . . . . . 745.8 Carrier Generation Scheme in FPGA . . . . . . . . . . . . . . 755.9 Sine Wave and Triangular Carrier . . . . . . . . . . . . . . . . 765.10 PWM Generation for U-phase . . . . . . . . . . . . . . . . . . 765.11 PWM Signals for U and V phases . . . . . . . . . . . . . . . . 775.12 Slow Starting Logic . . . . . . . . . . . . . . . . . . . . . . . . 785.13 Slow Starting V/F Sine Wave Reference . . . . . . . . . . . . 785.14 VSI Model Implementation in FPGA . . . . . . . . . . . . . . 795.15 Interconnection of Different Modules for v/f Drive. . . . . . . 805.16 Real-Time Simulation Waveforms . . . . . . . . . . . . . . . . 80

6.1 Cross-section of and 8/6 pole 4-phase SR Motor . . . . . . . . 846.2 Idealised Inductance Profile of the Four Different Phases . . . 856.3 Flux-linkage Characterstics . . . . . . . . . . . . . . . . . . . . 876.4 Torque Characterstics . . . . . . . . . . . . . . . . . . . . . . 886.5 (a) Inductance Profiles of the Four Stator Phases . . . . . . . 916.5 (b) Position Signals for Forward Rotation . . . . . . . . . . . . 916.5 (c) Position Signals for Reverse Rotation . . . . . . . . . . . . 916.6 Low Speed Control Strategy . . . . . . . . . . . . . . . . . . . 956.7 Control Strategy at High Speed . . . . . . . . . . . . . . . . . 956.8 FPGA Design File for Speed to Position Conversion . . . . . . 98

LIST OF FIGURES vii

6.9 FPGA Design File for Sector Selection . . . . . . . . . . . . . 996.10 FPGA Design File for Generation of Position Signals . . . . . 1006.11 (a) FPGA Design File for Generation of Enable Signals . . . . 1016.12 (b) FPGA Design File for Generation of Enable Signals . . . . 1026.13 High Speed (Forward) and Full Load (Forward) Waveforms . . 1036.14 Low Speed (Forward) and Full Load (Forward) Waveforms . . 1036.15 Starting Speed (Forward) and Full Load (Forward) Waveforms 1036.16 High Speed (Reverse) and Full Load (Forward) . . . . . . . . 1046.17 High Speed (Reverse) and Full Load (Reverse) . . . . . . . . . 1046.18 High Speed (Forward) and Full Load (Reverse) . . . . . . . . 1046.19 High Speed and Half Load . . . . . . . . . . . . . . . . . . . . 105

7.1 Matrix Converter Topology . . . . . . . . . . . . . . . . . . . 1087.2 Indirect Matrix Converter Topology . . . . . . . . . . . . . . . 1107.3 Input Converter and the Current Space Phasors . . . . . . . . 1127.4 Sector Definition . . . . . . . . . . . . . . . . . . . . . . . . . 1137.5 Modulation Functions and Raw Switch Signals . . . . . . . . . 1147.6 VSI and Space vectors . . . . . . . . . . . . . . . . . . . . . . 1157.7 Switch Signal Generation for VSI : Sector 1 . . . . . . . . . . 1167.8 Input Modulator Implementation in FPGA . . . . . . . . . . . 1187.9 Structure of Input Modulator . . . . . . . . . . . . . . . . . . 1197.10 Output Modulator Implementation in FPGA . . . . . . . . . . 1197.11 Reference angle Generation . . . . . . . . . . . . . . . . . . . 1207.12 Calculation of Duty Ratios . . . . . . . . . . . . . . . . . . . 1217.13 Calculation of Modulating Functions . . . . . . . . . . . . . . 1227.14 Duty Ratios dα and dβ . . . . . . . . . . . . . . . . . . . . . . 1227.15 PWM signals for S1 and S2 of Input Converter . . . . . . . . . 1237.16 PWM signals for Su and Sv of Output Converter . . . . . . . 1237.17 PWM signals for Sau and Sbu of Direct Converter . . . . . . . 1247.18 DC link voltage : Indirect Matrix Converter . . . . . . . . . . 1257.19 Structure of Output Modulator . . . . . . . . . . . . . . . . . 1257.20 Indirect Converter Model . . . . . . . . . . . . . . . . . . . . . 1267.21 Output Line Voltage: Indirect Matrix Converter . . . . . . . . 1267.22 Output Phase Voltage : Indirect Matrix Converter . . . . . . . 1277.23 Direct Matrix Converter Model . . . . . . . . . . . . . . . . . 1277.24 Line-Line Voltage : Direct Matrix Converter . . . . . . . . . . 1287.25 Phase Voltage: Direct Matrix Converter . . . . . . . . . . . . 1287.26 Input Converter Model in FPGA . . . . . . . . . . . . . . . . 1297.27 DC link voltage : Real-time simulation . . . . . . . . . . . . . 1307.28 Output Phase Voltage : Real-time simulation . . . . . . . . . 1307.29 Real-time Simulation Results . . . . . . . . . . . . . . . . . . 131

viii LIST OF FIGURES

List of Tables

1.1 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.2 PU Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Parameters of the Buck converter . . . . . . . . . . . . . . . . 162.2 Base Values for the Buck converter . . . . . . . . . . . . . . . 162.3 Per Unit Values . . . . . . . . . . . . . . . . . . . . . . . . . . 162.4 Parameters of the Boost converter . . . . . . . . . . . . . . . . 232.5 Base Values for the Boost converter . . . . . . . . . . . . . . . 232.6 Parameters of the Buck-Boost converter . . . . . . . . . . . . 302.7 Base Values for Buck-Boost converter . . . . . . . . . . . . . . 30

3.1 Details of the DC Motor . . . . . . . . . . . . . . . . . . . . . 393.2 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393.3 PU Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393.4 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.1 Details of the Induction Motor . . . . . . . . . . . . . . . . . . 554.2 Parameters of the Induction Motor . . . . . . . . . . . . . . . 564.3 Base Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564.4 PU Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564.5 Equations for implementing in Digital Domain . . . . . . . . . 58

6.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886.2 Torque . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896.3 Torque (contd..) . . . . . . . . . . . . . . . . . . . . . . . . . . 906.4 Switch Control Signals . . . . . . . . . . . . . . . . . . . . . . 926.5 θ1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946.6 θ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946.7 Details of the Switched Reluctance Motor . . . . . . . . . . . 966.8 Base Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966.9 PU Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

7.1 Switch Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

2 LIST OF TABLES

Chapter 1

Real-Time Simulation OfDynamic Systems

1.1 Introduction

Any system can be represented by a mathematical model. Dynamic systemsare represented by differential equations or difference equations. Simulation ofdynamic systems require the solving of these differential/difference equations.In off-line simulation tools, the solution is carried out in a non-real time man-ner. For example, if it is required to study the response of a system for a fewseconds, it may take minutes or even hours to complete the simulation. Thisdepends on the complexity and simulation parameters. This is because theactual time involved in the calculation of the variables is more. On the otherhand in Real-Time Simulation, the results are produced almost instantly. Thisis possible if the system model is implemented by an electronic circuit. Histor-ically, analog computers were used to solve differential equations. But analogcircuits are less flexible in simulating complex systems. Real-time simulationcan be done with digital circuits or microprocessors also. Here, the systemsequations need to be translated to difference-equations. However, conventionalmicroprocessors and Digital Signal Processors (DSPs) suffer from an inherentbottleneck in performing calculations. They process the data in a sequentialmanner. So, there is a limit to the minimum simulation step time that ispossible for a fixed clock frequency. This limitation can be overcome by par-alleling processors. Such a scheme is scalable and very useful for simulatingvery large dynamic systems with several variables. For real-time simulation ofcomparatively less-complex systems, a less costly alternative is required.

An FPGA is a suitable platform for implementing such systems. The basicadvantage of an FPGA is that it can be programmed to process data in parallel.Thus the implementation of system equations on an FPGA results in very shortexecution time. The system model is realized as a combination of sequentialand combinational logic elements. This digital circuit is then programmedin to the FPGA. The minimum time required to calculate the present state

4 Real-Time Simulation Of Dynamic Systems

CSV

Variables

USV

∆τ

Variables

Calculate State

Update State

Figure 1.1: Triggering Timing.

variables from previous state variables is the sum of propogation delay of alllogical elements and setup and hold times of sequential elements. A clocksignal drives the digital circuit. During each clock cycle, the present states ofthe system are calculated. These calculations are split into two stages as shownin Fig. 1.1. In the first stage the present states of the system are calculatedusing the previous states of the system. In the second stage the values areupdated.

1.2 Integration Methods

The dynamic systems may be represented generally in the form of ODE

dyi

dt= ei(xj, yk, t), i, j, k = 1, . . . , n (1.1)

where xj(t) are the independent forcing functions, yk(t) are the state variablesand t the time as variable of integration.

The procedure for solving a system of equations simply involves applyingthe one-step technique for every equation at each step before proceeding tothe next step. There are several integration methods [1] to solve the differ-ential equations (1.1). These methods differ in complexity. Each integrationmethod can be implemented by digital logic elements in FPGA. Because of itssimplicity, euler’s algorithm is widely used.

A. Backwards Euler’s MethodIn this method, the time axis is subdivided into several intervals. In eachinterval, ei is approximated by a constant representing the average of ei

in that interval. A new value of yi is predicted using the slope (equal tothe first derivative at the previous value) to extrapolate linearly over thestep size ∆t.

yi(n) = yi(n− 1) + ei(n− 1) ∗ ∆t (1.2)

In digital logic circuit, Euler’s method is represented as shown in Fig. 1.2.

1.2 Integration Methods 5

yn

en−1

yn−1

D−Flipflop∆τ

CSV

USV

Multiplier ADDER

D−Flipflop

Figure 1.2: Zero Order Integrator (Euler’s method).

D-Flipflop is used for delaying the input until the next clock pulse is given.With the rising edge of the clock pulse CSV, yi(n − 1) is latched. Errorfunction ei(n − 1) which is dependent on the previous state variablesyi(n−1) is calculated and given as input to the integration block. Inputsto the ADDER block are yi(n−1), ei(n−1)∗∆t as in the eq. (1.2). Statevariables are updated with the rising edge of the clock USV.

B. Heun’s MethodThe curve ei is approximated as a straight line within the interval (n −1)∆t to n∆t. The area under this straight line is an estimate of theintegral of ei between the limits (n− 1)∆t and n∆t. So

yi(n) = yi(n− 1) + ∆tei(n− 1) + ei(n)

2(1.3)

Implementation of the Heun’s method with logical elements is similarto Eulers method except the input ei(n − 1) is replaced by the averageof ei(n− 1) and ei(n). With the given previous state variable yi(n − 1),ei(n − 1) is calculated. As said before, FPGA is a parallel device. soei(n − 1) has to be latched (Latch) for calculating the average of errorfunctions. Multiplexer (MUX) selects either ei(n− 1) or average of errorfunctions depending upon the clock ‘Avg’. So Heun’s method requires twoclock cycles to calculate the present state variables Fig. 1.3. The dottedline shows division of the on period CSV into two halfs. Obviously, heun’smethod of integration appropriates more number of logic elements whencompare to Eulers method.


yn−1

yn

yn−pred

en−1

(b)

USV

CSV

∆τ

Latch

Avg

yn

en−1

yn−pred

yn−1yn−1

(a)

D−Flipfloperr

CSV

USV∆τ

Latch

Avg

Multiplier

Avg

MUX

MUX

Avg2

ADDER

ADDER

D−Flipflop

D−Flipflop

D−Flipflop

err

Figure 1.3: (a) First Order Integrator (Heun’s Method) (b) Triggering Timing.

1.2 Integration Methods 7

yn−1

en−1

yn

CSV

K1 / K2

(b)

USV

∆τ

yn

yn−pred

yn−1

__21

(a)

err

D−Flipflop

D−Flipflop

D−Flipflop

CSV

USV∆τ

Multiplier

Avg

MUX

MUX

en−1

yn−1

errK1 / K2

K1 / K2

ADDER

Figure 1.4: (a) Second Order Runge-Kutta Method (b) Triggering Timing.

C. Second-Order Runge-Kutta Method

yi(n) = yi(n− 1) + k2 ∗ ∆t

where k1 = ei

(yi(n− 1), t(n− 1)

)

k2 = ei

(

yi(n− 1) +1

2k1∆t, t(n− 1) +

1

2∆t

)(1.4)

This is the improved polygon method. This method also requires twoclock cycles to calculate the present state variables fig. 1.4.

Eventhough there are different integration methods to solve (1.1), the onlydifference would be the formulation of subroutine to compute the slopes. Thehigher order techniques are always the methods of preference [1]. However,other factors such as programming costs and the accuracy requirements of theproblem must also be considered when choosing a solution technique.


aR

Vg Vc

aRVg Ω µ= 100 V; = 10 ; L = 20 mH; C = 4 H

C

L

i+

_

Figure 1.5: Series RLC Circuit.

1.3 Simulating An RLC Circuit

An electrical series RLC circuit is shown in Fig 1.5. A transient current andvoltages are established in the circuit when the switch is suddenly closed.Equations that describe the transient behavior of the circuit 1.5 are

Vg = Ri + Ldi

dt+ vc (1.5a)

i = Cdvc

dt(1.5b)

Equations (1.5) are a pair of first-order linear differential equations that canbe solved using any above mentioned numerical methods.

The equations are first normalized with the help of arbitrary values Vb, Rb.

Vg

Vb

=R

Rb

i

ib+

L

Rb

d iib

dt+vc

Vb

(1.6a)

i

ib= CRb

d vc

Vb

dt(1.6b)

where ib = Vb/Rb.With the following abbrevations,

Vg

Vb

= V ∗

g ,i

ib= i∗,

R

Rb

= R∗,vc

Vb

= v∗c ,L

Rb

= τLR, CRb = τCR,

a nondimensional equation results

τLR

di∗

dt

τCR

dv∗cdt

=

−R∗ −1

1 0

i∗

v∗c

+

1

0

V∗

g(1.7)

These first order linear differential equations can be solved using any numericalmethods as mentioned in section 1.2.

1.4 Implementation 9

1.4 Implementation

A. Parameters : The Table. 1.1 gives the base values for voltage, current andthe values of other quantities.

Input Voltage (Va) 100V

Ra, L, C 10Ω, 20mH, 4µF

Voltage (Vb) 100V

Current (Ib) 10A

R∗ V ∗/I∗ = 1

τLR L/Rb = 2e−3

τCR CRb = 40e−6

Step time (∆T ) 25.6µ

Table 1.1: Parameters

pu value Equivalent digital Value Equivalent decimal value

2 pu 7FFFH 32767d

1 pu 3FFFH 16383d

0 pu 000H 0d

-1 pu(16bit) C000H 49152d

-2 pu(16bit) 8000H 32768d

Table 1.2: PU Values

B. PU System Followed : The Table 1.2 shows the digital equivalent for thepu values. The bit length of the digital word is not limited in an FPGA.Inorder to incorporate the signed arithmetic, the digital equivalent for anegative pu value is chosen as the 1’s compliment of digital equivalent ofits corresponding positive pu value.

1.5 FPGA Design Files

FPGA Design files of RLC Circuit are placed in ‘fpga program files’ folder.Fig. 1.6 and Fig. 1.7 are the FPGA design files to implements the equationsgiven in (1.7). The output waveforms are shown in Fig. 1.8


Fig

ure

1.6:

FP

GA

Des

ign

File

for

RLC

Circu

it

1.6 Conclusion 11

Figure 1.7: FPGA Design File for Euler’s Integration

Figure 1.8: RLC Circuit (Eulers Integration).(1) Input Voltage (2) Inductor Current (3) Capacitor Voltage

1.6 Conclusion

In this chapter, different integration methods are explained. Simple RLCcircuit has been implemented in FPGA based controller.


Chapter 2

Real-Time Simulation Of SMPC

2.1 Introduction

DC-to-DC converters convert electrical power provided from a source at acertain dc voltage to electrical power at a different dc voltage. Linear regula-tors are most common converters used for this purpose. They are simple toanalyze and design, also provide very high quality output voltage. But themajor drawback of linear regulators is their poor efficiency[11]. The losses insuch converters appear as heat in the series and shunt elements. The linearregulators are therefore used only for low power levels. For the applications,where the efficiency is very important, linear regulators are not suitable. Insuch applications, switched mode power converters are standard.

Switched mode power converters use power electronics semiconductor de-vices which operate in ON and OFF states. Because there is a small powerloss (ideally zero) in those states (very small voltage across a switch in the ONstate and zero current through a switch in OFF state), switching converterscan achieve high energy conversion efficiency.

2.2 Basic Principle of Operation

The basic circuit for SMPC is shown in Figure 2.1.

VgR

Vo(t)on off

−

+

Figure 2.1: Basic Switching Converter

14 Real-Time Simulation Of SMPC

The average value of output voltage depends upon the position of switch.The ON position connects the source Vg to the output. In the OFF position,output is totally isolated from the input. The switch is operated at a switchingperiod of Ts

For a fraction [dTs] of the switching period, the switch is kept ON. For therest of the time [(1 − d)TS], switch is kept OFF. The fraction d is defined asduty ratio of the switch[12]. The average output voltage can be calculated interms of d and is found to be:

Vo =1

Ts

∫ TS

0

Vo dt =1

Ts

∫ Ton

0

Vg dt+1

Ts

∫ Ts

Ton

0 dt = Vg

Ton

Ts

= Vgd (2.1)

2.3 Buck Converter

Buck converter is also known as step-down converter. As the name implies, astep down converter produces a lower output voltage than the dc input voltage.Figure 2.2 shows the circuit diagram of a Buck Converter with a resistive loadand a low pass filter.

offC R

on L

VcVg

i L

−

+

Figure 2.2: Buck Converter

The dynamic equations and output equations of the buck converter areobtained as follows.During ON time:

Ldi

dt= Vg − Vc (2.2a)

Cdvc

dt= il −

Vc

r(2.2b)

During OFF time:

Ldi

dt= −Vc (2.3a)

Cdvc

dt= il −

Vc

r(2.3b)

2.3 Buck Converter 15

Combining equations 2.2 and 2.3 , following equations are obtained

Ldi

dt= Vg(d) − Vc (2.4a)

Cdvc

dt= il −

Vc

r(2.4b)

vo = vc (2.5)

Vo = dVg (2.6)

Ig = dIo (2.7)

The above equations describe the complete modelling of the buck converter.The Eqn 2.4 is the dynamic equation of the converter. Eqn 2.6 and Eqn 2.7give the relation between input-output voltage and current respectively.

2.3.1 Power Circuit Design

A. Design of Inductor :

In each sub period [dTS and (1 − d)TS], the rate of change of currentis constant. The current ripple can be determined using the followingequation.

δIo =Vgd(1 − d)TS

L=

Vo(1 − d)TS

L(2.8)

δIoIo

= δi =(1 − d)RTS

L(2.9)

The value of the inductance L is designed such that δi is 10% of the outputcurrent Io.

B. Design of Capcitor :

The charging and discharging current of the capacitor decides the voltageripple. The ac part of the inductor current flows into the capacitor.

δVo =δQ

C=

1

C

1

2

δIo2

TS

2(2.10)

δVo =Vo(1 − d)T 2

S

8LC(2.11)

δVo

Vo

= δv =(1 − d)T 2

S

8LC(2.12)

The capacitor C is designed for δv to be 1% of the output voltage Vo.


2.3.2 Implementation

A. Parameters : The parameters of the Buck Converter used in the simula-tion program are shown in the Table 2.1.

Quantity ValueVg 13.33VL 0.64mHR 5ΩC 40µFTlr 0.00013Trc 0.0002d .75Ts 102.4µsec4t 3.2µsec

Table 2.1: Parameters of the Buck converter

B. Base Values for Different Quantities : As the implementation is digitallyrealized, there arises the need for following a pu system for simple under-standing. For perunitization of different quantities, the base values arerequired, which can be chosen as per convenience. The Table. 2.2 showsthe base values for voltage, resistance and current. The other bases arecalculated from the above mentioned base quantities.

Voltage (Vb) 13.33Vresistance (Rb) 5ΩCurrent (Ib) 2A

Table 2.2: Base Values for the Buck converter

C. PU System Followed : The Table 2.3 shows the digital equivalent for thepu values. The digital equivalent for a negative pu value is chosen as the1’s compliment its corresponding positive pu value.

pu value Equivalent digital Value Equivalent decimal value2 pu 7FFFH 32767d1 pu 3FFFH 16383d0 pu 000H 0d-1 pu(16bit) C000H 49152d-2 pu(16bit) 8000H 32768d

Table 2.3: Per Unit Values

2.3 Buck Converter 17

2.3.3 Normalized Equations

In this section, all the equations are perunitized and are made ready for im-plementation.

Ldi

dt= Vg(d) − Vc (2.13a)

Cdvc

dt= il −

Vc

r(2.13b)

Dividing the above equations by ib, and Vb respectively,

iL(pu) =1

Tlr

∫(Vg(pu)d− Vc(pu)

)dt

Vc(pu) =1

Trc

∫(iL(pu)d− Vc(pu)

)dt

Using the Eulers Method of integration [1], the equation in digital domaincan be written as

iL (n) = iL (n− 1) + e (n− 1) (4t) (2.14)

where

e (n− 1) =(Vg (n− 1) (d) − Vc (n− 1)

) 1

Tlr

Vc (n) = Vc (n− 1) + e (n− 1) (4t) (2.15)

where

e (n− 1) =(iL (n− 1) (d) − Vc (n− 1)

) 1

Trc

The digital realization for the above equations requires adders, subtrac-tors, multipliers and dividers. All these entities are available in the libraryof Quartus-II tool. Apart from these arithimetic logic entities, D-Flip Flopsare also needed for storing previous data values, in the case of performingintegration.

2.3.4 FPGA Design Files

FPGA Design files of Buck Converter are placed in ‘fpga program files’ folder.Fig. 2.3 and Fig. 2.4 are the FPGA design files to implements the equationsgiven in eqns 2.14 and 2.15.

2.3.5 Waveforms

The program developed (using the equations 2.14 and 2.15 ) for direct onlinesimulation in Quartus II tool are downloaded into FPGA board. The wave-forms are recorded and are compared with the off-line simulation waveformsas shown in Figs 2.5 and 2.6.

18

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ime

Sim

ula

tion

OfSM

PC

Figure 2.3: FPGA Design File of Buck Converter for PWM wave generation and DAC Interfacing

2.3

Buck

Converte

r19

Figure 2.4: FPGA Design File of Buck Converter for Vc and iL


0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.010

0.5

1

1.5

2

0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.010

0.5

1

0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.010

0.5

1

1.5

Vg

Vo

iL

t (sec)

Figure 2.5: Vg, Vo and iL waveforms (off-line simulation) for Buck ConverterScale: y-axis: all quantities in per unit

Figure 2.6: Vg, Vo and iL waveforms (real time simulation) for Buck ConverterScale: y-axis: 1 division = 5V (1 per unit = 5V )

2.4 Boost Converter 21

2.4 Boost Converter

Boost converter is also known as step-up converter. It produces a higheroutput voltage than the dc input voltage. Thus the gain of the converter ismore than unity. The practical range of duty ratio is 0 to 0.66. Figure 2.7shows the circuit diagram of a Boost Converter with a resistive load and a lowpass filter.

C RVg Vc

L

on

offi L

−

+

Figure 2.7: Boost converter

The dynamic equations and output equations of the Boost converter areobtained as follows.During ON time:

LdiLdt

= Vg (2.16a)

Cdvc

dt= −Vc

r(2.16b)

During OFF time:

LdiLdt

= Vg − Vc (2.17a)

Cdvc

dt= il −

Vc

r(2.17b)


LdiLdt

= Vg − Vc(1 − d) (2.18a)

Cdvc

dt= iL(1 − d) − Vc

r(2.18b)

vo = vc (2.19)


Vo =Vg

(1 − d)(2.20)

Ig =Io

(1 − d)(2.21)

The above equations describe the modelling of the boost converter. TheEqn 2.18 is the dynamic equation of the converter. Eqn 2.20 and Eqn 2.21give the relation between input-output voltage and current respectively.


A. Design of Inductor : In each sub period [dTS and (1 − d)TS], the rateof change of current is constant. The current ripple can be determinedusing the following equation.

δIL =VgdTS

L(2.22)

δILIL

= δi =d(1 − d)2RTS

L(2.23)


B. Design of Capacitor :

The charging and discharging current of the capacitor decides the voltageripple. The entire ac part of the inductor current flows into the capacitor.

δVo =δQ

C=

IodTS

C(2.24)

δVo

Vo

= δv =dTS

RC(2.25)



A. Parameters : The parameters of the Boost Converter used in the simula-tion program are shown in the Table 2.4.



Quantity ValueVg 2.5VL 0.32mHR 5ΩC 102.4µFTlr 0.000064Trc 0.000512d 0.25Ts 102.4µsec4t 3.2µsec

Table 2.4: Parameters of the Boost converter

Voltage (Vb) 10Vresistance (Rb) 5ΩCurrent (Ib) 2A

Table 2.5: Base Values for the Boost converter



LdiLdt

= Vg − Vc(1 − d) (2.26a)

Cdvc

dt= iL(1 − d) − Vc

r(2.26b)


iL(pu) =1

Tlr

∫(Vg(pu) − Vc(pu)(1 − d)

)dt

Vc(pu) =1

Trc

∫(iL(pu)(1 − d) − Vc(pu)

)dt

Using the Eulers Method of integration, the equation in digital domain canbe written as

iL (n) = iL (n− 1) + e (n− 1) (4t) (2.27)

where

e (n− 1) =(Vg (n− 1) − (1 − d)Vc (n− 1)

) 1

Tlr

Vc (n) = Vc (n− 1) + e (n− 1) (4t) (2.28)

where

e (n− 1) =((1 − d)iL (n− 1) − Vc (n− 1)

) 1

Trc



FPGA Design files of Boost Converter are placed in ‘fpga program files’ folder.Fig. 2.8 and Fig. 2.9 are the FPGA design files to implement the equationsgiven in eqns 2.27 and 2.28.

2.4.5 Waveforms


2.4

Boost

Converte

r25

Figure 2.8: FPGA Design File of Boost Converter for PWM wave generation and DAC Interfacing

26

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Sim

ula

tion

OfSM

PC

Figure 2.9: FPGA Design File of Boost Converter for Vc and iL


0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.01−1

0

1

2

0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.010

0.2

0.4

0.6

0.8

0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.010

0.5

1

1.5

Vg

V

i L

time (sec)

o

Figure 2.10: Vg, Vo and iL waveforms (off-line simulation) for Boost ConverterScale: y-axis: all quantities in per unit

Figure 2.11: Vg, Vo and iL waveforms (real time simulation) for Boost Con-verter

Scale: y-axis: 1 division = 2V (1 per unit = 5V )


2.5 Buck-Boost Converter

Buck-Boost converter can be obtained by the cascade connection of the twobasic converters: the Buck converter and the Boost converter. The gain of thisconverter may be above or below unity. The output polarity is opposite to thatof input polarity. The practical range of duty ratio is 0 to 0.66. Figure 2.12shows the circuit diagram of a Boost Converter with a resistive load and a lowpass filter.

C RVc

offon

Li

LVg

−

+

Figure 2.12: Buck-Boost Converter

The dynamic equations and output equations of the Buck-Boost converterare obtained as follows.During ON time:

LdiLdt

= Vg (2.29a)

Cdvc

dt= −Vc

r(2.29b)

During OFF time:

LdiLdt

= Vc (2.30a)

Cdvc

dt= −il −

Vc

r(2.30b)


LdiLdt

= Vg(d) + Vc(1 − d) (2.31a)

Cdvc

dt= −iL(1 − d) − Vc

r(2.31b)

vo = vc (2.32)

2.5 Buck-Boost Converter 29

Vo = −Vg

d

(1 − d)(2.33)

Ig = Iod

(1 − d)(2.34)

The above equations describe the modelling of the Buck-Boost converter.The Eqn 2.31 is the dynamic equation of the converter. Eqn 2.33 and Eqn 2.34give the relation between input-output voltage and current respectively.


A. Design of Inductor : In each sub period [dTS and (1 − d)TS], the rateof change of current is constant. The current ripple can be determinedusing the following equation.

δIL =VgdTS

L(2.35)

δILIL

= δi =(1 − d)2RTS

L(2.36)


B. Design of Capacitor : The charging and discharging current of the capac-itor decides the voltage ripple. The entire ac part of the inductor currentflows into the capacitor.

δVo =δQ

C=

IodTS

C(2.37)

δVo

Vo

= δv =dTS

RC(2.38)



A. Parameters : The parameters of the Buck-Boost Converter used in thesimulation program are shown in the Table 2.6.



Quantity ValueVg 7.5VL 0.64mHR 5ΩC 102.4µFTlr 0.000128Trc 0.000512d .25Ts 102.4µsec4t 3.2µsec

Table 2.6: Parameters of the Buck-Boost converter

Voltage (Vb) 10Vresistance (Rb) 5ΩCurrent (Ib) 2A

Table 2.7: Base Values for Buck-Boost converter



LdiLdt

= Vg(d) + Vc(1 − d) (2.39a)

Cdvc

dt= −iL(1 − d) − Vc

r(2.39b)


iL(pu) =1

Tlr

∫(dVg(pu) + Vc(pu)(1 − d)

)dt

Vc(pu) = − 1

Trc

∫(iL(pu)(1 − d) + Vc(pu)

)dt

Using the Eulers Method of integration, the equation in digital domain canbe written as

iL (n) = iL (n− 1) + e (n− 1) (4t) (2.40)

where

e (n− 1) =((dVg (n− 1) + (1 − d)Vc (n− 1)

) 1

Tlr

Vc (n) = Vc (n− 1) + e (n− 1) (4t) (2.41)

2.5 Buck-Boost Converter 31

where

e (n− 1) =(− (1 − d)iL (n− 1) − Vc (n− 1)

) 1

Trc


FPGA Design files of Buck-Boost Converter are placed in ‘fpga program files’folder. Fig. 2.13 and Fig. 2.14 are the FPGA design files to implement theequations given in eqns 2.40 and 2.41.

2.5.5 Waveforms


32

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Sim

ula

tion

OfSM

PC

Figure 2.13: FPGA Design File of Buck-Boost Converter for PWM wave generation and DAC Interfacing

2.5

Buck

-Boost

Converte

r33

Figure 2.14: FPGA Design File of Buck- Boost Converter for Vc and iL


0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.01−1

0

1

2

0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.01−0.4

−0.3

−0.2

−0.1

0

0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.010

0.2

0.4

0.6

0.8

Vg

V o

i L

time (sec)

Figure 2.15: Vg, Vo and iL waveforms (off-line simulation) for Buck-BoostConverter

Scale: y-axis: all quantities in per unit

Figure 2.16: Vg, Vo and iL waveforms (real time simulation) for Buck-BoostConverter

Scale: y-axis: 1 division = 2V (1 per unit = 5V )

2.6 Conclusion 35

2.6 Conclusion

In this chapter Real Time Simulation of basic Switching Power Convertersis presented. The Real time simulation is done by using Quartus II soft-ware (version 5.0). Results are also verified with MATLAB Simulation re-sults. MATLAB models used for offline simulation are placed in folder namedsimulinkprogramfiles.


Chapter 3

Real-Time Simulation ofSeparately Excited DC Machine

3.1 Introduction

The Direct Current machine have been dominating the field of adjustable speeddrives for over a century; they are still the most common choice if a controlledelectric drive operating over a wide speed range is specified. This is due totheir excellent operational properties and control characteristics.

3.2 Open Loop Control of DC Machine

The DC motor model used in the simulation is shown in Fig. 3.1. The modelrepresents a separetly excited dc motor. The mechanical load is defined by theparameters J , B and mL. The state equations describing the dc motor driveused in the simulation are the followings:

La

di

dt= −RaIa −Keωm + Va (3.1a)

Jdωm

dt= KeIa − Bωm −mL (3.1b)

The equations (3.1) are normalized with the help of rated values of Vb, Ib andωmb. Other base values which can be inferred from these base values. Theequations (3.1) are formulated in a way suitable for block diagram represen-tation.

τebdI∗adt

τmb

dω∗

m

dt

=

[−R∗

a −K∗

e

K∗

e −B∗

] [I∗aω∗

m

]

+

[1 00 −1

] [V ∗

a

m∗

L

]

(3.2)

where x∗ equals to perunitized value of x.

38 Real-Time Simulation of Separately Excited DC Machine

Ia

Va

+

+

_

La

Ra

−E = k

Electrical Section

,Ra La Ω

J = Motar and load Inertia = 8.4 kg−m

φ ek = K = EMF Constant (frequency constant) = 8.5 v/rad/s

aV = Input Voltage = 460 V = Load torqueML

= Armature resistance (0.024 ) and inductance (0.7 mH)

B = Motar and load viscous friction coefficient = 02

Rated speed =500 rpm, Rated Power = 300 kW,

LM

k φ 1J

B

k φ

Ia 1S

E

ω

Mechanical Section

φω

Figure 3.1: DC Motor Model.

Any Electrical machine can be represented in the form of state equations (3.2).A generalized user machine block(Fig 3.2) is developed such that any machineequations can be solved by knowing the state matrix and input matrix.

Multiply

Multiply

Multiplyxn−1

yn−1

A11

A12 ADD

e xn−1

IntegrationBlock

xn

xn−1

τ e∆τ

B11

Va

mLB12

Multiply

Multiply

Multiply

Multiplyxn−1

yn−1

Multiply

ADD IntegrationBlockVa

mL

A21

A22

B21

B22

e yn−1

τ m∆τ

yn

yn−1

Step Size∆τ= A= System Matrix B= Input Matrix

Figure 3.2: Generalized Machine Model.


A Parameters : The details of the separetly excited DC machine and thevalues of other quantities are given in table. 3.1 and 3.2

3.2 Open Loop Control of DC Machine 39

VOLTAGE 460 V

RATED CURRENT 690 A

POWER 300 kW

SPEED 500 rpm

Table 3.1: Details of the DC Motor

Voltage (Vb) 460V

Current (Ib) 690A

Mechanical Speed(ωmb) 2π ∗ Nb

60 = 52.359rad/sec

R∗

a 0.0359

K∗

e 0.9675

m∗

L 1.0000

τeb 0.0011

τmb 0.0726

Step time (∆t) 6.400µ


B PU System Followed : The Table 3.3 shows the digital equivalent for thepu values. The digital equivalent for a negative pu value is chosen as the1’s compliment its corresponding positive pu value.


1 pu FFFFFH 1048575d

0 pu 00000H 0d

-1 pu(24bit) F00001H 15728641d



FPGA Design files of DC Machine are placed in ‘fpga program files’ folder.Similarly simulink files are in ‘simulinkprogramfiles’ folder. Fig. 3.3 is theFPGA design file for DC machine. Real-time simulation of DC machine openloop consumed 4% of overall logic elements in FPGA board.


Figure 3.3: FPGA Design File for DC Machine

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60

0.5

1

1.5

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60

0.5

1

1.5

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6−5

0

5

10

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60

1

2

Time

(1)

(2)

(3)

(4)

(a) (b)

Figure 3.4: DC Machine(1) Input Voltage (2) Load Torque (3) Armature Current (4) Speed.(a) MATLAB/SIMULINK OFF-Line Simulation Waveforms(b) FPGA Real-Time Simulation Waveforms

Fig. 3.4(a) (OFF-Line Simulation Waveforms ) and Fig. 3.4(b) (Real TimeSimulation Waveforms) shows the waveforms obtained for th DC machine inopen loop.

3.3 Closed Loop Control of DC Machine 41

G1 (s)

SpeedFeedback

vω m−fb (s)

vω m−error (s)

ControllerSpeed

GN(s)

Limiter+

ia−error (s)v

ia−fbv (s)

Gc (s)

ControllerCurrent

Limiter+

(s)v refGch (s)

(s)v aωm

G2 (s)

CurrentFeedback

vω m−ref(s) ia−ref (s)v

Chopper

DC MOTOR i

Figure 3.5: Block Diagram of the DC Motor Drive

3.3 Closed Loop Control of DC Machine

In practice,the choice of DC motor drive is normally motivated by the possi-bility of operating over a wide range of the torque/speed plane with low lossesand matching the behaviour of the motor to the needs of the mechanical load.To achieve the desired operating characteristics in the presence of supply-andload -disturbances,feedback control is usually necessary.

Another reason why DC drives are normally contained in feedback loops isthat the armature of a large motor represents a very small impedance whichwhen supplied with nominal voltage would result in an excessive current of upto 10 times the nominal value. Under normal conditions, this is prevented bythe induced armature voltage e, which cancels most of the applied voltage Va

so that only the difference is driving the armature current ia. In transient op-eration,there is always the danger of excessive current due to rapidly changingarmature voltage or speed; the same is true with a steady state overload ofthe motor. It is therefore important to provide a fast current or torque limitto protect the motor, the power supply and the load. This is best realized byFEEDBACK CONTROL establishing an effective safeguard against electricaland mechanical stresses.

In most cases, the user of a controlled drive wants to be able to select areference speed vwm−ref which the motor should maintain as long as it is notoverloaded. The control schematic of a separately excited dc motor drive isshown in Fig. 3.5. The motor drive shown is a speed controlled system. Thedc output of a converter is fed to the armature of the dc drive. The field isseparately excited, and the field supply is kept constant for armature control.The dc motor has a tacho generator whose output is utilized for closing thespeed loop. The output of the tachogenerator is filtered to remove the ripplesto provide the signal, vwm−fb. The speed command vwm−ref is compared to thespeed signal to produce a speed error sinal. This signal is processed througha proportional-plus-integral(PI) controller to determine the torque command.The torque command is limited, to keep it with in safe current limits, and


the current command is obtained by propoer scaling. The armature currentcommand via−ref is compared to the actual armature current via−fb to have azero current error. In case there is an error, a PI current controller processesit to alter the control signal vref . The control signal accordingly modifies thetriggering angle of the converter and so the dc output of the converter.

The inner current loop assures a fast current response and hence also limitsthe current to a safe preset level. This inner current loop makes the convertera linear current amplifier. The outer speed loop ensures that the actual speedis always equal to the command speed and that any transient is overcomewithin the shotest feasible time without exceeding the motor and convertercapability.

3.4 Transfer Functions Of The Subsystems

3.4.1 DC Motor and Load

The equivalent circuit of the separately excited DC motor can be representedas in Fig. 3.5. The transfer function first between speed and input voltage isgiven by

F1 =ωm(s)

Va(s)=

1Ra

11 + sTa

1J

cφ

s

1 + (cφ)2

Ra(Tas+1)Js

=

1cφ

1 + sTem(1 + sTa)

(3.3)

where Ta = La/Ra is electrical time constant and Tem = JRa/(cφ)2 is elec-tromechanical time constant.The transfer function between armature current and input voltage is given by

F2 =ia(s)

Va(s)=

ωm(s)

Va(s)

ia(s)

ωm(s)=

1cφ

1 + sTem(1 + sTa)

Js

cφ

=1

Ra

sTem

1 + sTem(1 + sTa)

(3.4)

Similarly the transfer function between speed and load torque is given by

F3 =ωm(s)

mL(s)= − Ra

(cφ)2

1 + sTa

1 + sTem(1 + sTa)(3.5)

The transfer function between armature current and load torque is given by

F4 =ia(s)

mL(s)=

1cφ

1 + sTem(1 + sTa)(3.6)

3.4 Transfer Functions Of The Subsystems 43

3.4.2 Chopper

The chopper is modeled as first-order lag with a gain of G. The time delay Td

corresponds to the average conduction time. The transfer function is then

Gch(s) =Va(s)

vref(s)=

G

1 + sTd

(3.7)

where G = Vs/vrefm, Vs is input to the chopper and vrefm is the maximumcontrol voltage. Increasing the chopper frequency decreases the delay time,and hence the transfer function becomes a simple gain.

3.4.3 Current and Speed Controllers

The current and speed controllers are of proportional-integral type. They arerepresented as

Gc(s) =vref(s)

via−ref (s) − via−fb(s)=

Kc (1 + sTc)

sTc

(3.8)

GN(s) =via−ref(s)

vwm−ref(s) − vwm−fb(s)=

KN (1 + sTN)

sTN

(3.9)

where the subscripts c and N correspond to the current and speed controllers,respectively. The K and T correspond to the gain and time constants of thecontroller. Design of controllers is discussed in ref. [3]

3.4.4 Current Feedback

The gain of the current feedback is K2. In the case of a filtering requirement, alow-pass filter can be included in the analysis. The equivalent transfer functionis represented as

G2(s) =via−fb(s)

ia(s)=

K2

1 + sT2(3.10)

where T2 is the smoothing filter time constant.

3.4.5 Speed Feedback

The transfer function of the speed feedback filter is

G1(s) =vωm−fb(s)

ωm(s)=

K1

1 + sT1(3.11)

where K1 is gain, T1 is the time constant and vωm−fb is one of the inputs tospeed error block.


3.5 Simulation of DC Motor Drive

The equations for various subsystems are derived in the last section and thenassembled for real time simulation in this section. It is assumed that fieldcurrent is constant.

3.5.1 DC Motor Equations

The motor equations are given by (3.1) and the normalized equations aregiven by (3.2)

3.5.2 Speed-Feedback Filter

The transfer function of the speed feedback filter is given by equation (3.11).In time domain, this equation can be arranged as following:

dvωm−fb

dt=

1

T1(K1ωm − vωm−fb) (3.12)

This equation is normalized and resulted in the following form:

dv∗ωm−fb

dt=

1

T1

(K1ωmb

Vb

ω∗

m − v∗ωm−fb) (3.13)

By using Euler’s method of integration,

v∗ωm−fb(n) = v∗ωm−fb(n− 1) +∆t

T1

(K1ωmb

Vb

ω∗

m(n− 1) − v∗ωm−fb(n− 1)

)

(3.14)

3.5.3 Current-Feedback Filter

The transfer function of the current feedback filter is given by equation (3.10).In time domain, this equation can be arranged as following:

dvia−fb

dt=

1

T2

(K2ia − via−fb) (3.15)


dv∗ia−fb

dt=

1

T2(K2IbVb

i∗a − v∗ia−fb) (3.16)


v∗ia−fb(n) = v∗ia−fb(n− 1) +∆t

T2

(K2IbVb

i∗a(n− 1) − v∗ia−fb(n− 1)

)

(3.17)

3.5 Simulation of DC Motor Drive 45

Fig

ure

3.6:

Filte

r


3.5.4 Speed Controller

The transfer function of the speed controller is given by equation (3.9). Intime domain, this equation can be arranged as following:

via−ref =1

TN

∫

KN (vwm−ref − vwm−fb) dt + KN (vwm−ref − vwm−fb) (3.18)


v∗ia−ref =1

TN

∫

KN (v∗wm−ref − v∗wm−fb) dt︸︷︷︸

I−Controller

+ KN (v∗wm−ref − v∗wm−fb)︸︷︷︸

P−Controller

(3.19)By using Euler’s method of integration,

v∗ia−ref(n) =∆t

TN

KN v∗wm−error(n− 1) + y(n− 1) + KN v∗wm−error(n) (3.20)

where v∗wm−error = v∗wm−ref −v∗wm−fb, y(n−1) is previous value of I-Controller.

In order to maintain the drive system in safe operating region, the currentrefernce v∗ia−ref is limited to allowable maximum limits determined by themotor peak current capabilities. This reference limit is integrated into thesimulation as

0 ≤ v∗ia−ref ≤ v∗ia−ref−max (3.21)

3.5.5 Current Controller

The transfer function of the current controller is given by equation (3.8). Intime domain, this equation can be arranged as following:

vref =1

Tc

∫

Kc (via−ref − via−fb) dt + Kc (via−ref − via−fb) (3.22)


v∗ref =1

Tc

∫

Kc (v∗ia−ref − v∗ia−fb) dt︸︷︷︸

I−Controller

+ Kc (v∗ia−ref − v∗ia−fb)︸︷︷︸

P−Controller

(3.23)


v∗ref(n) =∆t

Tc

Kc v∗

ia−error(n− 1) + y(n− 1) + KN v∗ia−error(n) (3.24)

where v∗ia−error = v∗ia−ref − v∗ia−fb, y(n− 1) is previous value of I-Controller.

3.5 Simulation of DC Motor Drive 47

Fig

ure

3.7:

PI-

Con

trol

ler


Figure 3.8: Saturation

3.5.6 Chopper

The transfer function of the chopper is given by equation (3.7). At highfrequency of chopper, the transfer function becomes a simple gain.

Va

vref

= G (3.25)


V ∗

a = G v∗ref (3.26)

Discretizing the above equation results in

V ∗

a (n) = G v∗ref(n) (3.27)

3.6 Implementation

A. Closed Loop Parameters : The details of the separetly excited DC ma-chine and the values of other quantities are given in table. 3.4.

B. PU System Followed : The Table 3.3 shows the digital equivalent for thepu values. The digital equivalent for a negative pu value is chosen as the1’s compliment its corresponding positive pu value.


FPGA Design files of Closed loop DC Machine are placed in ‘fpga program files’folder. Similarly simulink files are in ‘simulinkprogramfiles’ folder. Fig. 3.6,

3.8 Conclusion 49

DC Bus Voltage 650V

Maximum Current 1200A

Chopper Switching frequency 1000Hz

K1 0.1909

T1 0.0167

K2 0.0083

T2 0.0016

KN 1.0308

TN 0.0837

KC 0.3089

TC 0.0292

G 65

Step time (∆t) 6.400µ


Fig. 3.7 and Fig. 3.8 are the FPGA design files respectively, to implementfilter, PI controller and saturation block.

Figure 3.9 shows the waveforms obtained for th DC motor in close loop.Initially,the motor is running at no load along with full load refernce and 50percent torque is applied after some time. Motor rotates in reverse directionwhen speed reference has changed from positive to negitive.

3.8 Conclusion

DC Motor open loop as well as closed loop has implemented in FPGA basedcontroller. Both Real-time and offline simulation results are presented.


Figure 3.9: DC Motor Drive with Speed and Current Feedback[ (1) ωref (2) mL (3) ia (4) ωm ]

0 0.5 1 1.5 2 2.5−0.05

0

0.05

0 0.5 1 1.5 2 2.5 30

0.5

1

0 0.5 1 1.5 2 2.5−2

0

2

0 0.5 1 1.5 2 2.5−2

0

2

time

ia

ωm

ωref

mL

Figure 3.10: DC Motor Drive with Speed and Current Feedback

Chapter 4

Real-Time Simulation ofInduction Machine

4.1 Introduction

In the past, mostly DC motors alone were used for variable speed applications.With the advances in power electronics, induction motors are replacing DCMotors in variable speed drives. The 3-phase induction motors are most pre-ferred for drive applications because of ruggedness, smaller size and low cost.The basic theory of the squirrel cage induction motor is reviewed here.


The induction motor has a three phase winding on the stator and a rotorcage with end rings which electrically behaves as another three phase winding.When the stator windings are supplied with balanced three phase currents,a revolving magneto motive force is produced in the air gap. If the statorwinding is designed properly, the spatial distribution of the stator mmf at anyinstant of time can be assumed to be sinusoidal. The location of the positivepeak (north pole) of this mmf is taken as its instantaneous position. The speedof rotation of the stator mmf wave is given by

Ns =120 fs

prevolution per minute (4.1)

where fs is the frequency of the stator currents; P is the number of poles.Because of the stator mmf, a rotating flux wave is produced in the airgap

of the machine. This flux wave has also sinusoidal spatial distribution at anyinstant of time and rotates in space in the same direction and with the samespeed as the stator mmf. The speed of the stator mmf (or the flux) is referredto as the synchronous speed.

As the flux sweeps past the rotor conductors, emfs are induced in theseconductors. Since the rotor bars are shorted by the end rings, currents flow in

52 Real-Time Simulation of Induction Machine

R s L ls

R m L m

L ' lr

R ' r

V s V m

w s w r

E ' r = n s V m

1:n

I s I ' r

I o

I c I m

Figure 4.1: Equivalent Circuit

the rotor conductors. The interaction of the rotor currents and flux producestorque and the rotor begins to turn. The rotor attempts to catch up with theflux. However since this would result in disappearance of torque, an equlibriumis reached where the rotor runs at a speed such that the relative motion of theflux is sufficient to produce enough torque to sustain the rotor speed. If therotor runs at a speed of N revolutions per minute, the relative speed of theflux with respect to the rotor is given by

Nr = Ns −N (4.2)

The slip ’s’ of the machine is defined as the ratio Nr/Ns.

Let ωr and ωs be the angular frequencies of the rotor and stator currentsrespectively. The airgap flux rotating at ωs electrical radians per second in-duces back emf Vm in the stator. The flux moves at a speed ωr with respectto the rotor. The corresponding emf induced in the rotor can be written as

E ′

r = n.s.Vm (4.3)

where n is the rotor to stator turns ratio and s is slip.

Therefore, the machine can be represented by an equivalent circuit as shownin figure 4.1. The two sides of the tranformer work at different frequencies,namely, ωr and ωs.

4.3 Modelling of Induction Machine using Space Phasors 53

ε

TransformationSpace Vectoris1

is2

is3

ε

ir1

ir2

ir3

isa

iraisb

irb

ar

rb

bs

as

Figure 4.2: Twophase equivalent of a 3-phase induction motor

4.3 Modelling of Induction Machine using Space Pha-sors

The symmetrical three phase squirrel cage induction motor has a three phasesystem of coils on the stator and a cage on the rotor which can be consideredto be equivalent to a three phase winding. The two sets of windings can berepresented by two equivalent two phase coils as shown in Fig. 4.2. The rotoraxis makes an angle ε (t) with respect to the stator axis. Two current spacephasors is (t) and ir (t) can be defined for the stator and rotor current asfollows:

is (t) = isa (t) + jisb (t) (4.4)

ir (t) = ira (t) + jirb (t) (4.5)

The flux linkages of various coils can be written down as follows

ψsa (t) = Lsisa (t) +Mira (t) cosε (t) −Mirb (t) sinε (t) (4.6)

ψsb (t) = Lsisb (t) +Mira (t) sinε (t) +Mirb (t) cosε (t) (4.7)

whereLs is self inductance of stator coils,M is the maximum value of mutual inductance between stator and rotor coils.

Combining equations 4.6 and 4.7 to form the stator flux space phasor.

ψs(t) = ψsa (t) + jψsb (t) = Lsis (t) +Mir (t) ejε(t) (4.8)


Similarly the rotor flux linkage space phasor can be derived as

ψr(t) = ψra (t) + jψrb (t) = Lrir (t) +Mis (t) e−jε(t) (4.9)

Note that Eqn 4.8 is with respect to stator coordinates and Eqn 4.9 iswith respect to rotor coordinates. Multiplication of ejε(t) results in clockwiserotation of the coordinate system by an angle of ε (t), while e−jε(t) results inanticlockwise rotation of the coordinate system by the same angle.

The voltage-current equations for the stator and rotor windings can bewritten as follows

vsa (t) = Rsisa (t) +dψsa (t)

dt(4.10)

vsb (t) = Rsisb (t) +dψsb (t)

dt(4.11)

vra (t) = Rrira (t) +dψra (t)

dt(4.12)

vrb (t) = Rrirb (t) +dψrb (t)

dt(4.13)

With the help of equations 4.8, 4.9 the above equations can be rewritten asspace phasors as follows,

vs (t) = vsa + jvsb = Rsis (t) + Ls

dis (t)

dt+M

d

dt[ir (t) ejε(t)] (4.14)

vr (t) = vra + jvrb = Rrir (t) + Lr

dir (t)

dt+M

d

dt[is (t) e−jε(t)] (4.15)

For a squirrel cage induction motor vr (t) = 0. With the above two equa-tions, the electrical behaviour of the machine is obtained.

It can also be shown that the torque developed by the machine is given by

Md (t) =2

3

P

2MIm[is (t) [ir (t) ejε(t)]∗] (4.16)

Transformation of the rotor current equation 4.9 to the stator stationarycoordinates can be done by multiplying ejε(t),

isr (t) = ir (t) ejε(t) (4.17)

Simplifying the above equations and separating out the real and imaginaryparts, the following equations can be obtained.

Rsisa (t)+σLs

disa (t)

dt−M2

Lr

ωisb (t)−M

Lr

Rrisra (t)−Mωisrb (t) = vsa (t) (4.18)


Rsisb (t) + σLs

disb (t)

dt+M2

Lr

ωisa (t) +Mωisra (t)−M

Lr

Rrisrb (t) = vsb (t) (4.19)

Rrisra (t) + σLr

disra (t)

dt− M

Ls

Rsisa (t) +Mωisb (t) + Lrωisrb (t) = −M

Ls

vsa (t)

(4.20)

Rrisrb (t) + σLr

disrb (t)

dt−Mωisa (t) − M

Ls

Rsisb (t) − Lrωisra (t) = −M

Ls

vsb (t)

(4.21)

Jdωm

dt=

2

3

P

2M [isra (t) isb (t) − isrb (t) isa (t)] −Ml (4.22)

P

2ωm = ω =

dε (t)

dt(4.23)

where σ =[

1 − M2

LrLs

]

ωm - rotor speed in mechanical rad/secω-rotor speed in electrical rad/secJ-moment of inertiaMl-Load torque

The above equations describe the complete dynamic behaviour of the in-duction machine. The Eqns. 4.18 and 4.19 serves the purpose of determningthe stator voltage vs (t) and the eqns. 4.20 and 4.21 corresponding to therotor, determine the machine electrical dynamic behaviour. The Eqn. 4.22determines the mechanical dynamic behaviour of the machine.

4.4 Implementation

A. Parameters : The details of the induction motor is presented in Table. 4.1.The parameters of the Induction motor used in the simulation programare shown in the Table 4.2.

VOLTAGE 240 VCURRENT 40 APOWER 1.5 KWPOLES (P) 4SPEED 3000 rpm

Table 4.1: Details of the Induction Motor


Quantity ValueRs O.2ΩLls 7.2mHRr 0.4011ΩLlr 3.6mHM 88mHLs = M + Lls 95.2mHLr = M + Llr 91.6mHJ 0.2Kg −m2

B 0.003

Table 4.2: Parameters of the Induction Motor

B. Base Values for Different Quantities : As the implementation is digitallyrealized, there arises the need for following a pu system for simple under-standing. For perunitization of different quantities, the base values arerequired, which can be chosen as per convenience. The Table. 4.3 showsthe base values for voltage (chosen as per phase rated voltage of IM),current (chosen as more than the rated line current of IM and less thantransient peak current) and frequency (chosen as rated frequency of IM).The other bases are calculated from the above mentioned base quantities.

Voltage (Vb) 240VCurrent (Ib) 200AFrequency (fb) 50HzFrequency in rad/sec (ωb) 2π ∗ fb = 314.16rad/sec

Resistance(Rb)Vb

Ib

= 1.2Ω

Mechanical Speed(ωmb)ωb

P/2 = 157.08rad/sec

Torque(Mb)3∗Vb∗Ib

ωmb

= 916.73N −m

Table 4.3: Base Values

C. PU System Followed : The Table 4.4 shows the digital equivalent for thepu values. The digital equivalent for a negative pu value is chosen as the1’s compliment its corresponding positive pu value.

pu value Equivalent digital Value Equivalent decimal value2 pu 7FFFH 32767d1 pu 3FFFH 16383d0 pu 000H 0d-1 pu(16bit) C000H 49152d-2 pu(16bit) 8000H 32768d


4.5 Normalized Equations 57

4.5 Normalized Equations

In this section, all the equations are perunitized and are made ready for imple-mentation. The sampling time for the implementation is chosen as 25.6 µsec.The eqn. 4.18 is repeated here.

Rsisa (t)+σLs

disa (t)

dt= vsa (t)+

M2

Lr

ωisb (t)+M

Lr

Rrisra (t)+Mωisrb (t) (4.24)

Dividing the above equation by Vb,

Rs(pu)isa(pu) (t) + σLs

disa(pu) (t)

dt= esa(pu) (t) where

esa(pu) (t) =vsa(pu) (t) +M2

Lr

ωb

Rb

ωpuisb(pu) (t) +M

Lr

Rr(pu)isra(pu) (t) +M

ωb

Rb

ωpuisrb(pu) (t)

=⇒ isa(pu) (t) =1

σLs

∫(esa(pu) (t) −Rs(pu)isa(pu) (t)

)dt

Using the Eulers Method of integration, the equation in digital domain can bewritten as

isa (n) = isa (n− 1) +(esa (n− 1) −Rs(pu)isa (n− 1)

) Ts

σLs

Note that, the sampling time Ts for the implementation is chosen as 25.6 µsec.

isa (n) = isa (n− 1) + (esa (n− 1) − 0.17puisa (n− 1)) 0.0024pu (4.25)

similarly other equations 4.19, 4.20, 4.21 and 4.22 can also be normalized. Ta-ble. 4.5 summarizes all the variables in the form easy for digital realization. Allthe operations are basically arithimetic operations. The digital realization forthe above equations requires adders, subtractors, multipliers and dividers. Allthese entities are available in the library of Quartus-II tool. Apart from thesearithimetic logic entities, D-Flip Flops are also needed for storing previousdata values, in the case of performing integration.


FPGA Design files of Induction Motor are placed in ‘fpga program files’ folder.Similarly simulink files are in ‘simulinkprogramfiles’ folder. Fig. 4.3 to Fig. 4.8are the FPGA design files to implements the equations given in table 4.5.

4.7 Waveforms

The program developed (using the equations in table. 4.5) for direct onlinecontrol of Induction machine in Quartus II tool are downloaded into FPGAboard. The waveforms are recorded and are compared with the off-line simu-lation waveforms.


Vsa (n)(1.5 ∗

√2)

puVs1 (n)

Vsb (n)(0.866 ∗

√2)

pu(Vs2 (n) − Vs3 (n))

isa (n) isa (n− 1) − 0.00048puisa (n− 1) + 0.064puω (n− 1) isb (n− 1) + 0.00093puisra (n− 1)

+0.066puω (n− 1) isrb (n− 1) + 0.00288puVsa (n− 1)

isb (n) isb (n− 1) − 0.064puω (n− 1) isa (n− 1) − 0.00048puisb (n− 1) − 0.066puω (n− 1) isra (n− 1)

+0.00093puisrb (n− 1) + 0.00288puVsa (n− 1)

isra (n) isra (n− 1) + 0.00046puisa (n− 1) − 0.069puω (n− 1) isb (n− 1) − 0.001puisra (n− 1)

−0.072puω (n− 1) isrb (n− 1) − 0.00276puVsb (n− 1)

isrb (n) isrb (n− 1) + 0.069puω (n− 1) isa (n− 1) + 0.00046puisb (n− 1) + 0.072puω (n− 1) isra (n− 1)

−0.001puisrb (n− 1) − 0.00276puVsb (n− 1)

ωm (n) ωm (n− 1) + [0.0038pu (isra (n) isb (n) − isrb (n) isa (n))] − 0.00074puMl (n− 1)

ω (n) ωm (n)

Table 4.5: Equations for implementing in Digital Domain

4.7

Wavefo

rms

59

Figure 4.3: FPGA Design File for isa


Fig

ure

4.4:

FP

GA

Des

ign

File

fori s

b

4.7

Wavefo

rms

61

Figure 4.5: FPGA Design File for isra


Fig

ure

4.6:

FP

GA

Des

ign

File

foris r

b

4.7

Wavefo

rms

63

Figure 4.7: FPGA Design File for ωm


Figure 4.8: FPGA Design File for Eulers Integration

4.7 Waveforms 65

Figure 4.9: Vsa*k and Vsb*k waveforms where k=1/(1.5*sqrt(2))Scale: y-axis: 1 per unit = 5V = 240v

0.5 0.51 0.52 0.53 0.54 0.55 0.56 0.57 0.58 0.59 0.6−3

−2

−1

0

1

2

3

0.5 0.51 0.52 0.53 0.54 0.55 0.56 0.57 0.58 0.59 0.6−3

−2

−1

0

1

2

3

Time

Vsa

Vsb

Figure 4.10: Vsa and Vsb waveformsScale: y-axis: 1 per unit = 1V = 240v


Figure 4.11: isa,isb, isra and isrb waveforms

Scale: y-axis: 1 per unit = 5V = 200A

0.5 0.6 0.7 0.8 0.9 1 1.1−1

0

1

0.5 0.6 0.7 0.8 0.9 1 1.1−1

0

1

0.5 0.6 0.7 0.8 0.9 1 1.1−1

0

1

0.5 0.6 0.7 0.8 0.9 1 1.1−1

0

1

Time

Isa

Isb

Isra

Isrb

Figure 4.12: isa,isb, isra and isrb waveforms

Scale: y-axis: 1 per unit = 1V= 200A

4.7 Waveforms 67

Figure 4.13: ωm and Mg ∗ 0.2/16 waveformsScale: y-axis1: 1 per unit = 5V = 157.08rad/sec;

y-axis2: 1 per unit =5V= 916.73N −m

0 0.2 0.4 0.6 0.8 1−0.2

0

0.2

0.4

0.6

0.8

1

1.2

0 0.2 0.4 0.6 0.8 1−0.04

−0.02

0

0.02

0.04

0.06

Time

ωm(pu)

Mg*0.2

Figure 4.14: ωm and Mg ∗ 0.2 waveformsScale: y-axis1: 1 per unit = 1V = 157.08rad/sec;

y-axis2: 1 per unit = 1V = 916.73N −m


4.8 Conclusion

The principle of direct on line start Induction Motor has been explained. It isimplemented in FPGA based controller. Both Real-time and offline simulationresults are presented.

Chapter 5

V/F Control of InductionMotor Drive

5.1 Introduction

Variable Speed Drives (VSDs) are increasingly becoming popular in the indus-try. Many of the speed control applications such as Fan/Pump drives do notrequire very good dynamic performance. In such appications the most suitablemethod of speed control of Induction Motors is V/F control. In this Chapter,the implementation of a V/F Drive controller in FPGA is explained.

5.2 Basic Principle of V/F operation

By keeping the airgap flux constant, and varying the stator frequency ωs, afamily of torque speed curves can be obtained for the Induction Motor asshown in Fig. 5.1. This method of speed control is also referred to as constantflux control. Note that constant flux control is only possible up to ratedvoltage and frequency. For further increase in the frequency beyond ratedfrequency, if the voltage be increased proportionally this would exceed therating of the machine. Therefore, beyond the rated frequency the peak torquecapability of the motor will come down as the airgap flux reduces below therated value. This region is known as field weakening region. To keep theairgap flux constant, it is sufficient to keep the ratio of induced emf to statorfrequency constant [5]. But this is difficult as the induced emf cannot bemeasured directly. However this can be done in an approximate manner bykeeping the ratio of terminal voltage Vs to ωs a constant. Hence this method ispopularly known as V/F control. The terminal voltage and the airgap voltageare reasonably close in magnitude at speeds above 10% of rated speed. At verylow speeds (and hence stator frequencies) the drop in the stator resistance andleakage reactance becomes appreciable in magnitude compared to the airgapvoltage. Therefore, at low speeds, keeping Vs

ωsconstant is not equivalent to

70 V/F Control of Induction Motor Drive

Tmax

Speed

f3f1 f4f2

Torq

ue

Field weakeningregion

Figure 5.1: Torque-Speed Characteristics of Induction Motor for ConstantFlux Control

keeping the flux constant. To some extent the drop in torque ability at lowspeeds can be counterbalanced by giving a boost to the stator voltage Vs atlow frequencies above the constant Vs

fvalue. Fig. 5.2 shows one example of

a v/f relation. In a V/F drive, the controller produces the required reference

fs(pu)

Vs(pu)

1.00.1

0.1

1.0

Figure 5.2: V/F relation including low frequency voltage boost

frequency command in accordance with the v/f relation. This command is thenused by a modulator to produce the gating pulses for the inverter. The inverter

5.3 Sine-Triangle Modulation 71

subsequently drives the Induction Motor. In the following section a popularmodulation technique known as Sine-Triangle Pulse Width Modulation (Sine-PWM) is explained.

5.3 Sine-Triangle Modulation

In Sine-Triangle modulation the duty cycle of the inverter switches is variedin a sinusoidal manner. Because of this, the average of the output voltage ineach switching cycle will also vary sinusoidally [5]. This results in an outputvoltage whose harmonics are at the switching frequency and its sidebands.

For obtaining Sine-Triangle PWM, the modulating sine wave is comparedwith a triangular carrier. For three-phase inverter, three reference sine waveswhich are shifted each other by 120o are compared against the carrier. Thereference waves are produced by the controller preceding the modulator. ThePWM signals thus obtained are used for the upper switches of each inverterlegs. Fig. 5.3 shows the production of PWM signals for one phase. The lowerswitches are controlled by the complimentary signals for the respective upperswitches. Fig. 5.4 shows the three-phase Voltage Source Inverter (VSI). Thegate pulses for the switches are marked in the figure.

The amplitude Ar of the reference sine wave is kept less than the amplitudeAc of the carrier for linear modulation. The ratio m = Ar

Acis called modulation

index. The maximum value ofm is 1 for linear modulation. For m greater than1, the middle pulses begin merging. This will introduce lower order harmonics.This case is known as overmodulation. Here only linear modulation is dealtwith.

For varying the amplitude of the output voltages produced by the VSI,the modulation index is varied. Similarly, for varying the output frequency,the referece frequency is varied. For low power drives where higher switchingfrequency is allowed, synchronisation of carrier and reference is not critical ifthe frequency ratio mf = fc

fris more than 21 [5]. In the forgoing discussion,

asynchronous modulation is assumed.

Tc

Tr

ArAc

PWM

1 pu

2 pu

Figure 5.3: Sine-Triangle PWM


SwSvSu

Su SwSv

DC

link U

VW

Figure 5.4: Three Phase VSI

5.4 Implementation of V/F Sine-Triangle Modulator inFPGA

In this section implementation of a V/F sine-triangle modulator with asyn-chronous PWM is described. The logical steps can be summarized as follows:

• Generation of V/F sine references

• Generation of Triangle carrier

• PWM generation

• Slow Start

These are detailed in the following.

5.4.1 Generation of V/F sine waves

For sine wave generation 1024 samples per cycle are used. For each sample,the angle θ is incremented in steps of ∆θ. Calculation of ∆θ is as follows:

θ =

∫

ωdt (5.1)

∆θ = 2πfTs (5.2)

5.4 Implementation of V/F Sine-Triangle Modulator in FPGA 73

where Ts is the sampling time.

∆θpu = fb.Ts.fpu

= 50 × 102.4µs× fpu

= 5.12 × 10−3 × fpu (5.3)

It is to be noted that θb is 2π and fb is 50Hz. In the digital implementation,1 p.u is 3FFFh, or 16383d. So, ∆θpu is expressed in digital domain as follows:

∆θ =(16383d × 5.12 × 10−3

)fpu

= 84d × fpu (5.4)

∆θ (n) = ∆θ (n− 1) + ∆θ (5.5)

where ∆θ (n) is the nth sample and ∆θ (n− 1) is the (n − 1)th sample of θ.The above is realized in the FPGA as shown in Fig. 5.5. The sine values foreach θ are stored in ROM. The address for each step in angle is generated asshown in the Fig. 5.5. In the figure, note that the p.u ∆θ, as in Eqn. 5.4, isobtained as a 32-bit number, and it has been scaled down to 16 bit. This isdone by dividing ∆θ[31..0] by 3FFFh. This way, it is ensured that ∆θ remainsperunitized.

The sine values for 1024 samples are stored in a ROM, with 10bit-wideaddress bus. The address generated as shown in Fig. 5.5 is to be scaled downto 10 bit. Counter10 is the 10th bit of the up-counter, with a period of 102.4µs.The sine values can be generated by a C or MATLAB program. [6], and storedin the ROM configured in FPGA. The sine wave amplitude is chosen as 1 p.u(3FFFh). Fig. 5.6 shows the sine wave.

For generating the three-phase waveforms, the respective angles, θy andθb are calculated by subtracting 120o and 240o from the R-phase angle, θr.Digitally, 120o is 5461d and 240o is 10922d, because 360o is represented by3FFFh. For each phase a sine table may be used. Another way is to havetwo sine tables for the two phases and use the three-phase balance relation(Vr + Vy + Vb = 0) to get the third sine wave.

Keeping V/F ratio constant

Per-unit values of maximum sine value and maximum frequency are the same(3FFFh). Hence, scaling of sine value for a particular reference frequency canbe done by simply multiplying the sine values by the reference frequency withproper scaling. Fig. 5.7 shows the entire scheme in block diagram.


84H

∆ θ[31..0]

freq_ref[15..0]

16

16

(n)[15..0]θ

[29..14]θ∆

(n−1)[15..0]θ

address_theta[15..0]16383D

(n)[15..0]θCounter10

clk

Q D

Figure 5.5: Theta Address Generation Scheme

0

1 pu

−1 puC000 H

3FFF H

180o 360o

Figure 5.6: p.u Sine wave

5461d

10922d

A−B

A−B

addr_theta_R[15..0]addr_theta_Y[15..0]

addr_theta_Y[15..0]

addr_theta_R[15..0]

addr_theta_B[15..0]

addr_theta_B[15..0]

ROM

freq_ref[15..0]

counter10clk

ROM

freq_ref[15..0]clk

ROM

freq_ref[15..0]clk

sine_val_R[31..0]

sine_val_Y[31..0]

sine_val_B[31..0]counter10

counter10

Figure 5.7: Generation of Three-phase V/F Sine waves

5.4.2 Carrier Generation

The carrier used for Sine-Triangle Modulation is a triangular waveform. Inthe FPGA, it is generated digitally by using a counter. The triangular carrier,

5.4 Implementation of V/F Sine-Triangle Modulator in FPGA 75

in analog methods is usually a bipolar signal. In digital implementation boththe modulating signal and the carrier used are unipolar in nature. Hence thepeak of the carrier is kept at 2 p.u. The sine modulating signals are given anoffset of 1 p.u, so that they also become unipolar.

A binary up-down counter is configured as shown in Fig. 5.8 for generatingthe required carrier. 1 p.u is set as 3FFH. Since the carrier peak is set at 2p.u, the maximum count is 7FFH. The p.u value for the amplitude of carrieris chosen based on the switching frequency required. In the FPGA controllerboard used, the clock frequency is 20MHz. This means for counting up to7FFH, it takes 102.4µs. The frequency of carrier and hence the switchingfrequency used here is nearly 5 kHz. The period of the MSB of the 12-bitcounter is 204.8µs.

sµ102.4 sµ204.8

Subcount[11..0]

10

0

7FFh

count11

trianglecarrier

2047 D

12 Bit UpCounter

MU

X

A−B

clock

count11

Trianglecarrier

12

2048D

count[11..0]

12

Sub

Figure 5.8: Carrier Generation Scheme in FPGA


5.4.3 Generation of PWM

The carrier is compared with the three v/f sine waves generated as describedin previous sections individually to get the three PWM pulses. Before com-parison, the sine waves have to be given an offset of 1 p.u so that they becomeunipolar. Also, it has to be noted that the generated sine values are 16 bitswide and the triangle carrier is only 12 bits wide. So, the sine values have tobe scaled accordingly, by selecting bits [15..4]. Fig. 5.9 shows the generatedtriangular carrier and the shifted sine wave for one phase. PWM generationfor one phase is shown in Fig. 5.10. The remaining signals are generated simi-larly with the respective sine values. Fig. 5.11 shows the PWM signals for theupper switches in the U and V legs of VSI.

Figure 5.9: Sine Wave and Triangular Carrier

Comparator12 bit

1024d

triangle_carrier[11..0]

sine_val_R[15..4]

shifted_sine_R[11..0]

PWM_R

Figure 5.10: PWM Generation for U-phase

5.5 Open-loop V/F Control of IM - Real-time Simulation 77

Figure 5.11: PWM Signals for U and V phases

5.4.4 Slow Start of Induction Motor

To keep the motor currents within safe limits during starting, the speed refer-ence has to be incremented slowly in a ramp fashion. The required rampingtime depends on the motor full load slip. The slow-starting scheme is describedin Fig. 5.12. Fig. 5.13 shows the slow rise of the frequency reference signal andthe corresponding sinusoidal reference produced by the v/f signal generator.

5.5 Open-loop V/F Control of IM - Real-time Simula-tion

Once the modulators are developed as described in previous sections, perform-ing a real-time simulation of the entire drive is possible if we can model theVSI and the Induction Motor in FPGA. Modelling of Induction Motor is dealtwith in Ch. 4. Modelling of a VSI is a straight forward task, if we assume idealswitches. The equations are algebraic in nature, and are directly converted totheir digital per-unit equivalent.

The pole voltages of the VSI with respect to the DC link negative point


MU

X

up/down

Counter

enable

slow_start_clock clk

a<b

count enable

clk

D Q

enclk

freq_input[15..0]

MU

X

freq_ref[15..0]

a=b enable

a=ba<ba>b

a>ba<b

freq_cmd[15..0]

a=b

a

b

freq_ref[15..0]

freq_cmd[15..0] compare

Figure 5.12: Slow Starting Logic

Figure 5.13: Slow Starting V/F Sine Wave Reference

can be expressed in terms of the switch states and DC link voltage, as:

Vu(t) = VDC .Su

Vv(t) = VDC .Sv

Vw(t) = VDC .Sw (5.6)

5.5 Open-loop V/F Control of IM - Real-time Simulation 79

The line voltages are then given by,

Vuv(t) = Vu(t) − Vv(t)

Vvw(t) = Vv(t) − Vw(t)

Vwu(t) = Vw(t) − Vu(t) (5.7)

The line-neutral voltages at the load are evaluated from the above, as

Vun(t) =Vuv(t) − Vwu(t)

3

Vvn(t) =Vvw(t) − Vuv(t)

3

Vwn(t) =Vwu(t) − Vvw(t)

3(5.8)

In the digital implementation of the above equations, 3FFFh is assumed as 1p.u voltage. The implementation of the model in FPGA is shown in Fig. 5.14.Interconnection of different modules of the entire system for real-time sim-ulation is shown in Fig. 5.15.Some of the important results are shown inFigs. 5.16(a) to 5.16(b).

VDC

VDC

VDC

Vuv

Vwu

VvwVv

Vw

Vu

Vv

Vw

Vu

Su

Sv

Sw

Vuv

Vwu

Vun

5431d

SUB

Vvw

Vuv

Vvn

5431d

SUB

Vwu

Vvw

Vwn

5431d

SUB

MU

XM

UX

MU

X

SUB

SUB

SUB

16

16

16

16

16

16

16

16

16

16

16

16

0

0

0

Figure 5.14: VSI Model Implementation in FPGA


ModulatorInverterModel

InductionMotorModel

v/f sine waves

Timing and ControlSignals

(Master Counter/ carrier generation)

Slow StartLogic

Su

Sv

Sw

Vu

Vv

Vw

Speed

Torque

Clock Vdc(p.u)

freq_reffreq_command

Clock

Figure 5.15: Interconnection of Different Modules for v/f Drive.

(a) (b)

Figure 5.16: Real-Time Simulation:(a) Speed Response for Step Commands(b) Output Line and Neutral Voltages of Inverter Model

5.6 Conclusion 81

5.6 Conclusion

Basic principles of V/F control scheme for Induction Motor are explained.Developing a v/f controller has been described. The modulation used in thecontroller is on Sine-triangle modulation. Implementation details of modulatorand the v/f controller in the FPGA controller board is also discussed. Finally,an entire open-loop v/f drive consisting of a VSI and an Induction motor issimulated in real-time and the results are given. This shows the capabilityof the FPGA controller board to work as a full-fledged control and real-timesimulation platform.


Chapter 6

Real-Time Simulation OfSwitched Reluctance Motor

6.1 Introduction

The SR motor differs from the conventional motors in many respects. Themotor has saliency both in stator and rotor. The excitation is limited tostator only. The torque is developed by the tendency of the magnetic circuitto adopt a configuration of minimum reluctance. The excitation currents areunidirectional and discontinuous in nature. The stator phases are sequentiallyexcited to obtain continuous rotation. So the SR motor cannot be operatedwith either AC or DC regular power sources. It has to be necessarily operatedfrom a switching power converter.


In SR motor, when a particular phase is excited, the flux in that phase willtry to align the nearest rotor pole along the corresponding stator pole axis.The aligned position between the stator and the rotor pole provides minimumreluctance. This reluctance torque mechanism can be explained with the helpof the diagram in Fig. 6.1. The figure shows that the rotor pole is lying alongthe axis OA. For a counter clockwise rotation, this position of the rotor isreferred as unaligned position (0) with respect to Ph1. After 30 movementof the rotor in the same direction, the same rotor pole will lie along OB, whichis referred as the aligned position (30) for Ph1. In Fig. 6.1, the rotor is shownin aligned position with respect to Ph3 and in unlaigned position with respectto Ph1, whereas it is at 15 position with respect to Ph2. On the account ofthe saliency in the rotor, the inductance(L) of the exciting coil is a functionof rotor position.

84 Real-Time Simulation Of Switched Reluctance Motor

Figure 6.1: Cross-section of and 8/6 pole 4-phase SR Motor

Consider the stator winding excited from a source voltage v

v = Ri+dψ

dt(6.1)

v = sourcevoltagei = coilcurrentR = coilresistanceψ = fluxlinkageL = coilinductance

v = Ri+d(Li)

dt(6.2)

L is a function of the rotor position. Equation 6.2 canbe decomposed as

v = Ri + Ldi

dt+ iω

dL

dθ(6.3)

ω = rotorspeedθ = rotorposition

The applied voltage is dropped in three parts, namely resistive drop(iR),inductive drop(Ldi/dt) and speed dependent counter emf (iωdL/dθ). It maybe noted that (unlike other standard machines) the counter emf exists onlywhen there is an inductance gradient with respect to position(dL/dθ 6= 0). Wemay now see the power relatinship,

vi = Ri2 + iLdi

dt+ i2ω

dL

dθ(6.4)

6.3 Inductance Gradient (L vs θ) 85

The above equation may be now arranged as

vi = Ri2 +d(Li2/2)

dt+ Tgω (6.5)

Tg = i2/2dL

dθ(6.6)

Equation 6.5 gives the power flow in the machine. The input power is madeup of resistive loss (i2R), rate of change of stored energy(d(Li2/2)/dt), and theconverted mechanical power(Tgω).

Equation 6.6 condenses the torque generating mechanism in the machine.Torque generation requires an excitation current in the coil and inductancegradient in the coil. the polarity of the generated torque is the independent ofthe polarity of the excitation current. The polarity of the generated torque isdependent only on the polarity of the inductance gradient(dL/dθ).

6.3 Inductance Gradient (L vs θ)

Figure 6.2: Idealised Inductance Profile of the Four Different Phases

For an 8/6 pole SR motor, the variation in self-inductances of the differentphases with respect to rotor position will be as in Fig. 6.2, when the followingassumptions are made-

1. all the phases are identical

2. magnetic saturation and fringing are neglected


3. pole widths of the stator and the rotor are the same and

4. the stator has a pole width to pitch of 0.5.

The inductance of each phase repeats periodically at 60 as shown in Fig. 6.2.The phase difference between two consecutive phases is 15. The winding canbe excited either in the positive or negative gradient region of the inductanceprofile. If the magnetic circuit is assumed to have no mutual coupling betweenphases and the magnetic characteristics is linear, the torque developed in SRmotor can be expressed as given by Eqn. 6.6.

By causing excitation during the positive or negative slope region of theinductance profile, the machine can be made to develop positive or negativetorque. By sequential switching of the phases, the motor can be driven ineither direction. In this set-up, the switching sequence for forward rotation(anticlockwise from the shaft end) is Ph1-Ph2-Ph3-Ph4-Ph1. The sequencefor the reverse rotation (clockwise) will be Ph4-Ph3-Ph2-Ph1-Ph4. It canbe concluded that the motor can be run in either direction and for both thedirections of rotation, the torque can be either positive or negative. Therefore,all four quadrant operation is possible using this motor.

Each phase is switched on and switched off at least once in every 60. Thisis called the fundamental switching frequency for the SR motor. During eachfundamental switching period all the phases are excited once and the intervalbetween the excitation of two consecutive phases are called the stroke angle.The total number of strokes per revolution (n), stroke angle (qstroke ) andfundamental switching frequency (f1) in one one phase can be expressed as,

n = qNr (6.7)

θstroke =2π

qNr

(6.8)

f1 =r.p.m

60Nr (6.9)

where, q is number of phases and Nr is the number of rotor poles. For an8/6 motor, strokes per revolution is 24, stroke angle is 15 and fundamentalswitching frequency for rated speed (1500 rpm) is 150Hz. Since switching ofphases are done in accordance with the information of rotor position, a positionsensor and a switching power converter are essential for an SR motor drive.

6.4 Flux-Linkage Characterstics

When a voltage pulse is applied to one of the phases of SRM, with all otherphases open, its voltage equation is given by

v = Ri+dψ

dt(6.10)

6.5 Torque Characterstics 87

Figure 6.3: Flux-linkage Characterstics

where v is the instantaneous voltage across the phase winding; R is its resis-tance and i the current. The flux-linkage ψ is,

ψ =

∫

(v − Ri)dt (6.11)

The flux-linkage, can be computed for different values of current with thehelp of Eqn. 6.11. Flux-linkage is measured for a set of rotor positions spanningfrom 0 to 30 at the step of 1. Since the inductance profile is symmetric withrespect to the aligned position of a particular phase the flux-linkage charac-teristics of a phase will also be symmetric with respect to the aligned position(30). Flux-linkage characteristics of a 4 kW, 8/6 pole SRM are given inFig. 6.3.

The static flux-linkage characteristics can be approximated by the followingmathematical expression.

i = K1(θ)ψ + (ψ > ψ1)K2(θ)(ψ − ψ1)2 + (ψ > ψ2)K3(θ)(ψ − ψ2)

3 (6.12)

where ψ1,ψ2 are constants; K1(θ),K2(θ), K3(θ) are functions of position. Theabove parameters K1(θ),K2(θ), K3(θ) are stored in a look-up table for every2. Linear interpolation can be used for intermediate values. The said valuesare given in tabular form in Table 6.1.

6.5 Torque Characterstics

Once, the value of current and position of a particular phase is known by 6.12,the instantaneous torque due to that particular phase can be found using thestored static torque data, T = f(ij, θj), given by table 6.2 and 6.3. In thesimiliar process, the torque due to other conducting phases also may be found.


Table 6.1:Position(θ) K1 K2 K3 ψ1 ψ2

0 68 0 0 0.2 0.45

2 66.75 0 0 0.2 0.45

4 65 0 0 0.2 0.45

6 60 0 0 0.2 0.45

8 52.5 0 0 0.2 0.45

10 42 20 0 0.2 0.45

12 29 48 0 0.2 0.45

14 22 40 200 0.2 0.45

16 17.5 25 400 0.2 0.45

18 14.5 13.5 300 0.2 0.45

20 13 5.5 200 0.2 0.45

22 12 1.5 150 0.2 0.45

24 11 0 125 0.2 0.45

26 10 0 110 0.2 0.45

28 8.9 0 105 0.2 0.45

30 8.5 0 110 0.2 0.45

0 10 20 30 40 50 60−40

−30

−20

−10

0

10

20

30

40

Figure 6.4: Torque Characterstics

The summation of all the phase torques at any instant gives the instantaneoustorque of the motor. Torque characteristics of a 4 kW, 8/6 pole SRM are givenin Fig. 6.4.

6.5 Torque Characterstics 89

Table 6.2: TorqueCurrent(A) 0 1 2 3 4 5 6 7 8 9 10

theta

0 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000

2 0.00000 0.00361 0.01787 0.02812 0.01801 0.00308 0.00343 0.00334 0.00264 0.00551 0.01451

4 0.00000 0.00690 0.02246 0.07362 0.13850 0.21330 0.32130 0.44540 0.58860 0.75030 0.91850

6 0.00000 0.01330 0.05761 0.10840 0.18600 0.30410 0.45740 0.64440 0.85890 1.11600 1.40700

8 0.00000 0.01440 0.07226 0.22610 0.47110 0.76540 1.12700 1.56500 2.08500 2.69000 3.37200

10 0.00000 0.09736 0.38110 0.86270 1.54300 2.44900 3.54700 4.80800 6.21700 7.71200 9.30100

12 0.00000 0.12260 0.52270 1.25100 2.29300 3.63800 5.25500 7.07300 9.03400 11.08000 13.16000

14 0.00000 0.12260 0.52820 1.27800 2.36600 3.76800 5.45400 7.34900 9.39800 11.54000 13.73000

16 0.00000 0.05792 0.35600 1.00000 1.98800 3.30900 4.91900 6.74300 8.73200 10.83000 13.00000

18 0.00000 0.10010 0.45060 1.14900 2.19300 3.55200 5.19600 7.04500 9.03000 11.12000 13.27000

20 0.00000 0.08709 0.41210 1.06600 2.05100 3.33600 4.88100 6.61900 8.48800 10.44000 12.45000

22 0.00000 0.01385 0.23870 0.78180 1.62600 2.75200 4.10200 5.61500 7.23700 8.89900 10.56000

24 0.00000 0.08618 0.40740 1.04100 1.96400 3.10000 4.41000 5.82000 7.23100 8.57900 9.86000

26 0.00000 0.11910 0.46780 1.11000 1.99300 3.04100 4.21900 5.39400 6.47300 7.43500 8.32800

28 0.00000 0.10940 0.46230 1.10500 1.92900 2.90800 3.98900 4.99200 5.87000 6.62500 7.32000

30 0.00000 0.03928 0.22000 0.52070 0.93840 1.45200 1.93000 2.29700 2.58000 2.84500 3.09300

32 0.00000 -0.03928 -0.22000 -0.52070 -0.93840 -1.45200 -1.93000 -2.29700 -2.58000 -2.84500 -3.09300

34 0.00000 -0.10940 -0.46230 -1.10500 -1.92900 -2.90800 -3.98900 -4.99200 -5.87000 -6.62500 -7.32000

36 0.00000 -0.11910 -0.46780 -1.11000 -1.99300 -3.04100 -4.21900 -5.39400 -6.47300 -7.43500 -8.32800

38 0.00000 -0.08618 -0.40740 -1.04100 -1.96400 -3.10000 -4.41000 -5.82000 -7.23100 -8.57900 -9.86000

40 0.00000 -0.01385 -0.23870 -0.78180 -1.62600 -2.75200 -4.10200 -5.61500 -7.23700 -8.89900 -10.56000

42 0.00000 -0.08709 -0.41210 -1.06600 -2.05100 -3.33600 -4.88100 -6.61900 -8.48800 -10.44000 -12.45000

44 0.00000 -0.10010 -0.45060 -1.14900 -2.19300 -3.55200 -5.19600 -7.04500 -9.03000 -11.12000 -13.27000

46 0.00000 -0.05792 -0.35600 -1.00000 -1.98800 -3.30900 -4.91900 -6.74300 -8.73200 -10.83000 -13.00000

48 0.00000 -0.12260 -0.52820 -1.27800 -2.36600 -3.76800 -5.45400 -7.34900 -9.39800 -11.54000 -13.73000

50 0.00000 -0.12260 -0.52270 -1.25100 -2.29300 -3.63800 -5.25500 -7.07300 -9.03400 -11.08000 -13.16000

52 0.00000 -0.09736 -0.38110 -0.86270 -1.54300 -2.44900 -3.54700 -4.80800 -6.21700 -7.71200 -9.30100

54 0.00000 -0.01440 -0.07226 -0.22610 -0.47110 -0.76540 -1.12700 -1.56500 -2.08500 -2.69000 -3.37200

56 0.00000 -0.01330 -0.05761 -0.10840 -0.18600 -0.30410 -0.45740 -0.64440 -0.85890 -1.11600 -1.40700

58 0.00000 -0.00690 -0.02246 -0.07362 -0.13850 -0.21330 -0.32130 -0.44540 -0.58860 -0.75030 -0.91850

59 0.00000 -0.00361 -0.01787 -0.02812 -0.01801 -0.00308 -0.00343 -0.00334 -0.00264 -0.00551 -0.01451

60 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000


Table 6.3: Torque (contd..)Current(A) 11 12 13 14 15 16 17 18 19 20

theta

0 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000

2 0.04549 0.07810 0.11400 0.15260 0.19630 0.24820 0.30800 0.37420 0.44840 0.53060

4 1.10100 1.30600 1.51800 1.74800 1.99300 2.25600 2.54800 2.85800 3.16100 3.43300

6 1.72900 2.07600 2.45900 2.88200 3.34300 3.83600 4.35400 4.92100 5.56800 6.32600

8 4.12800 4.96300 5.87600 6.85000 7.89400 9.00800 10.19000 11.45000 12.71000 13.94000

10 10.97000 12.70000 14.49000 16.33000 18.21000 20.14000 22.10000 24.11000 26.21000 28.46000

12 15.25000 17.37000 19.50000 21.67000 23.86000 26.05000 28.25000 30.46000 32.64000 34.77000

14 15.93000 18.15000 20.36000 22.57000 24.76000 26.94000 29.12000 31.30000 33.48000 35.66000

16 15.21000 17.41000 19.60000 21.77000 23.89000 25.99000 28.04000 30.05000 31.98000 33.82000

18 15.45000 17.64000 19.81000 21.94000 24.03000 26.07000 28.04000 29.92000 31.70000 33.35000

20 14.47000 16.49000 18.48000 20.42000 22.30000 24.13000 25.90000 27.58000 29.21000 30.79000

22 12.22000 13.85000 15.46000 17.04000 18.58000 20.08000 21.53000 22.93000 24.27000 25.59000

24 11.11000 12.33000 13.54000 14.74000 15.94000 17.11000 18.26000 19.39000 20.47000 21.52000

26 9.18100 10.01000 10.82000 11.63000 12.44000 13.24000 14.03000 14.82000 15.57000 16.28000

28 7.98000 8.61700 9.24100 9.85000 10.45000 11.04000 11.64000 12.23000 12.80000 13.33000

30 3.30800 3.50600 3.69900 3.87800 4.03400 4.18800 4.34200 4.49500 4.68300 4.95200

32 -3.30800 -3.50600 -3.69900 -3.87800 -4.03400 -4.18800 -4.34200 -4.49500 -4.68300 -4.95200

34 -7.98000 -8.61700 -9.24100 -9.85000 -10.45000 -11.04000 -11.64000 -12.23000 -12.80000 -13.33000

36 -9.18100 -10.01000 -10.82000 -11.63000 -12.44000 -13.24000 -14.03000 -14.82000 -15.57000 -16.28000

38 -11.11000 -12.33000 -13.54000 -14.74000 -15.94000 -17.11000 -18.26000 -19.39000 -20.47000 -21.52000

40 -12.22000 -13.85000 -15.46000 -17.04000 -18.58000 -20.08000 -21.53000 -22.93000 -24.27000 -25.59000

42 -14.47000 -16.49000 -18.48000 -20.42000 -22.30000 -24.13000 -25.90000 -27.58000 -29.21000 -30.79000

44 -15.45000 -17.64000 -19.81000 -21.94000 -24.03000 -26.07000 -28.04000 -29.92000 -31.70000 -33.35000

46 -15.21000 -17.41000 -19.60000 -21.77000 -23.89000 -25.99000 -28.04000 -30.05000 -31.98000 -33.82000

48 -15.93000 -18.15000 -20.36000 -22.57000 -24.76000 -26.94000 -29.12000 -31.30000 -33.48000 -35.66000

50 -15.25000 -17.37000 -19.50000 -21.67000 -23.86000 -26.05000 -28.25000 -30.46000 -32.64000 -34.77000

52 -10.97000 -12.70000 -14.49000 -16.33000 -18.21000 -20.14000 -22.10000 -24.11000 -26.21000 -28.46000

54 -4.12800 -4.96300 -5.87600 -6.85000 -7.89400 -9.00800 -10.19000 -11.45000 -12.71000 -13.94000

56 -1.72900 -2.07600 -2.45900 -2.88200 -3.34300 -3.83600 -4.35400 -4.92100 -5.56800 -6.32600

58 -1.10100 -1.30600 -1.51800 -1.74800 -1.99300 -2.25600 -2.54800 -2.85800 -3.16100 -3.43300

59 -0.04549 -0.07810 -0.11400 -0.15260 -0.19630 -0.24820 -0.30800 -0.37420 -0.44840 -0.53060

60 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000

6.6 Position Sensor 91

6.6 Position Sensor

Figure 6.5: (a) Inductance Profiles of the Four Stator Phases

Figure 6.5: (b) Position Signals for Forward Rotation

Figure 6.5: (c) Position Signals for Reverse Rotation

For an SR motor drive, switching on and switching off the phases are syn-chronised with the rotor position. The test motor is provided with four dis-crete sensors. The position signals made available from the position sensors.In real-time simulation, these position signals are generated continuously in


the simulation itself and are given in Fig. 6.5. In this figure, the idealisedinductance profiles of the four phases are also given.

6.7 Control Strategy

The traditional control method employs two regimes of control namely lowspeed chopping control, and high speed angle control. This angle controlmode has been referred to as single pulse mode by many authors. For an 8/6pole SR motor, each phase gets excited periodically at 60 interval. The phasedifference between successive phases will be 15 each. The control is definedin all the four quadrants of operation of the motor. These are

1. FSFT: Forward Speed Forward Torque

2. FSRT: Forward Speed Reverse Torque

3. RSFT: Reverse Speed Forward Torque

4. RSRT: Reverse Speed Reverse Torque

Again, in each quadrant, the control is divided in three speed ranges namely,

1. Starting speed((Less than 100 rpm in either direction)

2. Medium speed (Between 100 and 750 rpm in either direction)

3. High speed (Above 750 rpm in either direction).

Table 6.4 gives the digital raw enabling signals (produced from P, Q, R,S) for each phase under different operating conditions stated above. It maybe verified from the position signals that the right polarity of torque will begenerated if the different phases are excited in the enabling periods given inTable 6.4. The raw enable signals are further mixed with other appropreiatesignals for driving the switches in the four phases of the machine. These areexplained in the following sections.

Phase Starting Speed Low Speed High Speed

Forward Reverse Forward Reverse Forward Reverse

A P P PS PR S R

B Q Q QR QS R S

C P P PS PR S R

D Q Q QR QS R S

Table 6.4: Switch Control Signals

6.7 Control Strategy 93

Starting Speed Current Controlled Operation:

In the starting speed ranges, the individual phases are turned on/off in theraw enable duration and phase current is maintained at the desired current, I∗

by chopping control. I∗ is made a function of the desired torque. The controlstrategy is illustrated in Fig. 6.6. In the starting operation (or very low speedof operation), the raw enable signal is ended with the logic signal (I ≤ I∗ ).The switch control signal for the different phases are given below.

SA = P (I ≤ I∗)(T > 0) + P (I ≤ I∗)(T < 0)SB = Q(I ≤ I∗)(T > 0) +Q(I ≤ I∗)(T < 0)SC = P (I ≤ I∗)(T > 0) + P (I ≤ I∗)(T < 0)SD = Q(I ≤ I∗)(T > 0) +Q(I ≤ I∗)(T < 0)

Low Speed Current Controlled Operation:

In the low speed of operation ( speed upto 750 rpm), current control is used.The switch enable signals are given by the equations below. In both the start-ing region of operation and low speed of operation the phase current feedbackis also required to implement the switch control.

SA = PS(I ≤ I∗)(T > 0) + PR(I ≤ I∗)(T < 0)SB = QR(I ≤ I∗)(T > 0) +QS(I ≤ I∗)(T < 0)SC = PS(I ≤ I∗)(T > 0) + PR(I ≤ I∗)(T < 0)SD = QR(I ≤ I∗)(T > 0) +QS(I ≤ I∗)(T < 0)

High Speed Single Pulsed operation: In the high speed range, back-emfis considerable and it exceeds the supply voltage. Phase currents no longercan be controlled by chopping method. The individual phases are controlledwith two parameters defined as T-on and T-off. These turn-on time, T-on andturn-off time, T-off are illustrated in Fig. 6.7. The raw enable signal for thismode (shown in Table 6.4) is mixed with a controlled T-on and controlled T-off angles. Hence control of torque in this region is realised by controlling thedwell angle. Normally the T-on angle is defined as a function of shaft speedand demanded torque, whereas T-off angle is defined as a function of speedonly. At any particular speed, the desired average torque may be obtained bymore than one combination of these angles. Among these, the combinationswhich give minimum torque ripple and minimum peak current are desired.Generally, exhaustive search method is employed in simulation to calculatethe optimum value of these parameters. These are stored in a look up table asa function of load torque and speed and referred by the controller as desired.

The angle θ1 is a function of shaft speed as well as the desired torque. Theangle θ2 is a function of the shaft speed. The per unit shaft speed may varyin the range of 0.5 to 1 in either direction. The desired per unit torque mayvary in the range of -1 to +1. For the controller the values of θ1 and θ2 arestored in a look-up Table 6.5, 6.6 and referred to as desired.

94

Real-T

ime

Sim

ula

tion

OfSw

itched

Relu

cta

nce

Moto

r

Table 6.5: θ1Torque -1.00 -0.90 -0.80 -0.70 -0.60 -0.50 -0.40 -0.30 -0.20 -0.10 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00

Speed

-1.00 55.4 54.7 53.85 53.05 52.1 51 49.85 48.5 46.6 44 41 38.9 41.5 43.2 44.7 45.7 46.7 47.6 48.5 49.1 49.8

-0.90 53.65 53.05 52.3 51.5 50.7 49.8 48.75 47.5 45.9 43.5 40.5 38.4 40.8 42.4 43.6 44.6 45.5 46.3 47 47.8 48.4

-0.80 51.8 51.3 50.7 50.05 49.3 48.5 47.55 46.5 45 42.7 40 38 40 41.5 42.6 43.55 44.4 45.1 45.7 46.35 46.9

-0.70 50.05 49.6 49.1 48.5 47.9 47.2 46.4 45.4 44.05 42 39.5 37.6 39.5 40.9 41.9 42.7 43.5 44.05 44.55 45 45.6

-0.60 48.25 47.9 47.45 47 46.45 45.8 45.1 44.25 43.1 41.25 39 37.2 39 40.1 41 41.7 42.3 42.85 43.3 43.8 44.2

-0.51 46.4 46.05 45.7 45.3 44.9 44.4 43.8 43 42 40.4 38 36.5 38.2 39.2 39.9 40.4 40.9 41.4 41.9 42.2 42.5

0.51 17.5 17.8 18.1 18.6 19.1 19.6 20.1 20.8 21.8 23.5 21.5 19.6 18 17 16.2 15.6 15.1 14.7 14.3 13.95 13.6

0.60 15.8 16.2 16.7 17.15 17.7 18.3 19 19.9 21 22.8 20.8 18.85 16.9 15.75 14.9 14.2 13.55 13 12.55 12.1 11.75

0.70 14.4 15 15.45 15.95 16.5 17.3 18.1 19.1 20.5 22.4 20.2 18 15.95 14.6 13.6 12.8 12.1 11.5 10.9 10.4 9.95

0.80 13.1 13.65 14.3 14.9 15.6 16.45 17.4 18.5 20 22 19.6 17.3 15 13.5 12.45 11.5 10.7 9.95 9.3 8.7 8.2

0.90 11.6 12.2 13 13.7 14.5 15.4 16.4 17.6 19.2 21.6 19 16.5 14.1 12.5 11.25 10.2 9.3 8.5 7.7 6.95 6.35

1.00 10.2 10.9 11.5 12.4 13.3 14.3 15.3 16.8 18.5 21.1 18.5 16 13.4 11.5 10.15 9 7.9 6.95 6.15 5.3 4.7

Table 6.6: θ2Torque -1.00 -0.90 -0.80 -0.70 -0.60 -0.50 -0.40 -0.30 -0.20 -0.10 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00

Speed

-1.00 30 30 30 30 30 30 30 30 30 30 41 26.9 26.9 26.9 26.9 26.9 26.9 26.9 26.9 26.9 26.9

-0.90 30.50 30.50 30.50 30.50 30.50 30.50 30.50 30.50 30.50 30.50 40.50 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00 27.00

-0.80 30.80 30.80 30.80 30.80 30.80 30.80 30.80 30.80 30.80 30.80 40.00 27.20 27.20 27.20 27.20 27.20 27.20 27.20 27.20 27.20 27.20

-0.70 31.20 31.20 31.20 31.20 31.20 31.20 31.20 31.20 31.20 31.20 39.50 27.50 27.50 27.50 27.50 27.50 27.50 27.50 27.50 27.50 27.50

-0.60 31.50 31.50 31.50 31.50 31.50 31.50 31.50 31.50 31.50 31.50 39.00 27.80 27.80 27.80 27.80 27.80 27.80 27.80 27.80 27.80 27.80

-0.51 31.80 31.80 31.80 31.80 31.80 31.80 31.80 31.80 31.80 31.80 38.00 28.00 28.00 28.00 28.00 28.00 28.00 28.00 28.00 28.00 28.00

0.51 32.00 32.00 32.00 32.00 32.00 32.00 32.00 32.00 32.00 32.00 21.50 28.20 28.20 28.20 28.20 28.20 28.20 28.20 28.20 28.20 28.20

0.60 32.20 32.20 32.20 32.20 32.20 32.20 32.20 32.20 32.20 32.20 20.80 28.50 28.50 28.50 28.50 28.50 28.50 28.50 28.50 28.50 28.50

0.70 32.50 32.50 32.50 32.50 32.50 32.50 32.50 32.50 32.50 32.50 20.20 28.80 28.80 28.80 28.80 28.80 28.80 28.80 28.80 28.80 28.80

0.80 32.80 32.80 32.80 32.80 32.80 32.80 32.80 32.80 32.80 32.80 19.60 29.20 29.20 29.20 29.20 29.20 29.20 29.20 29.20 29.20 29.20

0.90 33.00 33.00 33.00 33.00 33.00 33.00 33.00 33.00 33.00 33.00 19.00 29.50 29.50 29.50 29.50 29.50 29.50 29.50 29.50 29.50 29.50

1.00 33.10 33.10 33.10 33.10 33.10 33.10 33.10 33.10 33.10 33.10 18.50 30.00 30.00 30.00 30.00 30.00 30.00 30.00 30.00 30.00 30.00


Figure 6.6: Low Speed Control Strategy

Figure 6.7: Control Strategy at High Speed

6.8 Implementation

A. Parameters : The details of the switched reluctance motor is presentedin Table. 6.7.

B. Base Values for Different Quantities : The Table. 6.8 shows the basevalues for voltage (chosen as per phase rated voltage of SR Motor), current(chosen rated current) and frequency (chosen as rated frequency). Theother bases are calculated from the above mentioned base quantities.

C. PU System Followed : The Table 6.9 shows the digital equivalent for thepu values. The signed arithmetic, the digital equivalent for a negativepu value is chosen as the 1’s compliment of its corresponding positive puvalue.


VOLTAGE 280 V

CURRENT 18 A

POWER 4kW

POLES (P) 8/6

SPEED 1500 rpm

Resistance O.2Ω

Table 6.7: Details of the Switched Reluctance Motor

Voltage (Vb) 280V

Current (Ib) 18A

Speed (Nb) 1500rpm

Frequency in rad/sec (ωb) 2π ∗ Nb

60 ∗Nr = 942.48rad/sec

Resistance(Rb)Vb

Ib

= 15.556Ω

Mechanical Speed(ωmb) 2π ∗ Nb

60 = 157.08rad/sec

Flux Linkages(ψb)Vb

ωmb

= 0.29771

Torque(Mb)Vb∗Ib

ωmb

= 32.086N −m

K1(b)Ib

ψb

= 32.086N −m

K2(b)Ib

ψ2b

= 32.086N −m

K3(b)Ib

ψ3b

= 32.086N −m

Table 6.8: Base Values


1 pu 3FFFH 16383d

0 pu 000H 0d

-1 pu(16-bit) C000H 49152d


6.9 Normalized Equations 97

6.9 Normalized Equations

In this section, all the equations are perunitized and are made ready for imple-mentation. The sampling time for the implementation is chosen as 25.6 µsec.The eqn. 6.1 is repeated here.

v = Ri+dψ

dt(6.13)

Dividing the above equation by Vb

v(pu) = R(pu)i(pu) +ψb

Vb

dψ(pu)

dt(6.14)

Using the Eulers Method of integration, the equation in digital domain can bewritten as

ψ (n) = ψ (n− 1) +(v (n− 1) − R(pu)i (n− 1)

)Ts ωb

Note that, the sampling time Ts for the implementation is chosen as 25.6 µsec.

ψ (n) = ψ (n− 1) +(v (n− 1) − 0.0129(pu)i (n− 1)

)∗ 0.004pu (6.15)

The flux linkage charcteristic equation is given by 6.12 and the correspondingnormalized equation is as follows:

i (n) = K1(pu) ψ (n) + (ψ (n) > ψ1(pu)) K2(pu) (ψ (n) − ψ1(pu))2

+ (ψ (n) > ψ2(pu)) K3(pu) (ψ (n) − ψ2(pu))3

(6.16)

Once, the value of current and position of a particular phase is known, theinstantaneous torque due to that particular phase can be found using thestored static torque data table 6.2, 6.3. In the similiar process, the torque dueto other conducting phases also may be found. the summation of all the phasetorques at any instant gives the instantaneous torque of the motor.


FPGA Design files of Switched Reluctance Motor are placed in ‘fpga pro-gram files’ folder. Similarly simulink files are in ‘simulinkprogramfiles’ folder.Fig. 6.8 to Fig. 6.12 are the FPGA design files to generate enable signalsexplained in section 6.7.

6.11 Waveforms

The program developed for switched reluctance motor in Quartus II toolare downloaded into FPGA by using Byte-blaster cable. The waveforms arerecorded and are compared with the off-line simulation waveforms.


Figure 6.8: FPGA Design File for Speed to Position Conversion

6.11 Waveforms 99

Figure 6.9: FPGA Design File for Sector Selection


Figure 6.10: FPGA Design File for Generation of Position Signals

6.11 Waveforms 101

Figure 6.11: (a) FPGA Design File for Generation of Enable Signals


Figure 6.12: (b) FPGA Design File for Generation of Enable Signals

6.11 Waveforms 103

0.74 0.742 0.744 0.746 0.748 0.75 0.752 0.754 0.756 0.758 0.760

0.5

1

1.5

0.74 0.742 0.744 0.746 0.748 0.75 0.752 0.754 0.756 0.758 0.760

0.5

1

1.5

0.74 0.742 0.744 0.746 0.748 0.75 0.752 0.754 0.756 0.758 0.760

0.5

1

1.5

time

Nm

Amp

Enab

le

sign

al

Figure 6.13: (i) Enable Signal, (ii) Phase Current, (iii) Average Torque[Scale: y-axis: 1 per unit = 5V , ωref = 1500 rpm (1 PU) and Mref =

32.1Nm (1 PU)]

1.065 1.07 1.075 1.08 1.085 1.09 1.095 1.1 1.1050

0.5

1

1.5

1.065 1.07 1.075 1.08 1.085 1.09 1.095 1.1 1.1050

0.5

1

1.5

1.065 1.07 1.075 1.08 1.085 1.09 1.095 1.1 1.1050

0.5

1

1.5

time

Nm

Amp

Enab

le

sign

al

Figure 6.14: (i) Enable Signal, (ii) Phase Current, (iii) Average Torque[Scale: y-axis: 1 per unit = 5V , ωref = 600 rpm (0.4 PU) and Mref =

32.1Nm (1 PU)]

1.65 1.7 1.750

0.5

1

1.5

1.65 1.7 1.750

0.5

1

1.5

1.65 1.7 1.750

0.5

1

1.5

time

Nm

Amp

Enab

le

sign

al

Figure 6.15: (i) Enable Signal, (ii) Phase Current, (iii) Average Torque[Scale: y-axis: 1 per unit = 5V , ωref = 90 rpm (0.06 PU) and Mref =

32.1Nm (1 PU)]


0.645 0.65 0.655 0.66 0.665 0.670

0.5

1

1.5

0.645 0.65 0.655 0.66 0.665 0.670

0.5

1

1.5

0.645 0.65 0.655 0.66 0.665 0.670

0.5

1

1.5

Enab

le

sign

al

Amp

Nm

time

Figure 6.16: (i) Enable Signal, (ii) Phase Current, (iii) Average Torque[Scale: y-axis: 1 per unit = 5V , ωref = -1500 rpm (-1 PU) and Mref =

32.1Nm (1 PU)]

0.88 0.882 0.884 0.886 0.888 0.89 0.892 0.894 0.896 0.898 0.90

0.5

1

1.5

0.88 0.882 0.884 0.886 0.888 0.89 0.892 0.894 0.896 0.898 0.90

0.5

1

1.5

0.88 0.882 0.884 0.886 0.888 0.89 0.892 0.894 0.896 0.898 0.9−1.5

−1

−0.5

0

time

Nm

Amp

Enab

le

sign

al

Figure 6.17: (i) Enable Signal, (ii) Phase Current, (iii) Average Torque[Scale: y-axis: 1 per unit = 5V , ωref = -1500 rpm (-1 PU) and Mref =

-32.1Nm (-1 PU)]

1.395 1.4 1.405 1.41 1.4150

0.5

1

1.5

1.395 1.4 1.405 1.41 1.4150

0.5

1

1.5

1.395 1.4 1.405 1.41 1.415−1.5

−1

−0.5

0

time

Nm

Amp

Enab

le

sign

al

Figure 6.18: (i) Enable Signal, (ii) Phase Current, (iii) Average Torque[Scale: y-axis: 1 per unit = 5V , ωref = 1500 rpm (1 PU) and Mref =

-32.1Nm (-1 PU)]

6.11 Waveforms 105

1.845 1.85 1.855 1.86 1.8650

0.5

1

1.5

1.845 1.85 1.855 1.86 1.8650

0.2

0.4

0.6

0.8

1.845 1.85 1.855 1.86 1.8650

0.2

0.4

0.6

0.8

time

Nm

Amp

Enab

le

sign

al

Figure 6.19: (i) Enable Signal, (ii) Phase Current, (iii) Average Torque[Scale: y-axis: 1 per unit = 5V , ωref = 1500 rpm (1 PU) and Mref = 16Nm

(0.5 PU)]


6.12 Conclusion

The principle of switched reluctance motor has been explained. It was im-plemented in FPGA based controller. Both Real-time and offline simulationresults are presented.

Chapter 7

Control and Real-TimeSimulation of Matrix Converters

7.1 Introduction

Matrix Converters are direct AC-AC power converters without a DC link ca-pacitor. Matrix Converters are now receiving considerable research attentiondue to a number of advantageous features. In a Matrix Converter, outputvoltages of desired frequency and amplitude (subjected to certain constraints)are directly synthesized from the input voltages. Matrix Converters can be de-signed to be more compact than the conventional AC-AC converters. In thischapter the implementation of modulators for Matrix Converters is discussed.The converters are also modelled in the FPGA and a real-time simulationof the same is given. Results are given for the direct on-line starting of anInduction Motor fed from the Matrix Converter.

The FPGA platform is capable of implementing complex converter con-trols. It is possible to simulate the entire drive system consisting of controller,converter and the machine in real-time.


The Matrix Converter is realized by a matrix arrangement of four-quadrant(bidirectional voltage-blocking, current-conducting) switches. Fig. 7.1 showsthe topology of a three-phase to three-phase Matrix Converter. Each inputphase is connected to all the output phases by bidirectional switches. Anyinput phase can be connected to any output phase, by turning on the cor-responding switch. The basic principle of the Matrix Converter is that byproperly switching the devices a desired set of output voltages can be synthe-sized from the set of input voltages. However there are certain constraints inthe power conversion. The input is typically a voltage source and the output isnormally connected to an inductive load. Simultaneous closing of more than

108 Control and Real-Time Simulation of Matrix Converters

SAu

BuS

SAv SAw

SBwSBu

SCv SCwSCu

A

B

C

vu w

Figure 7.1: Matrix Converter Topology

one switch connected to any output phase (u,v or w) will short circuit therespective input phases. Also, if at-least one switch connected to each outputphase is not ON, the current path will be broken. This will cause overvolt-ages to appear across the devices. The basic constraints for a three-phase tothree-phase Matrix Converter can be stated as follows:

SAu + SBu + SCu = 1 (7.1)

SAv + SBv + SCv = 1 (7.2)

SAw + SBw + SCw = 1 (7.3)

where, Sij = 1 or 0, representing the state of switch connecting the in-put phase i to output phase j. Due to the switching delays in the devices,commutation schemes are needed to avoid the violation of these constraints.Four-quadrant switches can be made with anti-series or anti-parallel connec-tion of IGBTs or MOSFETs.

7.3 Direct and Indirect Matrix Converters 109

7.3 Direct and Indirect Matrix Converters

Matrix Converters are realized in two basic topologies. The classical MatrixConverter is known as Direct Matrix Converter, due to the direct AC-ACconversion without any explicit DC link. However there is an alternate topol-ogy in which the Matrix Converter is realized as a cascade connection of twoconverters. This topology is known as Indirect Matrix Converter. Both arefunctionally the same.

7.3.1 Direct Matrix Conversion

The converter principle can be explained with a 3-phase to 3-phase converterexample. This clearly shows the switching constraints. There are 9 bidirec-tional switches which connect the input phases a,b,c to the output phasesu,v,w. The switch states can be represented as,Sij = 1 or 0 where, i = a, b, c & j = u, v, wFor example, when switch Sav is ON, input phase a is connected to out-put phase v. The instantaneous output voltages depend on the states of theswitches. Hence the output voltages can be expressed in terms of the inputvoltages and the switch states as follows:

vu(t)

vv(t)

vw(t)

=

Sau Sbu Scu

Sav Sbv Scv

Saw Sbw Scw

va(t)

vb(t)

vc(t)

(7.4)

For obtaining a desired low frequency averaged waveform, the switches aremodulated at a switching frequency much higher than both the input andoutput frequencies. The averaged output voltages can then be representedin terms of the individual switch duty ratios instead of the switch states inEqn. 7.4. The output voltages are represented as follows:

vu(t)

vv(t)

vw(t)

=

dau dbu dcu

dav dbv dcv

daw dbw dcw

va(t)

vb(t)

vc(t)

(7.5)

Or,vuvw = M(t) × vabc (7.6)

where, M(t) is the modulation (duty ratio) matrix in Eqn. 7.5The duty ratios are determined based on the desired amplitude and fre-

quency of the output voltages. There are several modulation methods to


achieve this. Modulation of the converter is described in section 7.4. Theinput currents are related to the output currents by the transpose relationgiven as;

iabc = MT (t) × iuvw (7.7)

7.3.2 Indirect Matrix Conversion

In the Indirect Matrix Converter, the AC-AC conversion is done in two stages.The input converter is a current source type rectifier. This converter usesbidirectional switches as in the case of Direct Matrix Converter. The switch-count can be reduced if regeneration is not needed. A number of new topologiesin this direction have been reported. The output converter is a voltage sourceinverter. Here the switches used are IGBTs with anti-parallel diodes. TheDC link does not have a capacitor. The control can be separated between thetwo converters. The modulation of the Converters is done in an independentmanner. Fig. 7.2 shows the topology. The conversion involves two stages. In

Sv

Sw

531

4 6 2

b

c

a u

v

w

Sup

n

idc

dcvn

vpn

vnn

uS

Sv

Sw

Figure 7.2: Indirect Matrix Converter Topology

the first stage, the input converter is modulated to get a dc link voltage. In thesecond stage, the output converter is modulated to get the AC output fromthe dc link voltage. Both the modulations are independently done. There is anexplicit DC link present in this topology. All modulation schemes applicableto VSI can be used here. Input converter is the dual topology of VSI. The DClink voltage produced by the input converter can be expressed as:

VDC(t) = vpn(t) − vnn(t) (7.8)

where vpn(t) and vnn(t) are the upper and lower pole voltages with respect tothe supply neutral. The pole voltages can be represented in terms of the input

7.3 Direct and Indirect Matrix Converters 111

voltages in a compact form as follows.

vpn(t)

vnn(t)

=

S1 S3 S5

S4 S6 S2

va(t)

vb(t)

vc(t)

(7.9)

The above expression gives the instantaneous voltages as the switch stateschange. The currents can also be represented in a similar manner.

The output voltages are obtained by the switching action of the outputconverter. The relation between the DC link voltages vpn(t) & vnn(t) and theoutput voltages u, v, w can be shown to be:

vu(t)

vv(t)

vw(t)

=

Su Su

Sv Sv

Sw Sw

vpn(t)

vnn(t)

(7.10)

Comparing the direct and indirect conversion, it is clear (Eqns. 7.4, 7.9 and7.10) that both are related.

vu(t)

vv(t)

vw(t)

=

Sau Sbu Scu

Sav Sbv Scv

Saw Sbw Scw

va(t)

vb(t)

vc(t)

=

Su Su

Sv Sv

Sw Sw

S1 S3 S5

S4 S6 S2

va(t)

vb(t)

vc(t)

(7.11)

vuvw = I × R× vabc (7.12)

Where I is the Inversion Matrix, and R is the Rectifier Matrix.

Here, the input rectifier stage produces the DC link voltage from the inputvoltages and at the same time modulates the DC link current in to sinusoidalinput currents. The DC link is a ‘virtual’ one in case of Direct Matrix Con-verter.


7.4 Modulation of Matrix Converters

Modulation of the Matrix Converter can be done in several ways. There areclassical methods like the Venturini method [9] and modern control techniquessuch as Space Vector Modulation [8]. Space vector Modulation method isdescribed here. There is an inherent limitation to the voltage conversion ratioin the Matrix converter in the linear modulation range. With space phasormodulation the maximum amplitude of the output line voltages that we cansynthesize is limited to 0.866 times the input line peak [9].

7.4.1 Indirect Converter Modulation

Indirect Converter is a cascade connection of rectifier and inverter. Here,modulation can be done independently. The input converter is modulatedbased on the Current Space Vector and output converter is modulated basedon Voltage Space Vector.

Input Converter Modulation

In the input converter, there are 6 bidirectional switches. Fig. 7.3 shows thecurrent phasors obtained for each switching combination. For each sector oneswitch is held ON during the sector, while the return phases are modulated.For example, in sector 1, the switch S1 is kept ON, while switches S6 and S2 aremodulated. If the two switches connected to the same phase are closed, thereis no current in that particular phase. Such switch combinations are the zerostates of the converter. The switch states S1S4, S3S6, and S5S2 are the 3 zerostates in this converter. The modulation index is kept at 1. For achieving a

2, 3

3, 4

4, 5

5, 6

6, 1

1, 2III II

IV

V VI

I

vdc

b

c

a

n

p

513

4 6 2

dci

Figure 7.3: Input Converter and the Current Space Phasors

unity input power factor, the reference current space phasor should be in phasewith the input voltage phasor. In each sector, one switch is kept ON, and the

7.4 Modulation of Matrix Converters 113

other two are modulated. The duty ratio of each combination of switch-statescan be calculated from Fig. 7.4. These are given in Eqn. 7.13. The α and βdirections show the active vectors, which arise from the switch combinations.In sector 1 (Fig.7.4), the switch combination S1S6 and S1S2 corresponds tothe active vectors in α and β directions respectively. The switch combinationS1S4 corresponds to the zero vector.

iα

iβ

CSCθ

6 I 2 3 4 5 6

0

a b c

S1 S6

S1 S2

i(t)

Figure 7.4: Sector Definition

dα = sin(π

3− θCSC

)

dβ = sin (θCSC)

d0 = 1 − dα − dβ (7.13)

Here, the modulation index is assumed to be 1.

Sequencing the active and zero states can be done in several ways consid-ering number of switchings in one switching cycle. The general approach is toget the raw switching signals first. These indicate the time duration for eachactive or zero vector. Then the sector information is used to produce the actualswitch control signals from the raw switching signals. Once the sequencing ofactive vector durations is determined, the modulation can be implemented bya carrier based approach. A ramp or triangular carrier is compared againstthe modulating functions to get the raw switch signals. Fig. 7.5 shows the gen-eration of raw switch signals. Eqns. 7.14- 7.17 give the modulating functions.Note that, the modulating function for odd sectors is m1 and for even sectorsis m3. In the figure, Ts is the sequence period. The switching frequency is 1

2Ts.

It is also possible to have a ramp based sequencing in which the zero statesare not divided into two in one sequence period.


T0TαTβTβTαT0T0

m0

m1 m3/

m2

S0

Sβ

Sα

Ts2

Carrier1

2

Figure 7.5: Modulation Functions and Raw Switch Signals

m0 =1 − dα − dβ

2= (0.5 − 0.5mSin(60o − θCSC) − 0.5mSin(θCSC)) (7.14)

m1 = (m0 + dα)

= (0.5 + 0.5mSin(60o − θCSC) − 0.5mSin(θCSC)) (7.15)

m2 = (m1 + dβ)

= (0.5 + 0.5mSin(60o − θCSC) + 0.5mSin(θCSC)) (7.16)

m3 = m0 + dβ

= (0.5 − 0.5mSin(60o − θCSC) + 0.5mSin(θCSC)) (7.17)

where m is the modulation index. From Figs. 7.3 and 7.5 we can obtainthe relation between the raw switch signals and the actual switch controlsignals.(See Table 7.1). The actual switch control signals derived from Table7.1 are given in Eqns. 7.18.


Table 7.1: Switch Signals

Sector Sr.1 Sr.2 Sr.3 Sr.4 Sr.5 Sr.6

S0 S1S4 S2S5 S3S6 S4S1 S5S2 S6S3

Sα S1S6 S2S3 S3S2 S4S5 S5S4 S6S1

Sβ S1S2 S2S1 S3S4 S4S3 S5S6 S6S5

S1 = Sr.1 + S0.Sr.4 + Sα.Sr.6 + Sβ.Sr.2

S2 = Sr.2 + S0.Sr.5 + Sα.Sr.3 + Sβ.Sr.1

S3 = Sr.3 + S0.Sr.6 + Sα.Sr.2 + Sβ.Sr.4

S4 = Sr.4 + S0.Sr.1 + Sα.Sr.5 + Sβ.Sr.3

S5 = Sr.5 + S0.Sr.2 + Sα.Sr.4 + Sβ.Sr.6

S6 = Sr.6 + S0.Sr.3 + Sα.Sr.1 + Sβ.Sr.5 (7.18)

Output Converter Modulation

Output converter is a normal Voltage Source Inverter (VSI). Hence the famil-iar modulation schemes can be applied to get the required output waveforms.Here, the conventional space vector PWM scheme is explained. The modula-tion functions for the conventional space vector PWM are the same as thosedescribed for input modulation. The VSI configuration and the voltage spacephasors that are derived from the switch states are shown in Fig. 7.6. Theduty ratios are given in Eqn. 7.19- 7.21.

1

0 a b c

VSI

Vdc

Sector 1

θVSI

000111

V

a

β

Vα

V

c

b

100

101001

110

011

010

*

Figure 7.6: VSI and Space vectors


dα = m× sin(π

3− θV SI

)

(7.19)

dβ = m× sin (θV SI) (7.20)

d0 = 1 − dα − dβ (7.21)

where m is the modulation index. For a doublesided modulation the modu-lation functions are defined similar to the input converters (Eqns. 7.14 - 7.17).The generation of raw switching signals and the switch control signals are donein a similar manner. Fig. 7.7 shows how this is done for the sector 1. Theswitch signals are generated by a logic combination of the sector informationand raw signals S0, Sα and Sβ (Eqns. 7.22).

T0TαTβTβTαT0T0

m0

m1 m3/

m2

S0

Sβ

Sα

Ts2

Carrier1

2

000100110111110100000

Sw

Sv

Su

Figure 7.7: Switch Signal Generation for VSI : Sector 1


Su = S0 + Sα (Sr.1 + Sr.6) + Sβ (Sr.1 + Sr.2 + Sr.5 + Sr.6)

Sv = S0 + Sα (Sr.2 + Sr.3) + Sβ (Sr.1 + Sr.2 + Sr.3 + Sr.4)

Sw = S0 + Sα (Sr.4 + Sr.5) + Sβ (Sr.3 + Sr.4 + Sr.5 + Sr.6) (7.22)

7.4.2 Direct Converter Modulation

Direct Converter Modulation can be achieved in a simple method, derivedfrom the Indirect Converter Control. First, modulation is carried out as ifthe converter is an indirect one. The switch control signals for the DirectConverter are then derived based on the relation between the two (Eqn. 7.11).This simpler approach is known as Indirect Modulation. The switch controlsignals for direct matrix converter from that of Indirect Converter are:

Sau = S1.Su + S4.Su

Sav = S1.Sv + S4.Sv

Saw = S1.Sw + S4.Sw

Sbu = S3.Su + S4.Su

Sbv = S3.Sv + S4.Sv

Sbw = S3.Sw + S4.Sw

Scu = S5.Su + S4.Su

Scv = S5.Sv + S4.Sv

Scw = S5.Sw + S4.Sw (7.23)

These can be realized with a logic circuit.


7.5 Implementation of Modulators in FPGA

The modulation methods described in the previous sections are implementedin the FPGA controller board. The modulator equations are implemented indigital circuits form. Fig. 7.8 shows the outline of implementation of the inputmodulator using a block diagram approach using the Quartus II software. Forimplementing the circuit, the structure shown in Fig. 7.9 is used. Fig. 7.10shows the implementation of the output modulator. Both the modulators aresimilar except in the generation of PWM signals and sector defintion. Here,details are given for the output modulator. The input modulator can beimplemented in a similar manner, following the description in the previoussection.

Figure 7.8: Input Modulator Implementation in FPGA

A fixed point scaling is used to represent the different variables in the FPGAprogram. For example, 1 p.u is represented by a 14 bit number 3FFF . Dutyratios and angles follow this p.u system. For calculating the duty ratios thesine table is stored in a ROM in the FPGA.

7.5 Implementation of Modulators in FPGA 119

d0

dα

dβ

ModulationFunctions

m1

m2

m0

Ratio CalcDuty

PWM

Ref. Inputs

CarrierGen./TimingSync. Circuit

Mod.IndexClock

Ref. phase

Ref. input signals

Identification

Sector

Carrier

Angle Gen.

Figure 7.9: Structure of Input Modulator

Figure 7.10: Output Modulator Implementation in FPGA

7.5.1 Output Modulator

The major building blocks for the modulator are:

• Angle Generation

• Sector Identification

• Carrier Generation

• Modulation Functions Generation


• PWM generation

Sector Identification and Reference Angle Generation

The angle θ, is generated from the reference output frequency by integratingit. The procedure is same as described in Ch. 5. Based on the angle, the sectorcan be identified. The reference angle for space vector, θV SI is generated fromthe sector information and A logic circuit for this purpose is designed basedon Fig. 7.11.

60o

Sect 1

Sect 2

Sect 3

Sect 4

θ vsi

Sect 5

Sect 6

1 p.u/

p.u.

ang

le

2000h1555h

AAAh

2AAAh3554h

3FFFh

360o

Figure 7.11: Reference angle Generation

Carrier Generation

A triangular carrier is required for the calculation of different dwell times (orthe ’raw switch signals’). This can be generated as described in Ch. 5.

7.5 Implementation of Modulators in FPGA 121

Generation of Modulation Functions and PWM

Generation of the modulation functions as described in Eqns. 7.17 are imple-mented by the per-unitized digital equations. The duty ratios dα, dβ and d0

are calculated first from Sine table. Figures 7.12 and 7.13 show how the dutyratios and modulating functions are generated. They are just digital equiva-lents of the equations presented in the previous sections. Modulation functionsthus generated are compared against the carrier as shown in Fig. 7.7 and theraw functions S0, Sα and Sβ are generated. Fig. 7.14 shows the duty ratios

Figure 7.12: Calculation of Duty Ratios

dα and dbeta produced by the output modulator. Generation of PWM signalsSu, Sv and Sw is by implementing the simple logic equation given in Eqn. 7.22with AND, OR gates. Note that this requires the sector information.

Fig. 7.15 shows the generated PWM signals for switches S1 and S2 in theinput converter. Fig. 7.16 shows the PWM signals for switches Su and Sv.The switching frequency is 5 kHz. Fig. 7.17 shows the switch control signalsfor switch Sau and Sbu of the Direct Matrix Converter.


Figure 7.13: Calculation of Modulating Functions

Figure 7.14: Duty Ratios dα and dβ

7.6 Modelling of Direct and Indirect Matrix Converters

For a functional simulation, an idealized model can be derived from the Con-verter equations. In this section idealized models of both Direct and IndirectConverters are presented. Offline and real-time simulation can be done basedon these models. Since the Converters doesnot contain any energy storageelements, the equations are simple algebraic equations.

7.6 Modelling of Direct and Indirect Matrix Converters 123

Figure 7.15: PWM signals for S1 and S2 of Input Converter

Figure 7.16: PWM signals for Su and Sv of Output Converter


Figure 7.17: PWM signals for Sau and Sbu of Direct Converter

7.6.1 Indirect Converter

The input converter model is given in Eqn. 7.24. Fig. 7.18 shows the DC linkvoltage produced by the input converter. Structure of the output convertermodulator is shown in Fig. 7.19. The output converter model is based onEqn. 7.25.

VDC(t) = Va (S1 − S4) + Vb (S3 − S6) + Vc (S5 − S2)

ia(t) = iDC(t) (S1 − S4)

ib(t) = iDC(t) (S3 − S6)

ic(t) = iDC(t) (S5 − S2) (7.24)

Vuv(t) = VDC(t) (Su − Sv)

Vvw(t) = VDC(t) (Sv − Sw)

Vwu(t) = VDC(t) (Sw − Su)

Vun(t) =Vuv(t) − Vwu(t)

3

Vvn(t) =Vvw(t) − Vuv(t)

3

Vwn(t) =Vwu(t) − Vvw(t)

3iDC(t) = iu(t).Su + iv(t).Sv + iw(t).Sw (7.25)

7.6 Modelling of Direct and Indirect Matrix Converters 125

The overall scheme of simulation for the indirect converter is shown in Fig. 7.20.Fig. 7.21 shows the output line-line voltage and Fig. 7.22 shows the outputphase-neutral voltage.

Figure 7.18: DC link voltage : Indirect Matrix Converter

d0

dα

dβ

m1

m2

m0

Ratio CalcDuty Modulation

Functions

Sector Number

Mod.Index

Clock CarrierGen./TimingSync. Circuit

Ref. Out Freq.Ref. Angle Gen

Ref. Phase

Sector

Carrier

PWM

Identification

Figure 7.19: Structure of Output Modulator


Figure 7.20: Indirect Converter Model

Figure 7.21: Output Line Voltage: Indirect Matrix Converter

7.6.2 Direct Converter

The Direct Converter model is given in Eqn. 7.4. The overall structure of theDirect converter is shown in Fig. 7.23. Fig. 7.24 shows the output line-linevoltage and Fig. 7.25 shows the output phase-neutral voltage.

7.7 Real-Time Simulation 127

Figure 7.22: Output Phase Voltage : Indirect Matrix Converter

Figure 7.23: Direct Matrix Converter Model

7.7 Real-Time Simulation

The Matrix Converter modulators are implemented in FPGA as described inthe previous section. The Converters and the motor are also be modelledand implemented in the FPGA. Induction Motor model is implemented asexplained in chapter ?. It then forms a real-time simulation of the converterand its controller. The advantage of such simulation is that it gives results


Figure 7.24: Line-Line Voltage : Direct Matrix Converter

Figure 7.25: Phase Voltage: Direct Matrix Converter

7.7 Real-Time Simulation 129

in real time. One can observe the nature and form of the output variables ina an Oscilloscope. For implementing the converters, the models described inEqn. 7.24, 7.25 and 7.4 are used. These equations can be implemented indigital form using adders and subtracters.

To illustrate how the converter equations are implemented in FPGA, theinput converter model is shown in Fig. 7.26.

While implementing the converter models, the per-unit system adopted issame as that of modulators. Sinusoidal sources are also generated in the FPGAwith sine tables.

Fig. 7.27 shows the DC link voltage of the indirect converter simulated inreal-time in the FPGA. Fig. 7.28 shows the output phase voltage. Thesewaveforms exactly match that of the offline simulation results presented insection 7.6. Fig. 7.29 shows the direct online starting characteristics of an

Figure 7.26: Input Converter Model in FPGA

Induction Motor driven by the Direct Matrix Converter. Here, the converter,modulator and the machine are modelled together in the FPGA. This showsthe capability of the FPGA platform to simulate in real-time, even a complexdrive system as a Matrix Converter Drive.


Figure 7.27: DC link voltage : Real-time simulation

Figure 7.28: Output Phase Voltage : Real-time simulation

7.8 Conclusion 131

Figure 7.29: DOL starting of Induction Motor fed by Matrix Converter : Real-time simulation

7.8 Conclusion

The principle of Direct and Indirect Matrix Converters has been explained.Modulation of Matrix Converters is shown and implemented in FPGA basedcontroller. Both Real-time and offline simulation results are presented.


Bibliography

[1] Steven C. Chapra, Raymond P. Canale, Numerical Methods for Engineers,2nd edition, 1990.

[2] Werner Leonhard, Control Of Electrical Drives, 3rd edition.

[3] R.Krishnan, Electric Motor Drives Modeling, Analysis, and Control, Pear-son Education, First Indian Reprint, 2003.

[4] S. Venugopal and G. Narayanan ”Design of FPGA Based Digital Platformfor Control of Power Electronics Systems”, Proceedings of 2nd National

Power Electronics Conference, December 22-24, 2005, pp. 409-413.

[5] V.T Ranganathan, “Course Notes on Electric Drives,”Department of Elec-trical Engg., IISc, Bangalore.

[6] “Laboratory Manual for Digital Control of Power Converters,” PowerElectronics Group, Department of Electrical Engg., Indian Institute ofScience, Bangalore.

[7] Patrick W, Wheeler,Jon C. Clare, Lee Empringham, and Alejandro We-instein,“Matrix Converters: A Technology Review,” IEEE Trans. On IE,vol.49, No.2, pp. 276-287

[8] L. Huber, D. Borojevic,“Space Vector Modulated Three-Phase to ThreePhase Matrix Converter with Input Power Factor Correction,” IEEETrans. Ind.Appl., Vol. 31, No. 6, pp.1234-1246, Nov/Dec 1995.

[9] A. Alesina, M.G.B Venturini, “Analysis and Design of Optimum Ampli-tude Nine-Switch Direct AC-AC Converters,” IEEE Trans. On PE, Vol.4,pp. 101-112, Jan. 1989.

[10] Mohan Undeland Robbins, Power Electronics Converters, Application,Design, Third Edition, John Wiley and Sons.

[11] Muhammad H. Rashid, Power Electronics Handbook, Academic Press.

[12] V. Ramanarayanan, Course Material on Switched Mode Power Conver-sion, 2006.

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