Boost Paper Unified Rev NMG 24-02-2016

8/18/2019 Boost Paper Unified Rev NMG 24-02-2016

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Energies 2016, xx, 1-x; doi:10.3390/——OPEN ACCESS

energiesISSN 1996-1073

www.mdpi.com/journal/energies

Article

A Framework to Power Electronic Converters Design and

Control By Including Dynamical System Response Criteria:

Non-ideal Boost DC/DC Converter Application

Jorge H. Urrea-Quintero 1, Nicolás Muñoz-Galeano 1,* and Lina M. Gómez 2

1 Universidad de Antioquia, Medellín 05001000, Colombia; e-mail: [email protected] Universidad National de Colombia, Medellín 05001000, Colombia; e-mail: [email protected].

* Author to whom correspondence should be addressed; [email protected], tel:

+57-4-2196445.

Received: xx / Accepted: xx / Published: xx

Abstract: This paper presents a framework to design and control Power Electronic

Converters (PECs). For this purpose, a non-ideal Boost DC-DC converter is dynamically

modeled and analyzed in steady-state. A non-linear average dynamical model is derived in its

general and bilinear form applying the Kirchhoff’s laws. Obtained average model is suitable

for implementation in any computational tool to large and small transients system analysis.

Then, steady-state model is obtained from average model, which allows to derive expressions

for equilibrium conversion ratio M (D) and efficiency η of the system. Later, conditions

for Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM)

are found. Simulations were made to see how parasitics losses affect both equilibriumconversion ratio and efficiency of the system. Then, inductor current and capacitor voltage

ripples analysis are carried out to find lower boundaries for inductor and capacitor values.

Boost DC-DC converter passive elements are sizing taking into account both steady-state

and zeros-based analyses. Finally, a non-ideal Boost DC-DC converter is designed and a

PI-based Current Mode Control (CMC) structure is implemented. PI controllers are tuning

by means of root-locus technique. Designed Boost DC-DC converter is implemented in

PSIM and system operating requirements are satisfactorily verified.

Keywords: power electronic converters; losses analysis; dynamical modeling; steady-state;efficiency.


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1. Introduction

Technological developments in power electronic fields have increased the use of DC-DC converters

in a large variety of applications, from the simplest ones (power supply for mobile phones or laptops

[1]) to more demanding ones (applications in the aeronautics field [2,3], automobiles industry [4–6],

telecommunications [7,8], and renewable energy field [9,10]). DC-DC converters main role is to

adjust voltage level, providing a regulated output voltage based on a variable voltage power supply.

In consequence, DC-DC converters represent an interesting and active research domain [11].

Design procedures of PECs must stablish a trade-off between passive elements sizing and dynamical

performance due to the close dependence between them, in a way that dynamical performance is not

deteriorated and operating requirements are satisfied [12]. This task represents a challenge for designers

because it requires a deep understanding of system dynamics, which, generally, implies to construct a

non-linear system dynamical model and its implementation in any computational tool [13,14].Modeling and simulation of PECs are essential steps that enable design verifications and control

of numerous electrical energy systems including modern electric grid and its components, distributed

energy resources, as well as electrical systems of ships, aircraft, vehicles, industrial automation, among

others [15].

Dynamical modeling and steady-state analysis of PECs have received a significant attention as tools

to achieve a deep understanding to suitable system design [11,12,15–21]. Dynamical modeling provides

a set of equations that describe dynamical system evolution, which allows to analyze dynamical system

performance and its relation with passive elements values [12]. In the other hand, steady-state analysis

provides expressions to determine PEC: (a) (M (D)), (b) (η), and (c) CCM and DCM boundaries [13,16,19].

Multi-resolution PEC models can be constructed, where ideal as well as non-ideal passive elements

are taken into account [22]. If only ideal passive elements are considered, PEC model is simplified. As

a consequence, if parasitic losses are neglected, models do not adequately represent the PEC behavior in

its entire operation range [23]. Moreover, ideal PEC models can not predict both M (D) and η limitations

[19]. Furthermore, ideal PEC models might lead to failure in predicting fast-scale instabilities [ 24,25].

Parasitics losses can be considered in the PEC design stage when system dynamical performance

and η are taken into account [19]. Parasitics losses are typically modeled as appropriate Equivalent

Series Resistances (ESR) associated with PEC passive elements [11,16,26,27]. Several works proposing

different PEC modeling approaches have been carried out [11,22,26,28–32]. Nevertheless, in the

reviewed literature, it does not exist a consensus about what is a suitable detailed level of the model,

such that the PEC is accurately represented, without the model derivation become as a challenge for

the designer. However, the trend remains the so-called average models, which describe low-frequency

dynamics of the system, neglecting high-frequency dynamics due to the switching [12,14,15,33–36].

From [15], it is possible to conclude that average models could be the best option to PECs

representation due to themselves: (a) are continuous and allow conducting large-signal time-domain

transient studies of the system with multiple power electronic modules, controllers, and mechanicalsubsystems; and (b) allow small-signal analysis, where the frequency-domain transfer functions and


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impedance characteristics are typically required for the design of controllers and stability analysis of the

overall system.

Average models that regard as well as disregard, some or all, parasitics losses have been presented

[12,14,34,36]. Recent works [26,36–40] show that a practical level of model detail for PECs includesparasitics losses as ESRs and disregards losses due to the switching. Models with this level of detail are

suitable for system designed, M (D) derivation, η analysis, and dynamical performance evaluation [38].

Moreover, these models are suitable for control purposes [14,36].

It is clear that based on average models, PECs can be designed and a dynamical performance analysis

can be carried out. Nevertheless, it is needed a design procedure that comprise all necessary steps to

design a PEC such that a set of given operating requirements are satisfied. Additionally, this design

procedure must be simple but useful.

In PECs field only few works that take into account the integration of system design and control

have been carried out [41–43]. In [41], the integrated design and control of a Buck DC-DC converter isinvestigated. This paper simultaneously optimal design the converter and its control structure. Averaged

linear model is employed as converter model. Covariance Control Theory (CCT) is adopted as method

to control structure design. CCT is a method for parameterization of all-stabilizing controller in terms of

the closed-loop covariance matrix.

Authors in [42] investigate how to maximize the dynamical performance of a Buck-Boost DC-DC

converter using an integrated design and control approach. As the considered Buck-Boost DC-DC

converter has nonlinear dynamics, a linearized averaged model is considered to simplify the problem. As

controller, a PID is selected. Averaged model parameters and controller parameters to be tuned are state

variables dependent, thus a nonlinear optimization problem is obtained. Several Buck-Boost DC-DC

converter reference trajectories are taken as reference to measure the converter dynamical performance

using a quadratic function cost. These reference trajectories are including in the function cost to be

optimized. Sequential quadratic programming is then used to solve the nonlinear optimization problem.

The two approaches presented by [41] and [42] fix the control structure. They provide optimal

parameters for fixed control structure, but they do not, in general, provide the optimal controller. A

reason that avoids finding out the optimal controller is the necessity to test iteratively all possible control

structures to find the optimal one.

Authors in [43] tackle the gap between methods that optimally design circuit parameters with anon-optimal controller and optimal control methods. The scope of this work is to optimally design

circuit parameters for control purpose that give a performance close to the limits of the circuit, but

without imposing any control structure. The considered design objectives are dynamical performance

and energy efficiency. In this work is proposed a simultaneous optimization of the circuit parameters

and control input using a variable substitution technique and a decomposition of the general min-max

problem into two simple min-max problems. The first min-max optimization problem yield the optimal

sequence of state for the worse case load, which is unique, one of the sought circuit parameter and

an auxiliary control input which embeds the effect of the other disturbances. These results are used

in a second min-max optimization problem to obtain real optimal control input and remaining circuit

parameters.


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Although in [43] none control structure is fixed, optimization techniques in this work are more

complex than optimization techniques adopted in [41] and [42]. In consequence, still is needed a

framework to easy design and control PECs. In this paper, a framework to easy design and control

PECs is provided. The detailed analysis of a non-ideal Boost DC-DC converter operating in CCM [44]is carried out since is one of the basic DC-DC converter topologies.

In this paper, a typical sequential form to PECs design is adopted, i.e., PEC structure is selected,

passive elements are sizing, and control structure is designed. However, unlike typical approaches to

PECs design, in this paper, a zeros-based analysis is carried out in order to include a dynamical system

response criteria to select passive elements size.

In a system, dynamical response is determined by poles and zeros location. Poles do not depend on

either system inputs or outputs. However, poles determine whether the system is stable or unstable, as

well as its natural frequency. Moreover, every pole generates a natural mode in the system response. In

contrast, system zeros are determined by the selected system inputs and outputs. Zeros location is relatedto system performance limitations, additional overshoot in unit step response, and undershoot magnitude

due to the system non-minimum phase behavior associated with Right Half Plane (RHP) zeros (unstable

zeros) [45].

Zeros modify system natural modes. PEC design process could takes into account the zeros location

such that several system dynamical characteristics are avoided such as both large currents and voltages

overshoots, or both sharp currents or voltages undershoots. Large currents or voltage overshoots can

cause converter failures. Otherwise, sharp currents or voltages undershoots are undesired behavior when

classical control structures are employed due to tracking limitations with feedback systems [46], [47].

Accordingly, zeros location analysis objective is to find suitable values for L and C such that RHP zeros

are avoided or that their impact are attenuated. In consequence, a trade-off between passive elements

size and system dynamical performance is established.

In this paper, widely accepted Current-Mode Control (CMC) structure for Boost DC-DC converter is

designed [48], [49]. The Boost DC-DC converter contains a RHP zero, i.e, the Boost DC-DC converter

could have a non-minimum phase behavior. Non-minimum phase behavior is the reason why a CMC

structure is needed [48]. CMC structure employs cascaded loops. This cascaded structure allows the

output voltage regulation while preserving the inductor current within specified safety limits. The outer

control loop deals with voltage regulation imposing low-frequency dynamics and the inner loop concernsthe faster current control. The voltage controller provides the setpoint of the inductor current, and this

latter acts as the control input of the outer voltage loop.

Standard controllers are employed for the CMC structure. Simple and robust classical invariant PI

controllers that are tuned based on linearized Single-Input-Single-Output (SISO) averaged models of the

Boost DC-DC converter. These PI controllers generate a continuous control signal (duty ratio d), which

needs a modulation PWM so it may be applied to the power switching gates.

The remaining of the paper is organized as follows: in the next section, both time- and

frequency-domain models of non-ideal Boost DC-DC converter is derived. In section 3, the non-ideal

Boost DC-DC converter is panned out in steady-state. Section 3 is composed of subsections 3.1, 3.2,

3.3, and 3.4. In subsection 3.1 an expression for M (D) is derived including ESRs. In subsection 3.2, an

efficiency expression η is derived taking into account ESRs. In subsection 3.3, conditions for operate in


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CCM or DCM are found. Knowing these conditions, it is possible to design a Boost DC-DC converter

that always operate in CCM if load variations are given. In subsection 3.4 inductor current and capacitor

voltage ripples analysis are carried out to find lower boundaries for inductor and capacitor values such

that ripples requirements are satisfied. In section 4, passive elements are sizing such that operatingrequirements are satisfied and system dynamical performance is achieved. Mathematical model is

contrasted with a PSIM implementation of the Boost DC-DC converter. In section 5, widely accepted

Current-Mode Control (CMC) structure for Boost DC-DC converter is designed. The aim is to design

a suitable control structure such that control objective is achieved. This stage is composed of following

subsections: in subsection 5.1, controllers are tuned by means of root-locus technique; in subsection

5.2, closed-loop system performance verification is carried out; and in subsection 5.3, system operating

requirements are verified. Finally, conclusions are provided in section 6.

2. Non-Linear Dynamical Modelling

Figure 1 shows a circuital representation of a typical non-ideal Boost DC-DC converter supplying

a dominant-current load represented as a Norton equivalent model. Engines and inverters are common

dominant-current loads that can be supplied by a Boost DC-DC converter. In Figure 1, L is inductor, C

is capacitor, and RL and RC are ESR for L and C , respectively. RL and RC represent all parasitic losses

in adopted non-ideal Boost DC-DC converter for this paper.

The Boost DC-DC converter operating in CCM can take two configurations according to the switch

position as shown in Figure 1: configurations (a) and (b) correspond to switch H = {h1, h2} being

turned on h1 = 1, h2 = 0 and turned off h1 = 0, h2 = 1, respectively. Therefore, switching function ucan be defined as follows: u = h1 = 1 − h2.

State variables (inductor current iL and capacitor voltage vC ) are defined to represent energy variation

of the system. System inputs are u, DC input voltage source vg, and current source io that is useful

to represent system current perturbations; system outputs are output voltage vo and iL. By applying

Kirchhoff’s laws to system in Figure 1, dynamical model given by equations (1)-(2) are derived.

LdiLdt

= vg − (RL + φC (1 − u))iL + φC R − 1

(1 − u)vC + φC (1 − u)io (1)

C dvC dt

=

1

1 + αC

(1 − u)iL −

vC R − io

(2)

Where αC = RC

R and φC =

RC 1 + αC

.

In this paper, widely accepted PI controllers based Current-Mode Control (CMC) structure for Boost

DC-DC converter is adopted [48], [49]. PI controllers tuning require a frequency-domain model. From

non-linear dynamical model given by equations (1) and (2), it is possible to obtain a linear state-space

model of Boost DC-DC. Next, frequency-domain model is obtained by means of the realization given

by the equation (3).

G(s) = 1

det(sI − A)C [adj(sI −A)] B + D (3)


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Figure 1. Nonideal DC-DC Boost converter circuital diagram.

Linear state-space model for Boost DC-DC converter is given by equation (10). Where x = [iL, vC ]T

,

u = [d, vg, io]T

, and y = [iL, vo]T

.

In equation (10), I L and V C , D and I o are states and inputs in their rated values, respectively.

Applying realization given by equation (3) to equations in (10), transfer functions given by equations

(4) and (5) are obtained. Numerator of equation (4) has three components, one for each system input,

i.e., d, vg, and io, respectively. Numerator of equation (5) has three components, one for each system

input, i.e., d, vg, and io, respectively.

Gvo(s) =

−(RLI Ls + φC RI o(1 −D) + φC (1 − D)V C − R(1 − D)V C + RRLI L)

(φC C (1 + αC )s + 1)

R(φC C (1 + αC )s + 1)(1 − D)

R(φC (1 − D)2 − φC (1 −D) − RL)(φC C (1 + αC )s + 1)

T

(RLC (1 + αC ))s

2 + φC RC (1 −D)(1 + αC )s − (φC − R)(1 − D)2

+φC (1 − D) + RL

(4)


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GiL(s) =

1

R

(((φC R2CI L) − (φC R2CI o) − (φC RCV C ) + (R2CV C ))(1 + αC )s

−φC R(1 −D)I L + R2

(1 −D)I L + φC RI L − φC RI o − (φC −R)V C )

RC (1 + αC )s + 1

φC RC (1 −D)(1 + αC )s + R(1 −D)

T

(RLC (1 + αC ))s2 + φC RC (1 −D)(1 + αC )s − (φC − R)(1 − D)2

+φC (1 − D) + RL

(5)

Once the current control loop in the CMC structure is closed, equivalent simplified representation of

the Boost DC-DC converter showed in Figure 2 is obtained. Large- and small-signal models of simplified

Boost DC-DC converter are given by equations (6) and (7), respectively. Applying realization given by

the equation (3), transfer functions of simplified model are given by the equation (9).

Figure 2. The equivalent simplified representation of the Boost DC-DC converter.

C dvC dt

=

1

1 + αC

iLREF (1 − D) −

vC R − io

(6)

v̇C = − 1

1 + αC 1

RC vC +

1

1 + αC

(1 −D)

C −

1

1 + αC

1

C

iLREF

io

(7)

vo

=

1

1 + αC

vC

+

1

1 + αC

RC (1 − D) −

1

1 + αC

RC

iLREF

io

(8)

Gvo(s) =[(1 + αC )RCRC s + R + RC ] (1 −D)−(1 + αC )RCRC s + R + RC

(1 + αC ) [(1 + αC )RCs + 1] (9)


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˙iLv̇C =

−

RL + φC

L

φC R − 1

(1 −D)

L

(1 −D)

(1 + αC )C −

1

RC (1 + αC )

iL

vC +

(10)

φC I L − V C

φC R − 1

− φC I o

L

1

L

φC (1 −D)

L

− I L

(1 + αC )C

0 − 1

(1 + αC C )

dvg

io

iL

vo

=

1 0

φC (1 −D) 1 − φC

R

iL

vC

+

0 0 0

−φC I L 0 −φC

dvgio

3. Steady-State Analysis

Once the system model is obtained following analysis might carried out: (1) derivation of M (D)

expression, (2) losses effect and efficiency η expression derivation, (3) conditions analysis of CCM and

DCM, and (4) inductor current ∆iL and capacitor voltage ∆vC ripples analysis. Aim of these analysis isto determine suitable passive elements (L and C ) boundaries which satisfy design requirements.

3.1. First Step: Derivation of the Equilibrium Conversion Ratio M (D) Expression

Steady-state model allows to obtain expressions for average rated values for both vC and iL as a

function of system inputs and parameters. The steady-state model is obtained by setting to zero model

given by equations (1) and (2). Thus, equations (11) and (12) are obtained.

I L =

V C

R (1 − D) (11)

V g =

RL + φC (1 −D)

R (1 −D)

−

φC R − 1

(1 − D)

V o (12)

Capital letters indicate the steady-state average values, thus: V g is input voltage, V o is output voltage,

I L is inductor current, and D is duty cycle.

From equations (1)-(2), it is found that V o = V C in steady-state. Therefore, the expression of M (D)

for the non-ideal Boost DC-DC converter is given by the equation (13).

M (D) = V oV g =

(1 − D)1 −

φC R

(1 − D)2 +

φC R

(1 −D) + αL(13)

where


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αL = RL

R

M (D) indicates the Boost DC-DC converter elevation voltage factor in terms of D, R, RL, and φC .

It is important to remark that if RL = 0 and RC = 0 in equation (13), this equation coincides with

ideal Boost DC-DC M (D), i.e., M (D) = 1

(1 −D).

3.2. Second Step: Losses Effect and Efficiency Expression Derivation

If ideal conditions are considered in Boost DC-DC converter analysis, M (D) tend to ∞ when D tend

to 1 and converter has an efficiency equal to 100%. However, these characteristics are not true in a real

PEC application.

This section shows how parasitics losses affect both M (D) and η in the non-ideal Boost DC-DC

converter case. Losses effect and efficiency analysis are carried out in order to find suitable values for

RL and RC such that designed PEC satisfies desired operating requirements.

The DC transformer is used to model ideal functions performed by a DC-DC converter [44]. This

model correctly represents the relations between DC voltages and currents of the converter. The resulting

model can be directly solved to find voltages, currents, losses and efficiency in the non-ideal Boost

DC-DC converter.

Equations (14) and (15) are obtained from equations (1) and (2). These equations stablish that average

value of both iL and vC are equal to zero in steady-state.

0 = V g − (RL − φC (1 −D)) I L −

1

1 + αC

V C (1 −D)

V d

(14)

0 = −

1

1 + αC

V C

R +

1

1 + αC

I L (1 −D)

I d

(15)

A circuital model based on equations (14) and (15) is built. This circuital model describes the DCbehavior of the Boost DC-DC converter with inductor and capacitor losses. A circuit of which Kirchoff

loop and node equation represent equations (14) and (15).

Equation (14) describes the average inductor voltage in the time interval T s and DC components of

voltages around a loop containing the inductor L, with loop current equal to the DC inductor current

I L. Therefore, a circuit containing a loop with current I L, corresponding to equation (14), is built in

Figure 3a. The first term in equation (14) is input voltage V g. The second term is a voltage drop of value

RL − φC (1 − D)I L, which is proportional to current I L in the loop. The third term is the dependent

voltage source V d = 11+αC V C (1−D), which depends on V C . This term is modeled using a dependentvoltage source as shown in Figure 3a. The polarity of the source is chosen to satisfy equation (14).Equation (15) describes the DC components of currents flowing into a node connected to the capacitor

C . Therefore, a circuit containing a node connected to the capacitor is built in Figure 3b, of which the


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node equation satisfies equation (15). The first term in equation (15) is a current magnitude

1

1+αC

V oR

,

proportional to the DC capacitor voltage V C in steady-state. The second term is a dependent current

source I d = 1

1+αC I L(1−D), which depends on DC inductor current I L. This term is modeled using a

dependent current source as shown in Figure 3b. The polarity of the source is chosen to satisfy equation(15).

Figure 3. Non-ideal Boost DC-DC Converter source depended equivalent circuit diagram.

Figures 3a and 3b are combined into a singe circuit. Circuits of Figures 3a and 3b can be further

simplified by acknowledging that V d and I d constitute an ideal DC transformer. In each case, thecoefficient is

1

1+αC

(1 − D). Hence, the fact that this coefficient appears on the primary rather than

the secondary side is owing to the symmetry of the transformer. Therefore, there is an equivalent DC

transformer, with turns ratio

1

1+αC

(1 −D) : 1, that represents the non-ideal Boost DC-DC converter.

Substitution of the ideal DC transformer model for the dependent sources yields the equivalent circuit of

Figure 4.

Figure 4. Ideal DC transformer model of the Boost DC-DC converter.


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The main importance of the equivalent circuit model in Figure 4 is that it allows to compute converter

efficiency η. Figure 4 predicts that the convert input power is given by the equation (16).

P in = V gI g = V g V C (1 − D)R (16)The load current is equal to the current in the secondary of the ideal DC transformer I d. Hence the

model predicts that the converter output power is given by the equation (17).

P out = V oI o = V o

V C

(1 + αC )R

(17)

Therefore, η = P out

P inis given by equation (18).

η = 11 + αC (1 − D) M (D) (18)Simulations of equations (13) and (18) are shown in Figure 5 for several values of αC and αL ratios

in order to see how much losses affect both M (D) and η.

Figure 5 shows αC and αL ratios effects on M (D) and η. Simulations on Figure 5a were carried out

for every possible combination of αC = [0, 0.05, 0.1] and αL = [0, 0.05, 0.1]. αC = 0 and αL = 0 are

the ideal case for the Boost DC-DC converter (without losses). The group of curves that corresponds

to the black lines (above lines group) has αL = 0 and αC = [0, 0.05, 0.1]. It can be noted that while

αC increases, curves move towards right. However, M (D) in the converter has an increasing trend and

eventually tend to infinite. For group of curves αL = 0.05 and αC = [0, 0.05, 0.1] (middle group lines),it is noted that while αC increases, M (D) decreases. M (D) also decreases for lines group αL = 0.1 and

αC = [0, 0.05, 0.1] (below lines group). From Figure 5, it can be concluded that M (D) has a tendency to

decrease in higher proportion when αL increases than when αC increases. Really, losses on the inductor

determine quadratic trend of the M (D) curves; while αC , to a lesser extent, determines the Boost DC-DC

converter gain. Both αL and αC determine M (D) form, however, αL determines curve trend.

From Figure 5b, it is observed that maximum η value reached by the converter is determined by losses

and it is given in D = 0 for every M (D) curve. For the studied case, it is the combination of αC and

αL what determines maximum value of η. η decreases while D increases dropping to 0 when D tends to

1, hence, converter should operate, as far as possible, with low D values. Increases of αC or αL causesdecrease of η , therefore, as far as possible, αC and αL should tend to zero to guarantee high converter

η. From Figure 5a it seen that for a value of M (D) there are two possible D values; however, from

Figure 5b is seen that higher D value always corresponds to a less η . Hence, if it is desired to operate

the converter as efficient as possible, always lesser D values that satisfies M (D) requirement must be

selected. Similar to Figure 5a, for Figure 5b, values were also clustered in groups of curves. For αL = 0

and αC = [0, 0.05, 0.1] (above lines group), it noted that while αC increases, η decreases notoriously.

For curves group αL = 0.05 y αC = [0, 0.05, 0.1] (middle lines group) and for curves group αL = 0.1

y αC = [0, 0.05, 0.1] (below lines group), something similar occurs, η decreases while αC increases.

However, decrease in η is more notable when αL increases than when αC increases. Combined effect for

high αL and αC leads to highly inefficient system with high losses.


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Figure 5. (a) the conversion ratio M (D) v.s. the duty cycle D . (b) Efficiency η v.s. the duty

cycle D

3.3. Third Step: Conditions Analysis of Continuous Conduction Mode (CCM) and Discontinuous

Conduction Mode (DCM)

The CCM is suggested since DCM causes larger voltage ripple [50], [51]. Furthermore, the peak

inductor current in DCM is higher than that in CCM with the same power level and current stress on the

power switch is also higher [52].

By [44], the sufficient conditions for operation in the CCM and DCM are given by equations (19) and

(20), respectively.

|I L| > |∆iL| for CCM (19)

|I L| < |∆iL| for DCM (20)

Where |I L| and |∆iL| are found assuming that the converter operates in CCM.


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The DCM operation condition for the Boost DC-DC converter is given by the equation ( 21).

D

(1 −D)

M (D) −

1

R >

2L

RT s(21)

where

K (D) = D

(1 −D)

M (D) −

1

R

(22)

K = 2L

RT s(23)

Dimensionless parameter K is a converter measure of the tendency to operate in the DCM [44]. Large

values of K lead to CCM, while small values of K lead to the DCM for some values of D. The critical

value of K is the boundary between modes, K crit(D), and it is a function of D and R, RC , RL, i.e, load

and ESRs of C and L.

Function K crit(D) has a critical point given by the equation (24).

D = 1

3 [−3αC + αC αL + αL] (24)

There is a maximum for the function in critical point given by the equation ( 24) due to the fact that

the second derivative of K crit(D) given by the equation (25) is always negative for D ∈ [0, 1].

d

2

K (D)dD2 = − 11 + αC (6D + 2αC ) (25)

From result given by equations (24) and (25), the sufficient condition for always operate in CCM is

given by the equation (26).

max (K (D)) < min (K ) (26)

where

min (K ) = min 2LRT sTherefore, if a value for R was given in the system specifications, a condition for the maximum

possible value of L is given by the equation (27) such that equation (26) is assured.

L > RT s

2 max(K (D)) (27)

Simulations of equations (22) and (23), varying R and L, are shown in Figure 6. Figure 6 shows how

variations of R and L affect both K crit(D) and K functions.

Figure 6 shows K (D) limits (continuous gray line) between CCM and DCM for the non-ideal Boost

DC-DC converter. Above K (D), converter works in CCM, while below converter works in DCM. Rand L factors influence operating mode of the system.

Figure 6a shows the effect on K when varying L = [20, 40, 60, 80]mH , setting R in 50Ω. R = 50Ω

represents an adverse case for the system (it is a heavy load). From Figure 6a, it is observed that converter


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Figure 6. (a) K (D) v.s. K varying R . (b) K (D) v.s. K varying L.

works in CCM for L values equal to 40, 60y80mH , while for L = 20mH the line intercepts K (D) limit,

hence, it works in DCM for several D values.

Figure 6b shows the effect on K when varying R = [125, 150, 175, 200]Ω, setting L in 100mH .L = 100mH represents a favorable case for the converter since ∆iL value decreases when L increases

and, therefore, probability of ∆iL > I L (DCM condition). From Figure 6b, it is observed that while R

decreases, the system is less likely to DCM. For R values equal to 150, 175y200Ω, the converter can or

cannot operate in CCM depending on D value. To guarantee CCM operation, independent of D value,

R value equal to 125Ω must be selected.

3.4. Fourth Step: Inductor Current and Capacitor Voltage Ripple Analysis

∆iL and ∆vC analysis is carried out to determine constraint equations for a suitable choice of bothL and C values. The analysis carried out in this section is suitable for the Boost DC-DC converter

operating in CCM.


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Figure 7 shows both typical inductor voltage vL and iL linear-ripple approximations. Slope, with

iL increasing or decreasing, is deduced from the analysis of V L at each subinterval of time taken into

account. Typical values of current inductor ripple ∆iL lie under 10% of the full-load value of I L [44].

From Figure 7 is seen thatiL begins at initial value iL(0). Then, iL increases with a constant slope duringthe first subinterval (DT s), h1 = 1 and h2 = 0. Switch changes to position h1 = 0 and h2 = 1 at time

t = DT s. Then, iL decreases with a constant slope. Switch changes back to position h1 = 1 and h2 = 0

at time t = T s and the process repeats.

Figure 7. a. Typical inductor voltage linear-ripple approximation. b. Typical current

inductor linear-ripple approximation.

As illustrated in Figure 7b, the peak inductor current I pk is equal to I L plus the peak-to-average ripple

∆iL. I pk flows through inductor and semiconductor devices that comprise the switch. The knowledge of

I pk is necessary when specifying the rating of the device.

The ripple magnitude can be calculated knowing both the slope of iL and the length of the first

subinterval (DT s). The iL linear-ripple approximation is symmetrical about I L, hence, during DT s, iL

increases by 2∆iL (since ∆iL is the peak ripple, the peak-to-peak ripple is 2∆iL). Thus the change in

current, 2∆iL, is equal to the slope with iL increases.

The inductor value L can be chosen from equation (28).

L =

V g − αL(1 − D)V o2∆iL

DT s (28)

Where T s = 1

f swand f sw is the converter switching frequency.

Equation (28) is a lower boundary for L value, where L can be choose such that in the worst Boost

DC-DC operating condition a maximum ∆iL is attained.

Likewise, vC linear-ripple approximation is depicted in Figure 8b and an expression derived for the

output voltage ripple peak magnitude ∆vC is obtained. Capacitor current linear-ripple approximation I C

is depicted in Figure 8a. vC begins at initial value vC (0). vC decreases with a constant slope during the

first subinterval (DT s), h1 = 1 and h2 = 0. The switch change to position h1 = 0 and h2 = 1 at timet = DT s. Then, vC increases with a constant slope. The switch changes back to position h1 = 1 and

h2 = 0 at time t = T s and the process repeats.


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Figure 8. a. Typical capacitor current linear-ripple approximation. b. Typical capacitor

voltage linear-ripple approximation.

The ripple magnitude can be calculated knowing both the slope of vC and the length of DT s. Thechange in vC , −2∆vC , during DT s, is equal to the slope multiplied by DT s. Equation (29) can be used

to select capacitor value C to obtain a given ∆vC .

C = V o

2R∆vC DT s (29)

Equation 29 is a lower boundary for C value, where C can be choose such that in the worst Boost

DC-DC operating condition a maximum ∆vC is attained.

4. Passive Elements Sizing

In this section, non-ideal Boost DC-DC converter operating requirements are specified. Then, passive

elements are sizing such that operating requirements are satisfied and system dynamical performance is

achieved. Finally, mathematical model is contrasted with a PSIM implementation of the Boost DC-DC

converter.

4.1. System Operating Requirements

In Boost DC-DC application, typical requirements are: input voltage range, output voltage range,

output power range, output current range, operating frequency, output ripple and efficiency. Unless

otherwise noted, continuous operating mode is assumed.

The set of operating requirements for the Boost DC-DC converter are specified in Table 1.

4.2. Passive elements sizing

Once operating requirements are established, passive elements are sizing. Concerning to passive

elements value selection, the main interest is to select suitable values for inductors and capacitors

such that constraints like maximum physical admissible currents and voltages, converter efficiency, and

converter conduction mode are satisfied by keeping an acceptable dynamical system performance.

Via steady-state analysis expressions given by (28) and (29) were deduced for lower inductor L and

capacitor C boundaries, respectively. These deduced expressions are suitable to choose L and C values in


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Table 1. Boost DC-DC converter operating requirements.

RequirementValues

Min Typ Max

Input voltage range 30V 35V 40V

Output voltage range 50V 70V 95V

Output power range 0W 100W 300W

Output current range 0A 2A 8A (At 50V)

Operating frequency 100kHz

Output current ripple 1% 5% 10%

Output voltage ripple 0.1% 0.5% 1%

Steady-State efficiency 90% 95% 98%

Load 25Ω 50Ω 100Ω

function of ∆iL, ∆vc, states, and inputs values in steady-state. Additionally, from converter conduction

mode analysis was deduced the expression given by (27) that allows to guarantee the Boost DC-DC

CCM operation in all operating range by choosing L value given the load impedance value R.

In PECs are desired that ∆iL ≤ max(∆iL) and ∆vo ≤ max(∆vo) are assured in entire operation

range. Then, based-on worst condition for ∆iL and ∆vo, L and C lower boundaries can be deduced such

that ripple constraints are satisfied. Equations (30) and (31) give lower boundaries for L and C values,

respectively.

L ≥

max(V g) −

RL

max(R)(1 −D) min(V o)

2max(∆iL)

DT s (30)

C ≥ max(V o)

2 min(R) max(∆vo) (31)

Equation (27) also gives a minimum boundary for L value. Then, equations (30) and (27) must be

evaluated and maximum L value must be selected as lower boundary.

Equation (30) depends of αC . Equation (27) depends of M (D), which depends of RL. Therefore, RC

and RL must be defined in order to choose L value.

From steady-state analysis, instead of calculate RC and RL values, it is suitable to establish αC and

αL values. αC and αL values can be chosen such that the system efficiency is η ≥ 90% in entire

operating range. Worst Boost DC-DC condition is when M (D) is maximized. M (D) = V o/V g, then

max(M (D)) = max(V o)/ min(V g). According to operating requirement in Table 1, min(V g) = 30V

and max(V o) = 95V , thus max(M (D)) ≈ 3.17. Losses ratios must be αC


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Figure 9. (a) Conversion ratio M (D). (b) Efficiency η.

If max(∆iL) = 0.1max(I L), in order to keep a converter safe operation [52], L ≥ 326.34µH

according to equation (30). Evaluating equation (27), L ≥ 40µH to always operate in CCM. iL

ripple-based condition is a less restrictive boundary for L than CCM-based condition. Therefore,

L ≥ 326.34µH is the lower boundary for this element.

If max(∆vC ) = 0.01max(V o), in order to keep a converter safe operation [52], C ≥ 14.120µF

according to equation (31).

Minimum L and C values are selected as system parameters. By [36], RL = 150mΩ and RC =

70mΩ are selected due to the fact that in this paper a Boost DC-DC converter with similar operating

requirements are designed and experimental tested with these RL and RC vales. Next, a simulation

of the designed Boost DC-DC converter is carried out. Figure 10 shows the step system response forV g = 35V , V o = 70V , I o = 0A, L = 326.34µH , C = 14.120µF , R = 50Ω, αC = 0.0034, αL = 0.006,

and f sw = 100kH Z .

Figure 10. (a) Gvd Step system response. (b) GiLd Step system response.

From Figure 10 is seen that, with minimum values of L and C , Voltage Overshot O.S.Gvd =

57.3427%, Current Overshot O.S.GiL

d = 190.0448%, and system setting time ts = 2.3ms. From Figure

10a is seen that the peak voltage value is 214.2V , while the final voltage value is 135.5V . From Figure

10b is seen that the peak current value is 34.0A, while the final current value is 11.41A. A designed

system with these overshoots needs oversized electronic devices such that these devices support both


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peak voltages and current values without a system damage. However, the electronic devices oversizing

can be expensive and inconvenient. Therefore, in this paper, an analysis of Boost DC-DC dynamical

characteristics is carried out. Boost DC-DC dynamical characteristics analysis test the passive elements

values impact in overshoots and system setting time.In Boost DC-DC converter applications, d is chosen as control input, while vg and io are

considered disturbances. Thus, d variations effect is of primary interest over system output. Then,

duty-ratio-to-voltage-output Gvd and duty-ratio-to-inductor-current GiLd transfer functions are studied,

i.e., characteristics of equations (4) and (5) are studied.

It is possible to obtain zeros of Gvd from system transfer function in equation (4). Zeros of Gvd are

given by equations (32) and (33).

s1 = − 1

RC C (32)

s2 = 1

L

[(φC − R)V C − φC RI o]

I LR (1 −D) + RL

(33)

Zero given by the equation (32) is negative because it depends on circuit parameters, all of which are

positive. However, zero given by the equation (33) is positive because it depends on circuit parameters,

V C , and I L, all of which are positive. Also, in steady-state current source I o is equal to zero. Zero given

by the equation (33) is then placed in the RHP of Laplace domain, which mean that if vo is selected as

system output, the system could have a non-minimum phase behavior.

Non-minimum phase behavior is a well-known result derived of the Boost DC-DC converter

study [53]. To avoid this system behavior a cascade control structure has been proposed [53],

[48]. Non-minimum phase behavior is avoided with this control structure since both GiLd and

inductor-current-to-output-voltage GvoiLREF transfer functions have a minimum phase behavior as will

be shown.

It is possible to obtain zeros of G(s)iLd from transfer functions in equation (5). Zero of G(s)iLd is

given by the equation (34).

s = − 1

RC 1

1 + αC (R − φC )RI L(1 −D)

φC RI L − φC RI o + (R − φC )V C + 1

(34)

Zero given by the equation (34) is negative because it depends on circuit parameters, all of which are

positive and, in steady-state, I o is equal to zero. This zero is then placed in the Left Half Plane (LHP) of

Laplace domain, which means that the system has a minimum phase behavior.

From equations (32) and (33) is seen that zeros of Gvd are in function of L and C vales. From equation

(34) also is seen than zero of GiLd is in function of L and C values. Therefore, a simulation was carried

out to evaluate effects of large values for both L and C . Figure 11 shows Gvd and GiLd overshoots and

setting time for several values of L and C .

From Figure 11 is seen that minimum possible value for C causes maximum overshoot in vo. While

a minimum possible value for L causes maximum overshoot in iL. Moreover, minimum C and L valuesgive minimum system setting time.

In contrast, large values for C cause high overshoot for iL. While large values for L cause

high system setting time. In consequence, two additional designed requirements are given in order


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Figure 11. (a) Gvd Step system response varying C and L: overshoot with zeros. (b) GiLd

Step system response varying C and L: overshoot with zeros. c Step system response varying

C and L: setting time.

to establish maximum possible values for L and C such that system overshoots and setting time

are suitable: (a) maximum duty-ratio-to-output-voltage overshoot max(O.S.Gvd) and (b) maximum

duty-ratio-to-inductor-current overshoot max(O.S.GiLd).

From Figure 11, any effect over system performance is achieved if the values of both L and C are

increased simultaneously. However, if either L or C values are increased both O.S.Gvd and O.S.GiLd are

decreased. Nevertheless, larger values of L have a major impact that larger values of C .

L = 1mH and C = 15µF are selected by results showed in Figure 11 since with these values

O.S.Gvd

≈ 52% and O.S.GiLd

≈ 100%, i.e., O.S.GiLd

is reduced approximately 90%. Further, ts =

3.4ms, i.e., the system setting time is increased 1.1ms. Thus, these L and C values establish a trade-off

between system overshoots and performance.

4.3. System Frequency Response Verification

Frequency response of both mathematical model and a PSIM circuital implementation are contrasted

in order to validate dynamical model of the designed Boost DC-DC converter via simulation. The Boost

DC-DC converter was parameterized with L = 1mH , C = 15µF , V g = 35, V o = 70, I o = 0, αC =

0.0034, αL

= 0.006, R = 50Ω, and f sw

= 100kH z . In consequence, I L

= 2.8812A and D = 0.5141 in

the equilibrium point.

Figure 12 presents the Boost DC-DC converter Bode diagrams of the mathematical model given

by equations (4) and (5) and PSIM circuital implementation. Frequency response of the PSIM


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Figure 12. (a) Gvd Bode diagram. (b) GiLd Bode diagram.

circuital implementation coincides with mathematical model. Then, PSIM circuital implementation is

satisfactorily reproduced by mathematical model.

5. Control Structure Design

Here, widely accepted Current-Mode Control (CMC) structure for Boost DC-DC converter is

designed [48], [49]. The aim is to design a suitable control structure such that control objective

is achieved. This stage is composed of following subsections: (1) control structure selection,

(2) controllers tuning, (3) closed-loop system performance verification, and (4) system operating

requirements verification.

5.1. Controllers Tuning

Generally speaking, converter control design is focused on imposing desired low-frequency behaviorto the system by means of specified closed-loop requirements. In the Boost DC-DC converter operating

in a switch-mode power supply, feeding a certain variable load, d needs adjustments in order to ensure a

constant vo for the entire operating range (voltage regulation). Besides, against any system disturbance,

d value needs to be adjusted such that the system can be driven back to the operating point.

The controller tuning task begins with a set of design specifications. The set of specifications are a

group of goals for the behavior of the controlled system. Specifications are composed for both transient

behavior (e.g. rise time, setting time, and maximum closed-loop system overshot) and stability margins

(e.g., relative stability, gain margin, phase margin).

Time domain specifications are placed by the system performance specifications. The transient

response of a regulated system is typically limited in terms of maximum deviation from the rated output

value and setting time in response to a transient. The goal for the Boost DC-DC converter controller


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design presented is to control the output voltage vo to within 2% of rated value (i.e. 68.6V to 71.4V ) in

response to unit step transients in both input voltage vg and current source io. Also, the controller should

be able to maintain the rated output voltage within the tolerances as the input varies over a range from

30V to 40V , though this should be considered a steady-state, not transient, operating requirement. As afinal specification, steady-state error in the output voltage vo should be eliminated.

Inner loop bandwidth (i.e., current loop) must be 20kH z or less due to the fact that the Boost DC-DC

converter switching frequency is 100kH z , and outer loop bandwidth (i.e., voltage loop) must be smaller

than 1

5 inner loop bandwidth [54], i.e., smaller than 5kH z . Additionally, a robustness index M s < 2 is

desired to establish a trade-off between control performance and robustness [55].

A PI controller, acting directly on d, has been designed to track the inductor current iLREF since

GiLd exhibits a minimum phase behavior. The inductor current PI controller was designed by means

of the root-locus technique, adopting following design specifications: damping factor ζ equal to 0.707

and a 20kH z closed loop bandwidth. The designed PI controller transfer function GC iL (s) is given by

the equation (35). These PI controller design specifications ensure: (a) zero steady-state error and a

satisfactory reference tracking for frequencies below 20kH z observed on transfer function T iLiLREF in

Figure 13. (b) Effective disturbance rejection for both input voltage vg and current source io variations

observed on transfer functions T iLvg and T iLio in Figure 13, respectively. (c) A M s = 1.2.

GC iL (s) = 1.27s + 55218

s (35)

Figure 13. Inner current control loop transfer functions.

A PI controller, that provides the setpoint of the inductor current control loop, has been designed to

regulate vo since the GvoiLREF (s) transfer function given by the equation (9) exhibits a minimum phase


23/30


behavior. The output voltage PI controller was designed by means of the root-locus technique, adopting

following design specifications: damping factor ζ equal to 0.707 and a 5kH z closed loop bandwidth.

The designed PI controller transfer function GC vo (s) is given by the equation (36). These PI controller

design specification ensure: a. zero steady-state error observed on transfer function T vovoREF in Figure14. b. Effective disturbance rejection for the current source io variations observed on transfer function

T voio in Figure 14. c. A M s = 1.2.

GC vo (s) = 0.07994s + 235.1

s (36)

Figure 14. Outer output voltage control loop transfer functions.

5.2. Closed-Loop System Performance Verification

The non-ideal designed Boost DC-DC converter with its control structure has been implemented in

PSIM to assess the closed-loop system performance. Figure 15a shows the closed-loop behavior at unit

steps of io around the operating point corresponding to the full load. Two current source io unit steps

were applied to evaluate the control structure performance. First unit step was applied at t = 10ms

and for 10ms, then the current source returns to its rated value io = 0. Second unit step was applied at

t = 30ms and for 10ms, then the current source returns to its rated value io = 0. From Figure 15a is

observed a satisfactory tracking of iLREF provided by the outer PI voltage controller and a satisfactory

regulation of vo to reject the load disturbances depicted as changes in io.

Figure 15b shows the closed-loop behavior at unit steps of the input voltage vg. Two vg unit steps were

applied to evaluate the control structure capabilities to regulate vo and to evaluated the boost capabilities

of the designed Boost DC-DC converter. Firs unit step was applied at t = 10ms and for 10ms. This first


24/30


unit step was equal to vg = −5V , i.e., the final value of the input voltage was vg = 30 that corresponds

with its lower boundary. Second unit step was applied at t = 30ms and for 10ms. This second unit step

was equal to vg = +5V , i.e., the final value of the input voltage was vg = 40V that corresponds with its

upper boundary. From Figure 15b is observed a satisfactory tracking of iLREF provided by the outer PIvoltage controller and a satisfactory regulation of the vo to changes in vg. It is important to remark that

under the worst condition for input voltage vg, the Boost DC-DC convert was able to keep the output

voltage in its rated value.

Finally, Figure 15c shows the closed-loop behavior at random unit steps of both io and vg. This

unit steps were applied such that the designed control structure performance could be evaluated against

any random disturbance. From Figure 15c is possible to see that the designed control structure has

a satisfactory performance against multiple disturbances within specified design requirements for the

Boost DC-DC converter in Table 1.

Figure 15. Closed-loop behavior at unit steps system disturbances.

5.3. System Operating Requirements Verification

Figure 16 shows: (a) P in, P out, and η and (b) iL and vo, when case c of Figure 15 is considered.

From Figure 16a is seen that P out never exceeds the maximum admissible output power and it is

always less that P in. It is also seen that the Boost DC-DC converter is never 100% efficient. Furthermore,

from Figure 16a is seen that only between t = 0.01s and t = 0.02s the efficiency is below 0.9. However,

in this time interval vg is equal to 20V , i.e., in this time interval the Boost DC-DC converter operates in

a not considered condition in Table 1. Accordingly, the designed Boost DC-DC converter satisfies both

power and efficiency requirements.


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Figure 16. (a) Instantaneous Power and efficiency verification. (b) Ripples verification.

Figure 16b shows iL and vo, a zoom was made for the worst simulated system condition. From Figure

16b is seen that even in the worst iL and vo condition, ripples are below to 1%. Accordingly, the designed

Boost DC-DC converter satisfies both iL and vo ripples condition.

In conclusion, Figure 16 shows that the Boost DC-DC converter system operating requirements given

in Table 1 are satisfied even in the worst simulated case ( see Figure 15c).

6. Conclusions

In this paper, a non-ideal Boost DC-DC converter was dynamically modelled and analized in

steady-state. In contrast with several adopted topologies to study the Boost DC-DC converter, in this

work, parasitic resistances in the passive elements (L and C ) were included in order to have a more

realistic approach of the system.

Based on the circuital configurations of the Boost DC-DC converter, Kirchhoff’s law was applied to

obtain a non-linear dynamical model. The obtained non-linear dynamical model was composed of a set

of coupled non-linear differential equations in function of state variables, input variables, and system

parameters. The obtained dynamical model was suitable to describe dynamical behavior of the system

and to derive the Boost DC-DC converter steady-state model.

Steady-state analysis was composed of: (a) M (D) expression derivation, (b) ∆iL and ∆vC analysis,

(c) losses effect analysis and η expression derivation, and (d) conditions analysis of CCM and DCM.

From expression of M (D), it was possible to find the maximum Boost DC-DC converter conversion

ratio in function of losses. An important conclusion from this result was that converter has a restricted

conversion ratio, which depends not only on losses, but also on both load and D

. ∆iL

and ∆vC

analysis

allowed to find lower boundaries to select L and C values to design the converter such that maximum

ripples can be guaranteed. Losses effect analysis allowed to obtain an expression to the system efficiency

in function of losses. From this expression, it was possible to conclude that the efficiency converter


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depends not only on losses, but also on both load and D. Moreover, it was concluded that the Boost

DC-DC convert never reaches an efficiency equal to 100%. Finally, conditions analysis of CCM and

DCM allowed to find boundaries such that the Boost DC-DC converter can be designed to operate in

CCM or DCM.Main features of dynamical modeling and steady-state analysis were: (a) developed dynamical model

allowed to represent both high and low frequency converter dynamics and allowed to carry out the

non-ideal Boost DC-DC converter steady-state analysis, which allowed to derive the expression of M (D)

that showed the converter conversion ratio limitations; (b) from the converter steady-state model, it was

possible to construct a suitable circuital converter representation that depicted the relations between DC

voltages and currents, which allowed to derive an Boost DC-DC converter efficiency expression that

showed the converter efficiency limits.

Based on non-linear dynamical model and steady-state analysis, it was possible to design a Boost

DC-DC converter such that a set of operating requirements are achieved in the entire operating range,even if bounded disturbances appear.

Finally, CMC structure was implemented for the designed Boost DC-DC converter. PI controllers

were tuning by means of root-locus controller design method. Finally, designed Boost DC-DC converter

was implemented in PSIM and system operating requirements were verified.

Acknowledgments

Authors wish to thank the support offered by the “Estrategia de sostenibilidad 2014 − 2015" and the

“Beca Estudiante Instructor" of Universidad de Antioquia (Colombia).

Author Contributions

Jorge H. Urrea-Quintero carried out most of the work presented here, Nicolás Muñoz-Galeano was

the advisor of this work, and Lina M. Gómez had a relevant contribution with her extensive knowledge

about systems theory.

Conflicts of Interest

The authors declare no conflict of interest.

References

1. Yousefzadeh, V.; Wang, N.; Popovic, Z.; Maksimovic, D. A digitally controlled DC/DC converter

for an RF power amplifier. Power Electronics, IEEE Transactions on 2006, 21, 164–172.

2. Naayagi, R.; Forsyth, A. Bidirectional DC-DC converter for aircraft electric energy storage

systems. Power Electronics, Machines and Drives (PEMD 2010), 5th IET International

Conference on, 2010, pp. 1–6.

3. Naayagi, R.; Forsyth, A.; Shuttleworth, R. High-Power Bidirectional DC-DC Converter forAerospace Applications. Power Electronics, IEEE Transactions on 2012, 27 , 4366–4379.


27/30


4. Chiu, H.J.; Lin, L.W. A bidirectional DC-DC converter for fuel cell electric vehicle driving

system. Power Electronics, IEEE Transactions on 2006, 21, 950–958.

5. Sharma, R.; Gao, H. Low cost high efficiency DC-DC converter for fuel cell powered auxiliary

power unit of a heavy vehicle. Power Electronics, IEEE Transactions on 2006, 21, 587–591.6. Camara, M.; Gualous, H.; Gustin, F.; Berthon, A.; Dakyo, B. DC/DC Converter Design for

Supercapacitor and Battery Power Management in Hybrid Vehicle Applications - Polynomial

Control Strategy. Industrial Electronics, IEEE Transactions on 2010, 57 , 587–597.

7. de Souza Oliveira, D., J.; Barbi, I. A three-phase ZVS PWM DC/DC converter with asymmetrical

duty cycle for high power applications. Power Electronics, IEEE Transactions on 2005,

20, 370–377.

8. Oliveira, D.; Barbi, I. A three-phase ZVS PWM DC/DC converter with asymmetrical duty

cycle associated with a three-phase version of the hybridge rectifier. Power Electronics, IEEE

Transactions on 2005, 20, 354–360.9. Liang, Z.; Guo, R.; Li, J.; Huang, A. A High-Efficiency PV Module-Integrated DC/DC Converter

for PV Energy Harvest in FREEDM Systems. Power Electronics, IEEE Transactions on 2011,

26 , 897–909.

10. Wang, Z.; Li, H. An Integrated Three-Port Bidirectional DC-DC Converter for PV Application

on a DC Distribution System. Power Electronics, IEEE Transactions on 2013, 28 , 4612–4624.

11. Vlad, C.; Rodriguez-Ayerbe, P.; Godoy, E.; Lefranc, P. Advanced control laws of DC-DC

converters based on piecewise affine modelling. Application to a stepdown converter. Power

Electronics, IET 2014, 7 , 1482–1498.

12. Liu, J.; Hu, J.; Xu, L. Dynamic Modeling and Analysis of Z Source Converter – Derivation of

AC Small Signal Model and Design-Oriented Analysis. Power Electronics, IEEE Transactions

on 2007, 22, 1786–1796.

13. Arango, E.; Ramos-Paja, C.A.; Calvente, J.; Giral, R.; Serna, S. Asymmetrical Interleaved

DC/DC Switching Converters for Photovoltaic and Fuel Cell ApplicationsŮPart 1: Circuit

Generation, Analysis and Design. Energies 2012, 5, 4590.

14. Arango, E.; Ramos-Paja, C.A.; Calvente, J.; Giral, R.; Serna-Garces, S.I. Asymmetrical

Interleaved DC/DC Switching Converters for Photovoltaic and Fuel Cell ApplicationsŮPart 2:

Control-Oriented Models. Energies 2013, 6 , 5570.15. Chiniforoosh, S.; Jatskevich, J.; Yazdani, A.; Sood, V.; Dinavahi, V.; Martinez, J.; Ramirez, A.

Definitions and Applications of Dynamic Average Models for Analysis of Power Systems. Power

Delivery, IEEE Transactions on 2010, 25, 2655–2669.

16. Liang, T.; Tseng, K. Analysis of integrated boost-flyback step-up converter. Electric Power

Applications, IEE Proceedings - 2005, 152, 217–225.

17. Davoudi, A.; Jatskevich, J.; De Rybel, T. Numerical state-space average-value modeling of PWM

DC-DC converters operating in DCM and CCM. Power Electronics, IEEE Transactions on 2006,

21, 1003–1012.

18. Wai, R.J.; Shih, L.C. Design of Voltage Tracking Control for DC-DC Boost Converter Via Total

Sliding-Mode Technique. Industrial Electronics, IEEE Transactions on 2011, 58 , 2502–2511.


28/30


19. Galigekere, V.; Kazimierczuk, M. Analysis of PWM Z-Source DC-DC Converter in CCM for

Steady State. Circuits and Systems I: Regular Papers, IEEE Transactions on 2012, 59, 854–863.

20. Thao, N.; Thang, T.; Ganeshkumar, P.; Park, J.H. Steady-state analysis of the boost converter for

renewable energy systems. Power Electronics and Motion Control Conference (IPEMC), 20127th International, 2012, Vol. 1, pp. 158–162.

21. Hu, G.Y.; Li, X.; Luan, B.Y. A Generalized Approach for the Steady-State Analysis of

Dual-Bridge Resonant Converters. Energies 2014, 7 , 7915.

22. Davoudi, A.; Jatskevich, J.; Chapman, P.; Bidram, A. Multi-Resolution Modeling of Power

Electronics Circuits Using Model-Order Reduction Techniques. Circuits and Systems I: Regular

Papers, IEEE Transactions on 2013, 60, 810–823.

23. Beldjajev, V.; Roasto, I. Efficiency and Voltage Characteristics of the Bi-Directional Current

Doubler Rectifier. Przegl ąd Elektrotechniczny 2012, 88 , 124–129.

24. Mazumder, S.; Nayfeh, A.; Boroyevich, D. Theoretical and experimental investigation of thefast- and slow-scale instabilities of a DC-DC converter. Power Electronics, IEEE Transactions

on 2001, 16 , 201–216.

25. El Aroudi, A.; Giaouris, D.; Ho-Ching Iu, H.; Hiskens, I. A Review on Stability Analysis

Methods for Switching Mode Power Converters. Emerging and Selected Topics in Circuits and

Systems, IEEE Journal on 2015, 5, 302–315.

26. Geyer, T.; Papafotiou, G.; Frasca, R.; Morari, M. Constrained Optimal Control of the Step-Down

DC-DC Converter. Power Electronics, IEEE Transactions on 2008, 23, 2454–2464.

27. Mariethoz, S.; Almer, S.; Baja, M.; Beccuti, A.; Patino, D.; Wernrud, A.; Buisson, J.; Cormerais,

H.; Geyer, T.; Fujioka, H.; Jonsson, U.; Kao, C.Y.; Morari, M.; Papafotiou, G.; Rantzer, A.;

Riedinger, P. Comparison of Hybrid Control Techniques for Buck and Boost DC-DC Converters.

Control Systems Technology, IEEE Transactions on 2010, 18 , 1126–1145.

28. Luo, F.L.; Ye, H. Small Signal Analysis of Energy Factor and Mathematical Modeling for Power

DC ndash;DC Converters. Power Electronics, IEEE Transactions on 2007, 22, 69–79.

29. Wu, X.; Xiao, G.; Lu, Y.; Chen, F.; Lu, D. Discrete-time modeling and stability analysis of

grid-connected inverter based on equivalent circuit. Applied Power Electronics Conference and

Exposition (APEC), 2015 IEEE, 2015, pp. 1222–1226.

30. Mahery, H.M.; Babaei, E. Mathematical modeling of buck ˝ Uboost dc

˝ Udc converter and

investigation of converter elements on transient and steady state responses. International Journal

of Electrical Power & Energy Systems 2013, 44, 949 – 963.

31. Davoudi, A.; Jatskevich, J. Parasitics Realization in State-Space Average-Value Modeling of

PWM DC-DC Converters Using an Equal Area Method. Circuits and Systems I: Regular Papers,

IEEE Transactions on 2007, 54, 1960–1967.

32. Qiu, Y.; Chen, X.; Zhong, C.; Qi, C. Uniform Models of PWM DC-DC Converters

for Discontinuous Conduction Mode Considering Parasitics. Industrial Electronics, IEEE

Transactions on 2014, 61, 6071–6080.

33. Chan, C.Y. A Nonlinear Control for DC-DC Power Converters. Power Electronics, IEEE

Transactions on 2007, 22, 216–222.


29/30


34. Urtasun, A.; Sanchis, P.; Marroyo, L. Adaptive Voltage Control of the DC/DC Boost Stage in

PV Converters With Small Input Capacitor. Power Electronics, IEEE Transactions on 2013,

28 , 5038–5048.

35. Roshan, Y.; Moallem, M. Control of Nonminimum Phase Load Current in a Boost ConverterUsing Output Redefinition. Power Electronics, IEEE Transactions on 2014, 29, 5054–5062.

36. Trejos, A.; Gonzalez, D.; Ramos-Paja, C.A. Modeling of Step-up Grid-Connected Photovoltaic

Systems for Control Purposes. Energies 2012, 5, 1900.

37. Kapat, S.; Krein, P. Formulation of PID Control for DC-DC Converters Based on Capacitor

Current: A Geometric Context. Power Electronics, IEEE Transactions on 2012, 27 , 1424–1432.

38. Kabalo, M.; Paire, D.; Blunier, B.; Bouquain, D.; Godoy Simões, M.; Miraoui, A. Experimental

evaluation of four-phase floating interleaved boost converter design and control for fuel cell

applications. Power Electronics, IET 2013, 6 , 215–226.

39. Mapurunga Caracas, J.; De Carvalho Farias, G.; Moreira Teixeira, L.; De Souza Ribeiro,L. Implementation of a High-Efficiency, High-Lifetime, and Low-Cost Converter for an

Autonomous Photovoltaic Water Pumping System. Industry Applications, IEEE Transactions

on 2014, 50, 631–641.

40. Evzelman, M.; Ben-Yaakov, S. Simulation of Hybrid Converters by Average Models. Industry

Applications, IEEE Transactions on 2014, 50, 1106–1113.

41. Gezgin, C.; Heck, B.S.; Bass, R.M. Integrated design of power stage and controller for switching

power supplies. Computers in Power Electronics, 1996., IEEE Workshop on, 1996, pp. 36–44.

42. Pomar, M.; Gutierrez, G.; de Prada Moraga, C.; Normey Rico, J. Integrated design and control

applied to a buck boost converter. Control Conference (ECC), 2007 European, 2007, pp.

948–954.

43. Mariethoz, S.; Almer, S.; Morari, M. Integrated control and circuit design; an optimization

approach applied to the buck converter. American Control Conference (ACC), 2010, 2010, pp.

3305–3310.

44. Erickson, R.W.; Maksimovic, D. Fundamentals of power electronics; Springer Science &

Business Media, 2007.

45. Hoagg, J.; Bernstein, D. Nonminimum-phase zeros - much to do about nothing - classical control

- revisited part II. Control Systems, IEEE 2007, 27 , 45–57.46. Aguiar, A.; Hespanha, J.; Kokotovic, P. Path-following for nonminimum phase systems removes

performance limitations. Automatic Control, IEEE Transactions on 2005, 50, 234–239.

47. Su, W.; Qiu, L.; Chen, J. Fundamental performance limitations in tracking sinusoidal signals.

Automatic Control, IEEE Transactions on 2003, 48 , 1371–1380.

48. Alvarez-Ramirez, J.; Espinosa-Pérez, G.; Noriega-Pineda, D. Current-mode control of DC-DC

power converters: a backstepping approach. International Journal of Robust and Nonlinear

Control 2003, 13, 421–442.

49. Qiu, Y.; Liu, H.; Chen, X. Digital Average Current-Mode Control of PWM DC-DC Converters

Without Current Sensors. Industrial Electronics, IEEE Transactions on 2010, 57 , 1670–1677.

50. El Aroudi, A.; Alarcon, E.; Rodriguez, E.; Leyva, R.; Villar, G.; Guinjoan, F.; Poveda, A.

Ripple Based Index for Predicting Fast-Scale Instability of DC-DC Converters in CCM and


30/30


DCM. Industrial Technology, 2006. ICIT 2006. IEEE International Conference on, 2006, pp.

1949–1953.

51. Ping, L.; Xin, M.; Bo, Z.; Zhao-ji, L. Analysis of the Stability and Ripple of PSM Converter in

DCM by EB Model. Communications, Circuits and Systems, 2007. ICCCAS 2007. InternationalConference on, 2007, pp. 1240–1243.

52. Liu, S.L.; Liu, J.; Mao, H.; qing Zhang, Y. Analysis of Operating Modes and Output

VoltageRipple of Boost DC - DC Convertersand Its Design Considerations. Power Electronics,

IEEE Transactions on 2008, 23, 1813–1821.

53. Chen, Z.; Gao, W.; Hu, J.; Ye, X. Closed-Loop Analysis and Cascade Control of a Nonminimum

Phase Boost Converter. Power Electronics, IEEE Transactions on 2011, 26 , 1237–1252.

54. Louganski, K.; Lai, J.S. Current Phase Lead Compensation in Single-Phase PFC Boost

Converters With a Reduced Switching Frequency to Line Frequency Ratio. Power Electronics,

IEEE Transactions on 2007, 22, 113–119.55. Vilanova, R.; Alfaro, V.M. Control {PID} robusto: Una visión panorámica. Revista

Iberoamericana de Automática e Informática Industrial {RIAI} 2011, 8 , 141 – 158.

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