Boundary Scan and Board Assisted-BIST

Boundary Scan/ BIST 1

Boundary Scan and Board Assisted-BIST

Long and Short Term Solutions for Test Point Erosion

Steve Butkovich Zoe Conroy - Cisco Systems Inc. Phil Geiger - Dell Computer

Contributing Companies Cisco Systems, Inc. Dell Hewlett Packard Huawei Alcatel EMC Intel Delphi

Agilent Teradyne Test Research Goepel Corelis Asset-Intertech IBM Infineon Fujitsu


The Test Process

PASTE PASTE

INSPECTION Placement Reflow Pre-Reflow AOI AOI

Assembly

AXI MDA

ICT

Flying Probe

Boundary Scan

Structural Test

Functional Thermal Margining

System Functional

Environment Stress Screen

Parametric / Calibration

Functional Test

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Introduction

• Structural connectivity test of devices on printed circuit boards is becoming increasingly difficult as technology advances •  Loss of standard test point access due to circuit density and signal integrity

concerns •  Minimum Operating Speed may exceed capability of test equipment or

methods •  No “test mode” designed into many devices to allow easy, straightforward

development of tests •  The loss of test capability is particularly critical when dealing with

memory devices


Portable

Network / Communication

Automotive

Consumer

Medical

Enterprise Service Provider

Entertainment Safety

Mobile

Office Systems Desktop Mobile High End Server

Imaging

Implantable Monitoring

Test Point Access vs. Time * 2011 iNEMI Test Technology Roadmap


Introduction

The void to fill • Contribution of Structural Test •  Precise diagnostic information for assembly defects

•  Far More Expensive with Functional Test

•  Ability to sense conditions that might damage product before power is applied

•  Ability to detect faults that might not prevent circuit function, but would affect the product reliability or performance

•  Rapid detection and diagnosis which can allow Closed Loop Corrective Action (CLCA) to be applied to an assembly process


Introduction

• Project Teams were formed within iNEMI –  Evaluate

•  current and upcoming boundary-scan related test methods

•  current and upcoming DFT technology solutions

–  Pros, cons, limitations

–  Determine current and future Best Practices using combinations of test methods and DFT technologies

–  Increase industry awareness of the following:

•  Boundary Scan Methods and Availability in Devices

•  Work with Standards Organizations in providing a standard method of controlling and use of boundary scan and Built in Self Test (BIST)

•  DFT technologies


Overview of Test Methods and Strategies

•  ICT - Full net access

•  ICT Integrated Boundary-scan

• Powered Opens at ICT

• Stand-alone Boundary-scan

• Processor Controlled Test

• Board Level BIST

–  FPGA Driven BIST

•  IEEE 1149.1Standard

•  IEEE 1149.6 Standard

•  IEEE 1581 – 2011 Standard

•  IEEE 1149.8.1- 2012 Standard

•  IEEE P1687 Standard under Development

•  Embedded capacitive sense plate (ECSP)

Test Methods DFT Strategies Methods/Strategies fall into two categories


Test Methods and Strategies

ICT – full access to the circuit • “Traditional” method of test – our baseline for test coverage • Timing requirements significantly limits test coverage for many current devices and future devices

ICT Integrated Boundary-scan • Software for ICT systems that uses ICT pin electronics to perform IEEE 1149.x boundary-scan testing of scan chains • Test speed limited by ICT pin electronics


Test Methods and Strategies IEEE 1581 – 2011 Standard

•  Method for static interconnect testing of memory devices •  IEEE 1581 test mode bypasses the functional memory core and

places combinatorial logic between the device inputs and outputs

IEEE 1581 Device

Memory Cells

Combinational Test Logic

Memory Controller

Test control Transparent Test Mode (optional)

Control Device

- IEEE

1149.1 Compliant

Input Bus

Output Bus

x

y XOR


Test Methods and Strategies Powered Opens

•  Used on ICT systems supporting powered opens techniques •  Combines capacitive opens techniques and boundary scan


Test Methods and Strategies Embedded capacitive sense plate (ECSP)

• Used with capacitive opens test methods • Build the capacitive opens sense plate into the IC package

Fill metal (black) is added for thermal connectivity and mechanical coplanarity. •  Electrically floating •  Has small capacitance to IC signal

nets

Figures adapted from US Patent Application Publication US2005/0253616 A1, Nov 2005. (This is a publication; the technology is not patented.)

Connect fill metal areas that couple to DUT signals. Bring a connection point to a surface area for our conventional sense plate to couple with.


Test Methods and Strategies Processor Controlled Test (PCT)

•  Access and control on-board CPU through the debug port •  At-speed testing of anything the processor can reach

–  Access to devices is made by conventional functional means through the processor •  Specific DFT in memory devices is not strictly required

–  They would be implemented at stand-alone boundary-scan, which precedes PCT in the test process

•  PCT can be a powerful tool to test memory –  Provides memory test rather than simply PCA assembly test

JTAG/PCT Module

To TAP


DFT Technologies Alignment with Test Methods


Boundary Scan Use Model

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Assembly

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Flying Probe

Boundary Scan

Structural Test


System Functional



Functional Test

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IEEE 1149.1, 1149.6, 1149.8.1, 1581 Standards


Board Assisted BIST

* International Electronics Manufacturing Initiative ** Integrated Circuit Built In Self Test

Problem: 2009 iNEMI* Roadmap determined risk from manufacturing test-point elimination due to higher speeds and shrinking form factors

Solution: Can IC BIST* be used at Board level test to address this? • No standard chip level interfaces or algorithms,

  Limits the introduction of BIST at board level test,

• Most “chip” level BISTs are designed for IC manufacturing, • Tests and algorithms are often not optimized to run at board test.

Project team investigating: •  What is current adoption of IC BIST at board test? •  Which BISTs would be the most useful at board test? •  How can these be optimized or standardized?


Board Assisted BIST Definition

Board-Assistance BIST is an embedded capability within an IC that is fully or partially self-contained, in that it incorporates some or all of the following

capabilities:

•  pattern/signal generation, •  pattern/signal delivery, •  response or data capture, •  response evaluation functions.


Goals of Board Assisted BIST

• Goals: –  Develop and promote the adoption of IC BIST at the board/system

level –  Steer IC providers toward BIST functions helpful for board/system

level test –  Provide board level standardization requirements for BIST interfaces

and algorithms –  Encourage IC vendors and ATE/Instrument providers to provide

standard products and tools based on these standards for BIST design.


• Many IC BIST tests are available and run at board level –  60% Board designers are requesting access to IC BIST

• Most needed Board Assist-BIST functions are: –  To test external memories –  BIST Pattern generators to drive data off chip –  HSIO-BIST to provide pattern to/through the PHY of a chip

• Access is predominantly via IEEE1149.1 TAP • Majority of BIST tests are proprietary

–  Potential roadblock to wider adoption and implementation

• BIST run at the board level is good at catching defects • Main areas of use: manufacturing board test, NPI, board debug and

diagnosis

Survey Key Takeaways


• However, some issues encountered: –  Some ICs do not support BIST function,

–  IC suppliers often do not give BIST function to board users,

–  Lack of access when IC is mounted on the board,

–  BIST function at board test not supported by a standard.

•  Looking to the future: –  Seen to be critical for future fault isolation,

–  Would like BIST coverage to be > 80% at board test –  > 75% respondents see BIST coupled with boundary-scan replacing lack

of test point access.

–  > 50% respondents plan to adopt or are actively considering adopting current IEEE standards.

Survey Key Takeaways


Test Methods and Strategies IEEE P1687 (IJTAG – Internal JTAG)

–  Defines a methodology for access to embedded test, debug, and configuration features (“instruments”) within an IC via the IEEE 1149.1 Test Access Port.

–  IEEE P1687 components: •  Scan-path network architecture

–  A hardware definition of network architectures and interface methods to provide access to the instruments

•  Architecture Description –  Instrument Connectivity Language (ICL) is a description language for the

characteristics of the instruments and the description of the access network (JTAG-like TDR Scan-Paths)

•  Procedure-Vector Description –  Procedural Description Language (PDL) is a protocol language for

communicating with the instruments and for enabling the instruments to be portable


Board Assisted BIST - Use Case 1

•  BA-BIST function for Board Test support built into IC’s to drive/capture the HSIO connections on the source chip to enable verification of the lanes and chip logic.

•  Features to be supported: loopback connection; pattern generation; error insertion; response evaluation; BER; and PHY adjustment.

•  connection of the BA-BIST function to chip pins allows Board Test Control, Configuration, and Access using a P1687 Embedded Instrument Interface, described by ICL and PDL, connected to a compliant JTAG TAP.


Board Assisted BIST – Use Case 2

•  BA-BIST function for Board Test support built into IC’s to drive/capture on source chip to enable verification of the IC to memory connections.

•  (IC can be an FPGA, ASIC or processor). •  Features to be supported: memory pattern generation; memory address generation;

response evaluation (comparator). •  Again, connection of BA-BIST function to chip pins allows Board Test Control, Configuration,

and Access using P1687 Embedded Instrument Interface, described by ICL and PDL, connected through a compliant JTAG TAP.


Built In Self Test

PASTE PASTE


Assembly

AXI MDA

ICT

Flying Probe

Boundary Scan

Structural Test


System Functional



Functional Test

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Conclusion and Summary • Technology Advancements in Device Density and Signal

Speed will Challenge Traditional Board Test –  Change will be evolutionary with some inflection points

•  High Speed Signals –  >3 GHz

•  High Density Packages – Will reduce the value of traditional assembly tests

• Design for Test (DFT) standards continue to be developed to address these issues –  Versions of these methods already exist to test semiconductors – What changes are interface access and test targets for BIST – Methods will preserve test

•  Cost could be increased test development skill •  New test equipment


QUESTIONS


REFERENCE SLIDES


Test Methods and Strategies ICT Integrated Boundary-scan

•  Software for ICT systems that uses ICT pin electronics to perform IEEE 1149.x boundary-scan testing of scan chains •  Test speed limited by ICT pin electronics

PROS •  Tools are well-known and

supported by industry •  Very good automation of test

development •  Good detection of shorts/opens

CONS •  Test must be designed to emulate

memory cycles through Boundary Scan –  Device Setup times and minimum operating

speeds may not be attainable •  Limited diagnostic isolation of

shorts/opens •  Limited diagnostic resolution

–  Can get down to lanes, but perhaps not net/pin level


Test Methods and Strategies IEEE 1581 – 2011 Standard

JEDEC Scan PROS

•  Turns memory devices into simple, low speed, MSI combinatorial devices –  2n+2 (n = # inputs) patterns per

device in the array to fully test interconnect defects.

•  Works well with IEEE 1149.1 •  Fault diagnosis is down to the

device pin level •  Good detection and isolation of

shorts nets/opens device pins •  Uses simple, inexpensive test logic •  Can be engineered to require zero

new pins •  Supports some level of test

automation

CONS •  Could have different

implementations on the same chip type from different vendors –  Mitigate that by getting JEDEC to

spec IEEE 1581 implementation •  Recently adopted (2011), not much

industry support now –  Projected implementation timeframe

2013-15 •  Input shorted to output could cause

an oscillation state •  No BSDL equivalent language

available for automatic test generation –  Minor issue

•  Requires IC fab process compatibility of logic and memory


Evaluation of Potential Test Solutions Stand-alone Boundary-scan with IEEE P1687

CONS

•  No IEEE P1687 supported devices exist – will not be practical for several years.

•  Very dependent on the board test capability of the IC instrument

•  Limited diagnostics on shorts and opens (test is similar to functional test)

PROS

•  IEEE P1687 will integrate very well into the stand-alone boundary-scan environment

•  “At Speed” test of memory •  More comprehensive test than only

structural test


Test Methods and Strategies Embedded capacitive sense plate (ECSP)

PROS •  Engineered into IC package, not

silicon

•  Passive analog technique

•  Can be engineered to avoid capacitive sense difficulties of heat sinks, internal ground planes and lack of lead frames

•  Capacitive sensing is widely used in board manufacturing community

•  Dovetails with newly minted IEEE 1149.8.1 technology or IEEE 1149.1 in memory controller

CONS •  Very new

•  Some development research needed

•  Needs to be in package specifications

•  Requires production tester with appropriate fixturing and capacitive sense capability

Documents

Boundary Scan and Board Assisted-BIST