Buck_converters for portable application

1

Magnetic Buck Converters for Portable Applications

Frank De StasiMathew Jacob

2

© 2003 National Semiconductor Corporation

Outline

1. Why use Switching Regulators?2. Common Device/Converter Specifications3. Buck Converter Analysis 4. CCM/DCM modes5. Selection of L and C6. Synchronous Buck Converters7. Conduction and Switching Losses8. Efficiency improvement using PWM/PFM/LDO modes9. Control Approaches10. Current Mode Models and Compensation Guidelines11. Transient Measurement Techniques12. Layout Guidelines

3


Efficiency

+–

µP/DSPcore

Powersupply

Vg

+

Vo

_

Ig Io

gg

oo

g

o

IVIV

PP

===power DCinput power DCoutput

η

4


Linear voltage regulator as power supply

+– C

+

Vo

–

Vg

Iload

Vref

+

-

QSeries pass transistor

Load

Bandgap reference

• Simple, low noise, small footprint area• Output voltage lower than the battery voltage• High efficiency only if Vo is close to Vg

5


Linear regulator power model

Qog III +=

)(?

Qog

oo

gg

oo

IIVIV

IVIV

+==

Bias current

Efficiency:

g

o

VV

<?Linear regulator efficiency cannot be greater than the ratio of the output and the input voltage

+–

Rs

+

Vo

–

Vg

Io

IQ

Ig

6


SMPS efficiency as a function of load

0

10

20

30

40

50

60

70

80

90

100

0.1 1 10 100 1000

Io [mA]

Eff

icie

ncy

[%]

..

Example:• Vg = 3.6 V• Vo = 1.5 V• 0 < Io < 300 mA

Linear regulator

Buck regulator

7


Buck (step-down) switching power converter

Low-pass LC filter

fs = 1/Ts = switching frequency

D = switch duty cycle

+–

L

C

+

v(t)

–

1

2

+

vs(t)

–

Vg

Ig Io

Load

vs(t) Vg

DTs D' Ts

0

t0 DTs Ts

Switchposition: 1 2 1

8


Buck converter ideal static characteristic

Conversion ratio:

DVV

g

o =

switch duty cycle

Vg

00 D

V

1

vs(t) Vg

0

t0 DTs Ts

area =DTsVg

⟨vs⟩ = DVg

9


Switch-Mode Power Supplies

• Step-up, step-down and inverting configurations available

• Switching converters are ideally 100% efficient• Real efficiency can be close to 100%; depends on

operating conditions and implementation– Losses and efficiency will be discussed

• Converters generate switching noise• Discrete filter components (L, C) are required• Higher switching frequency => smaller L, C

– Component selection will be discussed • Duty cycle is the control variable• Closed-loop output voltage control is usually applied

– Dynamic models and control will be discussed

10


Impact of efficiency: a system example

uP/DSP core mode Stand-by Wait Run1 Run2 FullRun% of time in this mode 90.0 4.0 3.0 2.5 0.5Load current Io [mA] 0.1 1.0 10.0 100.0 300.0

Linear regulator Efficiency [%] 34.7 40.9 41.6 41.7 41.7Battery current Ig [mA] 0.12 1.02 10.02 100.02 300.02Average Ig in this mode [mA] 0.11 0.04 0.30 2.50 1.50

Total linear reg average Ig [mA] 4.45

SMPS Efficiency [%] 29.1 78.4 93.7 93.0 87.7Battery current Ig [mA] 0.14 0.53 4.45 44.82 142.60Average Ig in this mode [mA] 0.13 0.02 0.13 1.12 0.71

Total SMPS average Ig [mA] 2.12

Example:• Vg = 3.6 V• Vo = 1.5 V• 0 < Io < 300 mA

11


Advantages of using SMPS over Linear regulators

• SMPS results in significantly lower average battery current

• High efficiency over a wide range of loads and output voltages is achieved with a SMPS

• SMPS with low quiescent current modes provide longer battery life for mobile systems that spend most of their time in “stand-by”

12


Buck regulators in the system

µP/DSP core

Antenna

I/OAudio

Interface

A/D

D/ALO

Baseband digital Analog/RF

PA

LNA

Display

PS PS PS PS

PS

PS PS PS

Battery ChargerPower distribution: Vg = 2.8-5.5 V

1.5 V 1-3.6 V

2.5 V 2.5 V 2.5 V

2.5 V

2.7-5.5 V

3.6 V

Buck SMPS regulators

Buck regulators are often used as switch-mode power supplies for baseband digital core and the RF power amplifier (PA)

13


Device/Converter Specifications

• Static voltage regulation– DC output voltage precision, i.e., % variation with

respect to the nominal value over:• input voltage range (“line regulation”)• output load range (“load regulation”)• temperature

• Dynamic voltage regulation– “Load transient response,” including peak output

voltage variation and settling time for a step load transient

– “Line transient response,” including output voltage variation and settling time for a step input voltage transient

14



• Overvoltage protection– prevents the output voltage from rising above a

specified limit• Undervoltage shutdown

– turns the device off if the input (battery) voltage drops below a specified threshold

• Current limiting (overload protection)– limits the load current

• Thermal shutdown– turns the device off if the temperature exceeds a

specified threshold

15



• Frequency synchronization– allows synchronization of the switching

frequency to an external system clock• Soft start

– controlled output voltage increase during start-up

• Shut-down and operating-mode control– enables a system controller to shut-down the

device, or to select an operating mode(PWM,PFM,LDO)

• Adjustment of the output voltage using– a resistive voltage divider,– external analog control voltage, or– digital (pin-select) control

16


Buck converter analysis

+–

L

C R

+

v(t)

–

1

2

iL(t)

+ vL(t) – iC(t)

Vg

L

C R

+

v(t)

–

iL(t)

+ vL(t) – iC(t)

+–Vg

L

C R

+

v(t)

–

iL(t)

+ vL(t) – iC(t)

+–Vg

Switch in position 1 Switch in position 2

17


Switch in position 1L

C R

+

v(t)

–

iL(t)

+ vL(t) – iC(t)

+–Vg

)(tvVv gL −=

Inductor voltage:

Small-ripple approximation:

Knowing the voltage, we can solve for the current from:

Solve for the slope:

Therefore, the inductor current increases in time with an essentially constant slope.

VVv gL −≈

dtdi

Lv LL =

L

VV

Lv

dtdi gLL

−≈=

18


Switch in position 2

)(tvvL −=

Inductor voltage:

Small-ripple approximation:

Knowing the voltage, we can solve for the current from:

Solve for the slope:

Therefore, the inductor current decreases in time with an essentially constant slope.

VvL −≈

dtdi

Lv LL =

LV

Lv

dtdi LL −≈=

L

C R

+

v(t)

–

iL(t)

+ vL(t) – iC(t)

+–Vg

19


Inductor voltage and current waveforms

iL(t)

t0 DTs Ts

IiL(0)

iL(DTs)∆iL

vL(t) Vg – V

t– V

D'TsDTs

Switchposition: 1 2 1

20


Average voltage across the inductor equals zero

vL(t)Vg – V

t

– V

DTs

Total area λ

The DC output voltage is directly proportional to the input voltage and the switch duty cycle

0))(1()(1

0

=−−+−== ∫ VDVVDdtvT

v g

T

Ls

L

s

gDVV =

21


Average inductor current equals the output current

oLLLC ItiRV

tiRtv

titi −=−≈−= )()()(

)()(

01

0

=−== ∫ oL

T

Cs

C IidtiT

is

oL Ii =

In steady state, the average inductor current equals the load current

We know that the average capacitor current equals zero

+–

L

C R

+

v(t)

–

1

2

iL(t)

+ vL(t) – iC(t)

Vg

IO

22


Light-load operation: CCM and DCM

t

)(tiL

oIhigh

oI low

Inductor current reverses polarity at light loads

t

)(tiL

oIhigh

oI low

Inductor current drops to zero before the end of the cycle: “Discontinuous conduction mode” (DCM)

withoutzero crossdetect

withzero crossdetect

23


Implementing Zero-cross detect

• With the zero-crossing comparator the switch S2 operates as a diode, resulting in DCM and improved efficiency at light loads

• All switchers in the LM26XX family have this feature

+–

L

C

+

v(t)

–

iL(t)

+ vL(t) – iC(t)

Vg

Io

S2

S2controllogic

S1

S2

S2 is turnedOFF

24


CCM vs. DCM

• In DCM, the inductor current is always positive• At light loads, in DCM, the duty cycle is significantly

lower than in CCM• CCM operation at light loads is undesirable because

the reversal of the inductor current polarity contributes to conduction losses, while it does not contribute to the output load current

• With a diode rectifier, DCM operation occurs automatically because of the diode characteristic

• With a synchronous rectifier, DCM operation at light loads can be accomplished by turning off the NMOS switch at the zero-crossing of the inductor current

25


DCM/CCM boundary

• Boundary between constant-frequency CCM and constant-frequency DCM depends on the circuit parameters and the load

• At the CCM/DCM boundary the inductor current ripple equals the output load current:

DCMCCMgs

gLo I

VV

LfVV

iI /2=

−=∆=

• If Io > ICCM/DCM, the buck converter operates in CCM• If Io < ICCM/DCM, the buck converter operates in DCM

26


Static characteristic in DCM

• As the load Io in DCM decreases, the duty cycle Dmust decrease to keep the output V in regulation

• Minimum possible on-time tp,min of the PMOS limits the minimum load current Io,min in constant-frequency PWM mode for which the output stays in regulation: If the output load current is reduced beyond Io,min the output voltage will start to rise and over voltage protection will activate.

g

osg

VILf

D

DVV

22

2

+=

spgg

o ftL

VV

VVI 2

min,min, 2−

=

)( VVgVgIfVL2

Dos

−=

27


Determination of the inductor current ripple magnitude

iL(t)

t0 DTs Ts

IiL(0)

iL(DTs)∆iL

(change in iL) = (slope)x(length of subinterval)s

gL DT

L

VVi

−=∆2

DLf

VVi

s

gL 2

−=∆ D

fi

VVL

sL

g

∆−

=2

Current ripple magnitude Basic inductance selection eq.

28


Output capacitor voltage ripple

iC(t)

vC(t)

t

t

Total chargeq

DTs D'Ts

Ts / 2

V

∆iL

∆v∆v

221 s

LT

iq ∆= )2( vCq ∆=

s

L

Cfi

v4

)2(∆

≈∆

[ ]sesrs

L CfRDCfi

v 8124

)2( +−∆

≈∆

(including esr)

The peak to peak output voltage ripple is the larger of the two values in the equations above.The equations can be used as capacitance selection equations if a target peak to peak output voltage ripple is known.

(neglecting esr)0

29


Practice problem: selection of L and C

• LM2612 is used to generate the output voltage of V = 1.5V at the max. DC output current of Io = 300 mA

• The input voltage is between Vg = 2.8V and Vg = 5.5V• Select L and C so that:

– the worst-case peak current ripple is ∆iL = 120mA, and

– the worst-case peak-to-peak output voltage ripple is 2∆v = 5 mV

30


Inductor selection

• LM2612 datasheet:Switching frequency is between fsmin = 468 kHz and fsmax = 732 kHz

−

∆=

∆−

=∆

−=

gsLgsL

g

sL

g

VV

fiV

VV

fiVV

DfiVV

L 11

222

HV

Vfi

VL

gsL

µ7.911

2 maxmin

=

−

∆≥

A 10µH inductor is chosen in the datasheet

31


Output filter capacitor selection

)2(41

vi

fC L

s ∆∆

=

Fv

if

C L

s

µ8.12)2(4

1 max

min

=∆

∆≥

A 22µF ceramic capacitor is chosen in the datasheet. A 10µF capacitor can also be used with slightly higher output ripple, in case the load transient requirements are not demanding.

32


Input current waveform

+–

L

C R

+

v(t)

–

1

2

iL(t)

+ vL(t) – iC(t)

Vg

)(tig

t

)( ti g

• Input current is pulsating, with large switching-noise component• Input filter (“decoupling”) capacitor is mandatory

• to reduce the input voltage noise and ensure proper operation of the device

• to prevent propagation of the switching noise to other system components

gC

33


Capacitor ripple currents

rI

i2RatioCurrentRipple

O

L =∆=

Os IfLDVoVg

rmin

)( −=

)(12rD1DICapacitorInputIrms

2

O +−=

12rICapacitorOutputIrms O=

H10L µ= V63Vg .= V81Vo .= kHz468fs =min

9620r .=

mA107CapacitorInputIrms =

mA56CapacitorOutputIrms =

4810r .=

mA204CapacitorInputIrms =

mA56CapacitorOutputIrms =

mA200Io = mA400Io =

34


Capacitors :How small can I go ?

Input CapacitorOutput Capacitor

When reducing the value of output capacitors ensure proper gain and phase margins and evaluate line/load transient performance and whether it meets requirements.

35


Switch realization with a synchronous rectifier“Synchronous Buck”

+–

L

C

+

v(t)

–

iL(t)

+ vL(t) – iC(t)

Vg

+

vsw(t)

–

Io

p

n

ip(t)

in(t)

PMOS

NMOS

vp

vn

drivers

PMOS: main switch

NMOS: synchronous rectifier

p

n

td1 td2

“dead” times

Dead times are used to prevent short-circuit currentthrough PMOS/NMOS

Switch control signals

36


Switch currents

)(tip

t

t

)(tin

Switch on-resistance and forward voltage drops result in switch conduction losses

opp DItiI ≈= )(

oprmsp IDtiI ≈= )(2,

onn IDtiI )1()( −≈=

onrmsn IDtiI −≈= 1)(2,

Average and RMS values

37


Conduction-loss models

vp

+

_vSG

body diode

ip(t)

ON OFF

+_vON

ip(t)Ron,p

+ _vON vn +

_

vGS

body diode

in(t)

ON OFF

+_ vON

Ron,n

+_ vON

in(t)

in(t)vON +_

RD

+_ vON

in(t)VD

iL(t)L

iL(t)LRL

+ _vLwindingresistance

ideal

PMOS: On-resistance Ron,pNMOS: On-resistance Ron,n

Diode: Forward voltage drop VD in series with on-resistance RD Winding resistance RL

38


Buck circuit when the PMOS is ON

iL(t)LRL


idealip(t)Ron,p

+ _vON

+–

Io

+

V

_

Vg

VIRRVviRRVv oLpongLLpongL −+−≈−+−= )()( ,,

oL Ii ≈

39


Buck circuit when the NMOS is ON

VIRRviRRv oLnonLLnonL −+−≈−+−= )()( ,,

0=gi

idealiL(t)LRL


Io

+

V

_

+– Vg

Ron,n

40


Steady-state model with conduction losses

0=Lv

oLnonpong IRRDDRDVV ))1(( ,, +−+−=

Inductor volt-second balance:

Input current: ogg DIiI ==

Equivalent steady-state circuit model with conduction losses:DR + (1-D)R + R

+–

+–

DVg

+

V

–

DIoVg

IoIg on,p on,n L

R

)()(,,

,

ponnonog

Lnono

RRIVRRIV

D−+++

=Duty cycle considering losses

41


Switching losses

• Switching losses are proportional to the switching frequency

• Switching loss mechanisms:– Charging/discharging of capacitance at

MOSFET gates and switch node– Inductive switching transitions– Body-diode reverse recovery– Oscillator and other misc. controller losses– Inductor eddy-current and core losses

42


Improving light-load efficiency

• In PWM mode, light-load efficiency is reduced because a significant portion of switching losses does not scale with load

• In PWM mode, the oscillator and the power switches are always switching at high switching frequency

• Low-power modes are based on the idea of reducing the switching frequency in proportion to the load

• If the switching frequency is proportional to load, high efficiency can be maintained over a very wide range of loads

43


Switching frequency in PFM mode

og

peakp VV

LIt

−=

o

peakn V

LIt =

snppeako fttII )(21

+=

−=

g

o

peak

oos V

VLI

IVf 1

22

In PFM, the switching frequency is directly proportional to the load current

tp tnTs

iL

Ipeak

Lo iI =

44


Output voltage ripple in PFM

tp tnTs

iL

Ipeak

Lo iI =

)(2)(

2)2(

2

ogo

gpeaknp

peak

VVV

V

C

LItt

C

Iv

−=+≈∆

The output voltage ripple is typically higher in PFM than in constant-frequency PWM mode

45


PWM/PFM Combination

• High efficiency over very wide range of loads• Low IQ

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0.1 1 10 100 1000Iout in mA

Eff

icie

ncy

LM2618 PFM LM2618 PWM

Vin = 3.6V

46


Discussion of Operating Modes

PWM

LDO PFM

• LDO: linear regulator• Low-noise• Very low IQ• Simple controller

• High efficiency over very wide load range• Very low IQ• Simple controller• Increased output voltage ripple

• Best efficiency at moderate to heavy load• Constant-frequency, low switching noise• Synchronization to external clock possible• Relatively high IQ and poor light-load efficiency

47


PWM/LDO Combination

PWM

LDO PFM

• High efficiency (moderate-to-heavy load)• Low noise:

• Constant-frequency operation• No switching noise at very light loads (LDO)

• Very low IQ

Example: LM2608

48


PWM/PFM Combination

PWM

LDO PFM

• High efficiency over very wide range of loads• Low IQ

Examples: LM2612/LM2614

49


Selection Guide

50


Control approaches in constant-frequency PWM mode

• Voltage-mode control– The switch duty cycle is controlled based on

output voltage sensing

• Current-mode control– The switch duty cycle is controlled based on

output voltage and switch current sensing

51


Voltage-Mode Control Architecture

p n

+–vg(t)

Powerinput Load

Compensator

Gc(s)

VrefVoltage

reference

v

Feedbackconnection

Pulse-widthmodulator

vc

p(t)

TsdTs t t

vc(t)

L

C

+

v(t)

–

iL(t)

+ vL(t) – iC(t)+

vsw(t)

–

Io

Gatedrivers

Dead-time

Controller chip

52


Current-Mode Control Architecture

p n

+–vg(t)

Powerinput Load

Compensator

Gc(s)

VrefVoltage

reference

v

Feedbackconnection

vc

p(t)

TsdTs t t

vc(t)

L

C

+

v(t)

–

iL(t)

+ vL(t) – iC(t)+

vsw(t)

–

Io

Gatedrivers

Dead-time

Controller chip

Current-modemodulator

ip(t)

Rsip(t)

53


Current-mode summary

• Advantages of current-mode control– Simpler, approximately single-pole responses– Inherent rejection of line disturbances– Built-in over-current protection

• LM26XX family is based on current-mode architecture

• LM2608/12/18 feature internal compensation• LM2614/19 require external compensation

54


Important definitions

Cross-over frequency fc is the frequency where the magnitude response of the loop gain drops to 1, i.e. 0 dB

dB 01)( →=cjwT

Phase margin PM is the difference between the phase of the loop gain at the cross-over frequency and -180o

ocjwTphasePM 180)]([ +=

Gain margin GM (in dB) is the negative of the loop-gain magnitude response (in dB) at the frequency fm where the phase of the loop gain equals -180o

[ ] omm jwTphasejwTGM 180)( ,)(log20 −=−=

55


Example of finding phase and gain margins

10. 100. 1000. 10000. 100000.

- 1 5 0

- 1 0 0

- 5 0

0

5 0

1001 10. 100. 1000. 10000.

GM

PM

KHz 10≈cfoPM 71= dB 24=GM

56


Current Mode Power Stage Model

cV

)())//((

)()//(ˆˆ

oo

om

c

o

RL

s1CRRs1

CESRs1RRgVV

⋅+⋅⋅⋅+

⋅⋅+⋅⋅≈

oV

mgoR

L

ESR

C

R

57


Closed Loop Regulator Model

cV

oV

+-

refVoA

pR

3R 4C

mgoR

L

RESR

C

IF: CRRo4C3R ⋅≈⋅ )//(

cFCESR2

1 ≥⋅⋅⋅π

c

o

F

RL

2

1≥

⋅⋅π

4CR2RRgF

p

omc

⋅⋅⋅⋅≈

π//

)()()//(

)()()//(

opo

o

oom

A4CRs1RL

s1CRRs1

4C3Rs1CESRs1ARRgGainLoop

⋅⋅⋅+⋅⋅+⋅⋅⋅+

⋅⋅+⋅⋅⋅+⋅⋅⋅≈

58


Compensation Example

Objective: To compensate a LM2614 to get a stable system

Ω= 10RF10C µ=

Ω= m10ESRH10L µ=

Load resistance

Output capacitor

ESR of output capacitor

Inductor

Ω= 5Ro

mho1gm =

Ω= k33Rp

Ω+= k52R1RRp )//(

Small signal output resistance

Transconductance of power stage

10000Ao = Open loop gain of error amplifier

R1,R2 are external feedback resistor dividers,5 kO is internal

kHz84CRoR2

1poleloadThe .

)//(=

⋅⋅⋅=

π

kHz80L2

RopolefrequencyhighThe =

⋅⋅=

π

)(. ignoretoenoughhighMHz61CESR2

1zeroESRThe =

⋅⋅⋅=

π

59


Compensation Example

We now need to choose the values of R3 and C4 to give a stable regulator response. If we set the zero frequency of R3 and C4 equal to the load pole frequency, and we choose a loop gain crossover frequency, Fc, much lower than the high frequency pole, then we can assume that the loop gain has a first order response. By choosing Fc = 30 kHz, the 80 kHz pole will contribute only 20 degrees of phase lag at Fc. This should give us a phase margin of about 90-tan-1(30/80) = 90-20 = 70 degrees.

This should give a stable regulator. Of course the real circuit should be checked under all conditions to ensure a stable system. This is only one of the methods to stabilize a regulator. Any other small signal methods that apply to feedback systems, will work here as well.

pF680pF536RpFc2RRogm4C ≈=

⋅⋅⋅⋅=

π)//(

Ω≈Ω=⋅= k47k494C

CRRo3R )//(

60


Compensation guidelines

Typically we like to choose a crossover frequency as high as possible. This gives a regulator with a fast transient response. However, if Fc is too close to the high frequency pole, of the power stage, the phase margin will be degraded. If we chose a Fc in the previous example of 75 kHz, then the phase margin would only be 47 degrees. Given the fact that these equations are only approximate, the phase margin of the real circuit will probably be smaller. This will give a “ringy” transient response. Lower crossover frequencies give a slower regulator, but tend to be more stable, and more “on-the-safe-side”.

The size of the output capacitor is also a compromise. Smaller gives more under/over-shoot during a load transient and slightly higher output voltage ripple. However, with regulators that are internally compensated, smaller values of output capacitor will tend to increase Fc and therefore decrease phase margin. Large values of output capacitor will give small under/over-shoot and ripple, but are physically larger. Parts such as the LM2614, with external compensation, are much more flexible with regards to output capacitor value. In any case, it is always best to stay within the range given in the datasheet.

61


Line Transient Measurements

+15V 1000µ F

LM12CL

-15V

DUT

50Ω

0.5µ H (L)

30Ω

50KΩ 50KΩ

220pF(C)

1000µ F

10µF

10µ F

600mV

30µ s

PulseGenerator

Output

Adjust L and C to minimise overshoots

62


Load Transient Measurements

Con

stan

t Loa

d

Pul

se L

oad

DU

T

50Ω

IRF 510 FunctionGenerator

Output

63


Layout guidelines

• Electrical guidelines– component placement and length of traces– width of traces– curling of critical current loops– routing of sensitive traces– ground pins and ground plane– voltage regulator placement on the system

board• Mechanical guidelines

64


Critical current loops in a buck regulator

+–

L

C

+

v(t)

–

1

2

+

vs(t)

–

Vg

Ig Io

Load

The critical current loops carry large currents with significant switching ripples

65


Component placement and length of traces

• The two critical loops carry large switching currents and act as antennas that radiate switching noise

• Place C1, chip, L, and C2 as close as possible, to minimize the area of the two critical current loops

Loop 1Loop 2

66


Routing of sensitive traces

Route noise sensitive traces, such as the voltage feedback path, away from the critical current loops with noisy traces between power components

67


Ground pins and ground plane

Connect the chip ground pins and the filter capacitor ground pins using a large component-side fill

Connect this area to the ground plane using several vias

This approach prevents large switching currents from circulating through the ground plane, and reduces ground bounce to the chip

68


Voltage regulator placement

sensitive analog/RF

Place switching regulator away from sensitive analog/RF subsystems

69


References and Acknowledgements

• R.W.Erickson, D.Maksimovic, Fundamentals of Power Electronics, 2nd Edition, Kluwer Academic Publishers, 2000, ISBN 0-7923-7270-0

• LM26XX Data Sheets, National Semiconductor Corporation– LM2608,LM2612,LM2614,LM2618,LM2619

• Dragan Maksimovic, Associate Professor, ECE Dept, University of Colorado, Boulder, CO

70

Documents

Buck_converters for portable application