Build your own bypass-capacitor tester.pdf

8/10/2019 Build your own bypass-capacitor tester.pdf

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T

he program in Listing 1 uses a pseu-do-RETI instruction to provide a

five-priority-level interrupt systemfor the 8051P microcontroller. The inter-rupt-priority order, from high to low, isINT0 IT0 INT1 IT1 INTP. Before thepseudo-RETI instruction arrives in theIT0 or IT1 interrupt-service routine, theaddress of the first instruction, which isafter the pseudo-RETI instruction, goesback into the stack.The internal, nonad-dressable flip-flop associated with IT0 orIT1 clears to acknowledge a higher inter-rupt after execution of the pseudo-RETIinstruction, while the IT0 or IT1 inter-

rupt-service routine executes continu-ously until the RETI instruction arrives.Hardware circuits can exchange the INT1and INT2 interrupts,and software can setthe IT1 and IT2 interrupts.

You can download Listing 1 from theWeb version of this article at www.ednmag.com.

Software makes full use of 8051’s interrupt systemDeng Yong, Shanghai Jiaotong University, China

LISTING 1—FIVE-PRIORITY-LEVEL INTERRUPT SYSTEM FOR 8051P

Software makes full use

of 8051’s interrupt system..........................111

Improve FET-based gain control ..............112

Circuit improves on bias

for GaAs FETs................................................114

Build your own bypass-

capacitor tester ............................................116

DAC and op amp provide

variable-control voltage..............................118

Logic offers complementary-

switch control................................................120

Circuit measures currents

in dc servo motor ........................................122

Edited by Bill Travis

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One problem with standard FETgain-control circuits isincreased noise when you

use the FET as a part of a resistive at-tenuator in series with an op amp.This configuration attenuates the sig-nal before amplification; hence, it re-quires much higher gain bandwidthand better noise performance from

the op amp.When you substitute theFET for the gain-setting resistor in anoninverting op-amp circuit, distor-tion limits the circuit configuration toapplications in which the input volt-age is less than a few hundred milli-volts. The FET imposes this limita-tion, because the channel-depletionlayer is a function of V

DGand

VGS

. The improved circuit inFigure 1 uses the FETas part of the feed-back loop. The voltage across

the FET is limited in this ap-plication, and the noise per-formance is good. An addedbonus is improved linearity performance. The transferfunction for the improved cir-cuit is as follows (Reference 1):

When R 2R

3R

1and R

4

R DS

(FET drain-source resist-

ance),the transfer function re-duces to G1R

2||R

3/R

DS.

The minimum drain-sourceresistance for the FET on hand,J271, is 76 at V

GS0V. The

actual VDS

at the inception of distortion varies with eachFET, but keeping V

DSlower

than 200 mV usually preventsdistortion.In the design in Fig-ure 1, the FET drain-sourcevoltage is limited to approxi-mately 100 mV to prevent dis-

tortion. The divider action be-

tween R 3

and R DS

creates VDS

from theoutput voltage, according to the fol-lowing equation:

You can calculate R 3 as 24.5 k andselect 24 k . The parallel value of R 2

and R 3

determine the maximum cir-cuit gain.Selecting R

2as 3 k yields R

1

equal to 27 k and a maximum gainof 37. The measured gain atV

CV

GS0V is 36.1, which corre-

lates well with the calculated value.R A

and R B

are feedback resistors thatlinearize the FET’s V

GSversus R

DS

transfer function. You can nor-mally obtain adequate lineariza-tion with equal-value resistors,

but you can also control theslope of the transfer function by setting the resistor ratio. Thegraph in Figure 2 shows that R

A

modifies the transfer functionand linear control-voltage range(V

GS). The p-channel FET, J271,

requires a positive control volt-age, but you can use a negativecontrol voltage with an equiva-lent n-channel FET, such as theJ210. The circuit is versatile andprovides low distortion, wide

range, good linearity, and low cost. The TLC071 op amp haslow input-bias currents and hasprovisions for input offset-volt-age correction.

Reference

1. Mancini, Ron, “Op ampsfor everyone,” Texas Instru-ments, September 2000, pg 3.

TLC071

7V

7V

VOUT

R2

3k

R1

27k

R3

24k

J271RA

100k

RB

100k

VC

VIN

+

F igure 1

Improve FET-based gain controlRon Mancini, Texas Instruments, [email protected]

The drain-source resistance of the FET controls the gain

of the op-amp stage.

10 20 30 40

GAIN

FET-CONTROL

VOLTAGE

(V)

8

7

6

5

4

3

2

1

0

RA=27k

RA=51k

RA=100k

F igure 2

The ratio RA /R

Bin Figure 1 controls the slope of the gain-control

transfer function.

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ednmag.com.

.R 076.0

076.05V1.0

R R

R VV

3

3DS

DSOUTDS

+

=

=

+

=

.R

R

R R R R

GV

V

1

4

3232

IN

OUT

++

==



ideasdesign

It’s important to properly sequencethe bias applied to an RF/mi-crowave GaAs FET or a MMIC

(monolithic-microwave-IC) amplifier.These devices are extremely sensitive todrain and gate voltage levels as well as tothe order in which these biases turn onand off. A GaAs-FET amplifier that usestwo bias voltages—a negative supply,V

GG, on its gate and a positive supply,V

DD,

on its drain—requires that VGG be pres-ent before the application of VDD

. Whenpowering down the amplifier, V

DDmust

go to 0V before VGG

changes from its neg-ative value to 0V. Figure 1 shows a com-monly used disable circuit found in many voltage-regulator data sheets. The circuituses a 2N3904 switching transistor to pullthe ADJ pin to ground to disable the volt-age regulator. The circuit does not set theoutput of the regulator to 0V but insteadsets the output to the regulator’s referencevoltage, 1.25V. The condition in which a

GaAs FET or MMIC has 0V on the gateand 1.25 on the drain can result in dam-age to the device. For example, M/A-Com’s MAAM26100-PI MMIC poweramplifier requires 8V for V

DDand

5V for VGG

. With 1.25V on VDD

and 0V on VGG

, the MMIC draws ap-proximately three times its nominal draincurrent, sufficient to cause destructivefailure. Figure 2 shows an improved cir-cuit for the adjustable regulator.

A medium-power pass transistor, Q2, a

Central Semiconductor CBCP69, con-

nects to the input of the voltage regula-tor to disable the regulated output volt-age. In disabled mode, the voltage at theregulator’s output is 0V. In enabled mode,Q

1saturates and activates a voltage di-

vider comprising R 1

and R 2. Q

2saturates,

and the output swings from 0 to 8V. Be-cause of the propagation delay of thetransistor switching network, the 8V out-put switches from 0 to 8V after the 5Vsupply switches from 0 to 5V. D

1sets

the disable threshold of the5V supply to approximately 4V to minimize the

delay between the5V supply switching

from 5V to 0V and the regulatorswitching from 8V to 0V. To ensure thatV

GGremains at 5V after disabling IC

1,

you can exploit the high FET gate resist-ance and the low-leakage Schottky-diodecharacteristic. The combination of highgate resistance of the GaAs FET, the low-leakage Schottky diode, D

2, and the 10-

F capacitor, C1, provides a high V

GGRC

time constant when the5V supply is off

(in other words, at 0V). The RC time con-stant of the Schottky-diode leakage re-sistance, the FET gate resistance, and C

1

is long compared with the RC time con-stant at V

DD. As well as having low reverse

leakage, D2

has an inherently low (0.1V)forward drop.

+

+

+

LT1085IN OUT

ADJ

3.01k

1k 5V VGG

VDD

V2

V1

Q1

2N39041.62k

301

10 F

10%

35V

10 F

10%

35V

5V

15V

C2

0.1 F

50VIC1

8V

1

3 2

F igure 1

Circuit improves on bias for GaAs FETsTom Roberts, Anritsu Co, Morgan Hill, CA

In disabled mode, this circuit supplies a potentially damaging 1.25V to the drain of a GaAs FET or a

MMIC.

+

+

+

10 F

35V

10%

IC1

LT1085IN OUT

ADJ

V2

VGG

CMOSG2-3

C1

10 F

10V

10%

5V

D2

5V

D1

MBZ5226

3.3V

5%

Q1

2N3904

R2

4.7k

1%

1k

1%

V1

VDD

8V

10 F

35V

10%

301

1%

1.62k1%

R1

1k1%

15V

0.1 F50V5%

Q2

CBCP693 2

1

F igure 2

This circuit provides safe power-up and power-down sequencing for sensitive GaAs FETs and

MMICs.

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Most circuits use bypass capaci-tors and can deliver substandardperformance if the capacitors have

poor pulse characteristics. Few if any ar-ticles cover how to test bypass capacitorsfor pulse characteristics. The circuit inFigure 1 tests these characteristics. Itcharges the capacitor under test through100 k for approximately 1 msec andthen discharges it through 10 for ap-proximately 40 nsec. The cycle then re-peats. The circuit uses a double-sided

copper-clad pc board. All the compo-nents except the 10 resistor connect toone side of the board, so they can bene-fit from shielding by the cast-aluminumenclosure (Figure 2).All leads are as shortas possible and as close as possible to thecopper-clad board. The layout is suchthat you don’t need the oscilloscopeprobe’s ground lead; the ground on theprobe contacts a ground post on the pcboard. The ground posts, feedthroughs,connections to the capacitor under test,and oscilloscope probes use vector-board

terminals.The circuit comprises an astable mul-

tivibrator using two 2N3904 transistors,

Q1

and Q2, and associated components.

A voltage reducer/shaper uses a trimmercapacitor, C

1; a 100-pF capacitor, C

2;and

a 200 resistor, R 1. An amplifier uses a

2N3906 transistor, Q3, and associated

components, and a power amplifier usesa PN2222A transistor, Q

4, and associat-

ed components.C1, C

2, and R

1produce a

fast rise- and fall-time, 0.7V pulse whenthe multivibrator’s output switches neg-ative. Because the Q

3transistor has no

bias, it conducts only at the peak of the

input pulse and produces a pulse withfast rise and fall times. The output fromthe Q

3drives Q

4, causing that transistor

to conduct for approximately 40 nsec.You can obtain interesting results whentesting capacitors with long leads andthen testing the same capacitors withshort leads, corroborating the universaladvice to keep leads short.

TO OSCILLOSCOPE

DIFFERENTIAL INPUT

CAPACITORUNDER TEST

100k

1k

2k

2k

71.5k 71.5k

0.01 F

0.01 F

20V 20V 20V

20V

20V 20V

20V

20V

20V

5.5 TO 30 pF

100 pF

10 F0.1 F

Q1

2N3904

Q2

2N3904

Q3

2N3906

Q4

PN2222A

R1

200

1N4148

1N4148

+GROUND

CAST-ALUMINUM ENCLOSURE

NOTE:

ADJUST TRIMMER CAPACITOR

FOR GOOD WAVESHAPE/AMPLITUDE.

6-32 SCREW

FOUR PLACES

C1

C2

10

F igure 1

Build your own bypass-capacitor testerCarl Pugh, Pugh Magnetics, Newark, CA

Test the pulse characteristics of bypass capacitors using this simple circuit.

F igure 2

Components all connect to

one side of the pc board, and

a cast-aluminum cover pro-

vides shielding.

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ideasdesign

Early DACs contained standard R-2R ladder networks, and pro-duced a negative output volt-

age. These early DACs, such as theMAX7837/7847 and the MAX523, re-quire both positive and negative supply rails to accommodate their negative out-put. With the transition to single-supply ICs, however, many modern DACs oper-ate with a single supply rail and an in-verted R-2R ladder network. The invert-

ed R-2R network produces a positiveoutput voltage.Despite the popularity of single-supply ICs,some applications stillrequire a negative control voltage. Figure1 shows a circuit that satisfies this re-quirement. The circuit contains a mod-ern, inverted R-2R ladder DAC and oneop amp. In comparison with older DACs

IC2

68HC912B32

IC3

MAX541

IC4

MAX4162

IC1

MAX837

MOSI DIN

SCK SCLK

CS CS

5V

0.1 F

5V

0.1 F 0.1 F

0.1 F10

F

0.1 F

0.1 F

DGND AGND

VDD REF

OUT

GND

OUT IN

5V

249k 499k

+

5V

5

2

5V

IC1

MAX837

F igure 1

DAC and op amp provide variable-control voltageChad Olson, Maxim Integrated Products, Sunnyvale, CA

This compact circuit allows microcontroller IC2

to generate a variable negative voltage.

LISTING 1—TRIANGLE-WAVE GENERATOR



ideasdesign

containing standard R-2R ladders, thisapproach offers lower supply voltages,higher speed, and smaller packages. TheDAC, IC

3, operating with a 2.5V reference

voltage from IC1 and driven by micro-controller IC2, produces an output swing

from 0 to 2.5V. Op amp IC4inverts and

amplifies this output to produce a 0 to5V output. For test purposes, the soft-ware routine in Listing 1 commands the

microcontroller to generate a 0 to 5Vtriangle-wave output.You can download

the listing from the Web version of thisarticle at www.ednmag.com.


The complementary-switch con-troller in Figure 1 uses a few invert-er gates to provide drive signals for

the complementary switches. Comple-

mentary-switch configurations findwidespread use in synchronous-rectifi-cation circuits, charge pumps, full-bridgecontrol circuits, and other cir-cuits. The circuit in Figure 1 pro-vides not only a complementary drivesignal but also a deadtime delay on bothrising and falling edges. The high-speedinverter gates use IC

1, a 74HC04 CMOS

circuit, and 1N5819 Schottky diodes D1

and D2. The 74HC04 inverter features

symmetrical input thresholds,VIHMIN

andV

ILMAX , at 70 and 30% of the supply volt-

age,respectively.InFigure 1, IC1A invertsthe signal at Node A to produce A. WhenA rises, C

1rapidly charges through D

1.

Output B drops immediately because of IC

1B’s inversion. However, Output C

drops after a delay time that R 2

and C2

determine because D2

is reverse-biased.The following formula gives the delay time, t

1(Figure 2):

When A falls, C1 discharges throughR

1. Output B rises after a delay

time that R 1and C

1determine.C

2

discharges rapidly through D2, and out-

put C rises immediately. The followingformula gives the delay time, t

2:

By inverting C, IC1D

can provide C asignal with the same polarity as B.By se-

lecting values for R 1, C1, R 2, and C2, you

can program the delay times. The delay can be as short as 50 nsec and as long asseveral milliseconds.This range providesflexible, optimized control for target de-

vices. R 1 and R 2 should be larger than 2

k because of the limited current avail-able from the inverter IC.

3

1

4

5

C1

C2

R2

R1

D2

1N5819

D1

1N5819

IC1AA

IC1B B

6

9 8

SN74HC04

C

C

A

IC1D

IC1C

F igure 1

Logic offers complementary-switch controlYen-Hsu Chen, Analog Integrations Corp, Hsinchu, Taiwan

This circuit provides drive for complementary switches with programmable deadtimes.

t1

t2

A

C

C

B

AF igure 2

By manipulating the resistor and capacitor values in Figure 1, you can program t1 and t2.


.7.0lnCR V

V7.0lnCR t 22

DD

DD221 ==

.7.0lnCR

V

V3.0VlnCR t

11

DD

DDDD112

==



ideasdesign

The simple circuit design in Figure1 lets you measure all com-ponents of a current flowing

in a dc servo motor. The rectified outputof the circuit uses ground as a reference,so you can measure the output by usinga single-ended A/D converter. The cur-rent-sense resistor, R

1, has a value of

0.1. The Zetex (www.zetex.com)ZXCT1010 IC converts the differential

signal across R 1 to a single-ended signal.Two of these ICs form a signal rectifier.The single-ended signal makes measure-ment by an A/D converter cost-effective,small, and frugal in power consumption.The method also makes it possible tomeasure current from many sources at atime, such as in robots that use multipleservo motors. Measurement accuracy isapproximately 3%, which is adequatein most dynamic systems. Hence, an 8-

bit A/D converter suffices to digitize thesignal. If an average value of the currentis of interest, then you can place an av-eraging capacitor between the V andV terminals to remove the ac compo-

nent. The unfiltered signal has 300-kHzresponse to ac current.

R1

0.1

ZXCT1010ZXCT1010

M+

3

4 5

3

4 5

100

DC

MOTOR

SENSEDOUTPUT

VOLTAGE

V+

V

2 TO 30V DC

H-BRIDGE AND

DRIVER CIRCUIT

F igure 1

Circuit measures currents in dc servo motorShyam Tiwari, Sensors Technology Private Ltd, Gwalior, India

With this simple circuit, you can measure the currents in a dc servo motor.


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Build your own bypass-capacitor tester.pdf