C166 Family-High Performance 16-Bit Microcontrollersalt.ife.tugraz.at/LV/upprog/Pdfs/Fol167.pdf · C167 HL MC AT, lehmann ... * 10-bit / 8bit ADC * full Bus Support/ MUX Bus only

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167

HL MC AT, lehmann16x_all.ppt25.04.2005, 18:15

- 1Microcontrollers

C166 Family-High Performance 16-Bit Microcontrollers

SAB 8xC166SAB 8xC166C167xC167xC165C165C163C163C164xC164xC161xC161x

SABSAB--C167CRC167CR

XRAMXRAM1KByte1KByte

XRAMXRAM1KByte1KByteRAMRAM

1KByte1KByte

RAMRAM1KByte1KByte

PWMPWM

ADCADC

CANCAN

BUSBUS--CONTROLCONTROL

INTERRUPTINTERRUPTUNITUNIT

CAPCOMCAPCOM1+21+2

SSCSSC

USARTUSARTGPTGPT1+21+2

IR+PECIR+PEC--CONTROLCONTROL

ROMROM

WDTWDT

CORECORE

TheThe ReferenceReference ClassClass1

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 2Microcontrollers

WDTOSC.PEC

CPUROM /

RAM

PORTS

CAPCOM

ADCBusExt..

Processor -System

Interrupt-System

USART GPTs

Peripheral-System

Flash

Control

X-BusSync Communication PWMPeripheral.

C166 FamilyThe Three Subsystems


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 3Microcontrollers

WDTOSC.PEC

CPUROM /

RAM

PORTS

CAPCOM

ADCBusExt..

Processor -System

Interrupt-System

USART GPTs

Peripheral-System

Flash

Control

X-BusSync Communication PWMPeriphrl.

Microcontrollers:Control oriented instruction set

optimized event handling“System on Silicon”

Microprocessors:High computational power

high data throughputgood addressing capabilitiesHLL-supporting architecture

C166 FamilyThe Best of Both Worlds


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 4Microcontrollers

+ CAN

+ PWMMore I/OMore AD-Ch.

Different Mix

ProcessorCore

n x 4 KBROM

n x 512 BRAM

DowngradedCore

n x 8 KBFlash-EPROM

InternalROM

OSC.

InternalRAM

PECInterrupt Controller WDT

PORTS

CAPCOM10-bitADCBus

Control

Ext..USARTs GPTs

CPU

The Modular Concept


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 5Microcontrollers

Four Bus Modular SystemX Bus X Bus ModulesModules

RAM1k

RAM1k

NewModules

Timers USART SSC

Ports NewModulesWDT

ADC

CAPCOM

XRAMSSP

NewModules

CAN

I²C

NewModules

ROM8K

ROM32K

Flash32K

Flash128K

NewModules

OTP64K

Flash64K

CoreCore32

bit

32 b

it

16 - b i t16 - b i t

2x16

bit

2x16

bit

16 - b i t16 - b i t

Basic Library Basic Library ModulesModules


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 6Microcontrollers

LowLow CostCostProcessorProcessor OrientedOriented

* different RAM Size* up to 16 M Addr. Range* up to 5 Timers* Serial Interfaces

SSP, SSC

C165C165* 2KB RAM* 3V* P-TQFP-100

* 1KB RAM* SSP* 3V* reduced Peripherals* P-TQFP-100

C163C163* less Chip Selects* full Bus Support/

MUX Bus only* 3 V Options* 25 MHz Option

* 16MHz CPU* 4 M address* 1-2KB RAM* Pwr. Man. / RTC* P-MQFP-80/100

C161xC161x

* CAPCOM* PWM* Serial Interfaces* Timer* 10-bit / 8bit ADC* full Bus Support/

MUX Bus only

8xC1668xC166* 1KB RAM* 32KB ROM* 32KB Flash* P-MQFP-100

Balanced Peripheralset for a broadApplication Ranges:Price differentiation:

* 1K / 2 KB RAM* ROM / Flash / OTP

General General PurposePurpose

C164C164* 2KB RAM* 64KB OTP/ROM/Flash* Full-CAN 2.0B active* Power Management / RTC* CAPCOM6* P-MQFP-80

* 16 M Address Range* 2/4 KByte RAM* 32 CAPCOM* 4 PWM* 2 Serial Interface* 5 Timer* Chip Selects

Benefits in System Integration

* Extensive I/O

C167CRC167CR* CAN* 4K RAM* PLL

C167SRC167SR* 2KB RAM* PLL

* 2KB RAMC167C167

C167SC167S* 32K ROM* 2KB RAM* PLL

HighlyHighly IntegratedIntegrated

RoadmapRoadmap2

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 7Microcontrollers

Prefix Temp. Range Type Memory Code PackageCode Designation Size Type Code

SASA

B,FB,F C167C167 ((--)) LL MM

BB C167CRC167CR 16*16* FF MM

B, F, K B, F, K C167CRC167CR((--)) LL MM4*4* R*R* MM

B,F,KB,F,K C167SRC167SR ((--)) LL MM

B, F,KB, F,K C167CRC167CR 16*16* R*R* MM

B= 0/ 70 °CF= -40/ 85 °CK= -40/110 °C

C= CAN InterfaceR= 2KBytes XRAM

M= Metric Quad Flatpack

32KBytes

ROMLess

Flash

Mask ROMBB C167SC167S 44 MMRR

128KBytes

Numbering SchemeC167 Products

OverviewOverview3

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 8Microcontrollers

C166C166--CoreCore

167CR

PLL(input: 5 MHz)OSC(output: 20MHz)

2KB XRAM

Port

6Po

rt 0

Port

4

Port 1 Port 5 Port 3 Port 2 Port 8 Port 7

CPU

Dua

l Por

t

RAM

2 KByte

Interrupt ControllerWatchdog

PeripheralData

ExternalInstr./Data

Instr./Data

MultiFunktional

10-BitADC

USART

ASCBRG BRG

SSC

Sync.Channel

(SPI)

GPT1

T3

T4

GPT2T2

T5

T6

CAPCOM1, 2

32 Channels

Tim

er

7Ti

mer

1

Tim

er

0Ti

mer

8

PWM ModulePT 1PT 2

PT 3

PT 4

16 16 15 16 8 8

16

8

8

16

16

16

1632

PEC

Interrupt Bus

Data

Data

128 KByteROM/

EPRONFLASH

XBU

S(1

6-bi

t NO

N M

UX

Dat

a/

Add

ress

es)

External Bus,XBUS Control,5 * CS Logic

CAN2.0 B active

16 Channels

36 ext. IR

XTAL

3OverviewOverview -- C167CR Block Diagram

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 9MicrocontrollersCPUCPU

Overview (20MHz)

CompleteComplete 1616--bit bit architecturearchitecture withwith 3232--bit bit busbus to to thethe internalinternalROM to ROM to processprocess 88--bit, 16bit, 16--bit and bit and eveneven 3232--bit (MUL/DIV) bit (MUL/DIV) operandsoperands20 MHz CPU 20 MHz CPU clockclock resultsresults in an in an instructioninstruction cyclecycle time of time of 100ns 100ns whichwhich guaranteesguarantees highesthighest CPU CPU performanceperformanceTo To avoidavoid an an accumulatoraccumulator bottleneckbottleneck16 General 16 General PurposePurpose Register (GPR) Register (GPR) areare implementedimplemented--Up to 16 Up to 16 GPRsGPRs fromfrom a a registerregister bankbank-- AnyAny registerregister bankbank isis freelyfreely locatablelocatable in in internalinternal RAMRAMEasyEasy and and efficientefficient programmingprogramming isis supportedsupported byby powerfulpowerfulinstructionsinstructions combinedcombined withwith complexcomplex addressingaddressing modesmodesTransparent Transparent programmingprogramming of of thethe onon--chipchip peripheralsperipherals via via an universal Special an universal Special FunctionFunction Register (SFR) Register (SFR) interfaceinterface

4

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 10Microcontrollers

OnOn--ChipChip(EP)ROM(EP)ROM

SPSTK OV

STK UV

Block DiagramROM / RAM interaction

CPUCPU

MDLMDH

Mul./Div.-HW

Bit-Mask Gen.

ALUALU16-bit

Barrel-Shifter

Code Seg.PtrData Page

Pointer

OnOn--ChipChipStaticStaticRAMRAM

R15

R0

STK OV

STK UV

General

R15

R0

Purpose

Registers

Context Ptr.

4-StagePipeline

Exec. UnitInstr. Ptr.Instr. Reg.

ADDRSEL 1ADDRSEL 2ADDRSEL 3ADDRSEL 4

PSWSYSCONBUSCON 0

32

16

16

BUSCON 1BUSCON 2BUSCON 3BUSCON 4

4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Up to 16 Up to 16 GPRsGPRs = 1 Register = 1 Register bankbankConsistingConsisting of max.of max.-- 8 Word8 Word--RegistersRegisters-- 8 Word8 Word--Registers Registers withwith lowerlower and and higherhigher Byte Byte accessaccessTheThe GPRsGPRs areare bitbit--addressableaddressableAnyAny Register Register bankbank cancan bebe freelyfreely allocatedallocated in in internalinternal RAMRAMTheThe locationlocation of of thethe activeactive Register Register bankbank isis determineddetermined bybyContextContext Pointer (CP)Pointer (CP)CP CP cancan bebe easilyeasily switchedswitched, to , to selectselect anotheranother Register Register bankbankSWTC (SWTC (oneone instructioninstruction cyclecycle))

General Purpose Register(GPR)

4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



0F600

R8R8R9R9R10R10R11R11R12R12R13R13R14R14R15R15

RH0RH1RH2RH3RH4RH5RH6RH7

RL0RL1RL2RL3RL4RL5RL6RL7

ContextContext pointerpointer

0FDFE

2KBytesinternal RAM

R0R0R1R1R2R2R3R3R4R4R5R5R6R6R7R7

STKOV

STKUV

R15R15

R0R0

0FC00

Stackpointer UnderflowStackpointer

Stackpointer Overflow

STKUV

STKOV

Block DiagramROM / RAM interaction with 2K RAM

4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Four Stage Instruction Pipeline at 20 MHz

4CPUCPU

EffectiveEffective executionexecution time of time of mostmost instructioninstruction in 100 nsin 100 nsThreeThree wordword prefetchprefetch queuequeue ((buscontrollerbuscontroller) to ) to supportsupportpipelinepipelineOptimizedOptimized branchbranch processingprocessing-- For For branchbranch instructioninstruction ((JumpJump, , CondCond. . JumpJump, , CallCall, Return,...) , Return,...)

onlyonly oneone additional additional machinemachine cyclecycle isis normallynormally requiredrequired to to fetchfetch targettarget instructioninstruction

JumpJump CacheCache-- For For looploop processingprocessing no additional no additional machinemachine cyclecycle isis requiredrequired

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Processing of each instruction is partitioned in 4 stages

FetchDecode

Execute

Write Back

1. Instr. 2. Instr. 3. Instr. 4. Instr.

Time1 Machine Cycle = 100 ns at 20 MHz CPU clock

Four Stage Instruction Pipeline at 20 MHz

4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Instruction Set at 20 MHz

DataData manipulationmanipulation-- ArithmeticArithmetic and and booleanboolean instructioninstruction incl. fast incl. fast multiplymultiply//dividedividein 0.5/1.0us in 0.5/1.0us --Multiple (up to 15) Multiple (up to 15) bitbit shiftshift and and rotaterotate in 100 ns in 100 ns -- Bit to Bit to bitbit manipulationmanipulation in in internalinternal RAM and RAM and SFR’sSFR’s

DataData movementmovement--MOV MOV instructionsinstructions withwith all all importantimportant addressingaddressing modesmodes-- Byte to Byte to wordword conversionconversion-- System System stackstack (PUSH, POP) (PUSH, POP) withwith overover-- and and underflowunderflowcontrolcontrol-- User User stackstack (MOV (MOV withwith autoauto incrementincrement and and decrementdecrement))

......

4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



ProgramProgram manipulationmanipulation-- JumpsJumps and and callscalls / / conditionalconditional jumpsjumps underunder 16 different 16 different conditionsconditions-- SoftwareSoftware-- and and hardwarehardware--TrapsTraps-- Fast Fast contextcontext switchingswitching in 100 nsin 100 ns

Special Special instructionsinstructions forfor-- Power Power consumptionconsumption reductionreduction and and systemsystem ControlControl-- NonNon--interruptableinterruptable instructioninstruction sequencessequences-- ExtendedExtended addressingaddressing accessaccess

...Instruction Set at 20 MHz

4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Address Space...

CompleteComplete addressaddress spacespace-- “von Neumann” “von Neumann” architecturearchitecture withwith multiple multiple internalinternal busbusstructurestructure to to avoidavoid busbus bottlenecksbottlenecks-- 64KByte 64KByte nonnon--segmentedsegmented addressaddress spacespace-- up to 16 MBytesup to 16 MBytes-- segmentedsegmented addressaddress spacespace: 64KB : 64KB codecode segmentssegments and 16K and 16K datadata pagespages

InternalInternal addressaddress spacespace-- up to 128 KBytes ROM / up to 128 KBytes ROM / FlashFlash--EPROMEPROM--maxmax 4 KByte 4 KByte SFR'sSFR's

MemoryMemory

RAMRAMRAM

ROMROMROM

C167C167C167 C167CRC167C167CRCR

4 KByte4 KByte4 KByte 4 KByte4 KByte4 KByte

128 KByte Flash128 KByte 128 KByte FlashFlash 128 KByte 128 KByte FlashFlash

5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Flexible Flexible extext. . busbus configurationsconfigurations to to simplifysimplify systemsystemintegrationintegration-- up to 24up to 24--bit bit AddressAddress / 8/ 8--bit bit DataData (MUX and NMUX)(MUX and NMUX)-- up to 24up to 24--bit bit AddressAddress / 16/ 16--bit bit DataData (MUX and NMUX)(MUX and NMUX)-- Five Five completelycompletely independent independent configurationconfiguration registersregisters-- Five Five programmableprogrammable chipchip selectsselects and and programmableprogrammable busbus

controlcontrol signalsignal to save to save externalexternal glueglue--logiclogic-- ProgrammableProgrammable HOLD/HOLDA/BREQ HOLD/HOLDA/BREQ busbus arbitrationarbitrationfunctionfunction forfor multimulti--mastermaster operationsoperations

...Address Space

MemoryMemory5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Bit Addressable Space

Segment 0 Segment 0 includesincludes InternalInternal MemoryMemory

512 BytesSFR’s

InternalRAM

1K

1KInternalRAM

ExternalMemory

Internal ROM /Flash E²PROM

(mappable to Seg. 1)

512 BytesExt. SFR’s

00000

0E800

08000

0FE00

0FA00

0F200

100007 0

128K

0.5K

0.5K

Reserved

up to 16 Mup to 16 MBytesBytesCode Segments Data Pages

0

1

2

3

3

2

1

0

7

6

5

4

11

10

9

8

15

14

13

12

InternalROM/

FLASH

10000

20000

30000

3FFFF

Internal and externalMemory Map - C167CR

MemoryMemory

0F000

X-Bus Peripheral

Full Full -- CANCAN

0F600Reserved

5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Code and Data Addressing via Segmentationand Paging on 16 Mbyte address range

MemoryMemory

15

Data addressing with Data Page Pointer (DPP) Code addressing with Code Segment Pointer

Selection of oneData Page Pointer 8-bit Segment

Number16-bit

14-bit

10-bitPageNumber

Physical 24-bit Code addressPhysical 24-bit Data address

DPP3DPP2DPP1DPP0

Code Seg. Pointer013 16-bit Adress 015 16-bit Instr. Pointer71415 0

5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



M B y te K B y te

8 4 2 1 M 5 1 2 2 5 6 1 2 8 6 4 3 2 1 6 8 4 2 1 K 5 1 2 2 5 6 1 2 8 6 4 3 2 1 6 8 4 2 0

2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0

1 6 K

D P P 0 = 0 0D P P 1 = 0 1D P P 2 = 1 0D P P 3 = 1 1

Data Addressing via Data Page Pointer (DPPx)

MemoryMemory5

DPP

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Data Addressing via Extended Mode

Examples: Override Segment Number

EXTS RN,#data2 ;data2:No. of instructionsMOV [RM],Ri ;to be used for Ext.Addr.Mode

EXTP RN, #data2MOV [RM], Ri

RN RM RN RM

Physical address, where the contents of Ri is moved to Physical address, where the contents of Ri is moved to

15 0 0 0 015 1515

0 0 0 013

A13 A0A14A23A0A15A16A23

9157

Override Page Number

OverridesOverrides standardstandard DPP DPP addressingaddressing schemescheme to to easeease large large (up to 32(up to 32--bit) bit) addressaddress calculationcalculation-- Segment Segment oror Page Page overrideoverride byby an immediate an immediate valuevalue-- Segment and Page Segment and Page overrideoverride byby a Register a Register contentscontents

MemoryMemory5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



External bus speed optimization by prefetching into the instruction queue !

Instr. Instr. FetchFetch TimeTime2 Word2 Word

Bus Bus CycleCycle TimeTime0 / 1 / 2 0 / 1 / 2 WaitWait StatesStates

n.an.a..

nonenone nonenone 16 Bit16 Bit 8 Bit8 Bitnonenone

nonenone Port 0, 1, 4Port 0, 1, 4 Port 1, 4Port 1, 4 Port 1, 4Port 1, 4Port 0, 1, 4Port 0, 1, 4

singlesingle ChipChipModeMode

16 Bit 16 Bit DataData16/24 16/24 bitbit AddressAddress

NON MUXNON MUX


MUXMUX


NON MUXNON MUX


MUXMUX

AddressAddress LatchLatch

Instr. Instr. FetchFetch TimeTime1 Word1 Word

usedused PortsPorts

100/150/200 ns100/150/200 ns

Comparison of Bus Speed at Different Bus Configurations at 20 MHz CPU Clock

100ns /../..100ns /../..

100ns /../..100ns /../..

100/50/200 ns100/50/200 ns 300/400/500 ns300/400/500 ns

600/800ns/1µs600/800ns/1µs

70/120/170 ns70/120/170 ns 70/120/170 ns70/120/170 ns 70/120/170 ns70/120/170 ns

200/300/400 ns200/300/400 ns 300/400/500 ns300/400/500 ns

150/200/250 ns150/200/250 ns

70/120/170 ns70/120/170 ns

400/600/800 ns400/600/800 ns

200/300/400 ns200/300/400 ns

100/150/200 ns100/150/200 ns 150/200/250 ns150/200/250 ns 150/200/250 ns150/200/250 ns100ns /../..100ns /../..

EPROM Access EPROM Access Time t17Time t17

11 1.51.5 2.52.5 4.54.53.03.0(50% 2 (50% 2 wordword instructionsinstructions) )

rel. rel. speedspeed forfortyptyp. . codecode

MemoryMemory5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Relative Performance vs. CPU Frequency

0 .0 0

2 .0 0

4 .0 0

6 .0 0

8 .0 0

1 0 .0 0

1 2 .0 0

1 4 .0 0

1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5

C P U F r e q u e n c y (M H z )

Rel

ativ

e Pe

rfor

man

ce

S in g le C h ip P e r f o r m a n c e0 W S P e r f o r m a n c e1 W S P e r f o r m a n c e2 W S P e r f o r m a n c e

0 .0 0

2 .0 0

4 .0 0

6 .0 0

8 .0 0

1 0 .0 0

1 2 .0 0

1 4 .0 0

1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5

C P U F r e q u e n c y (M H z )

Rel

ativ

e Pe

rfor

man

ce

S in g le C h ip P e r f o r m a n c e0 W S P e r f o r m a n c e1 W S P e r f o r m a n c e2 W S P e r f o r m a n c e

graph by Patrick Pettibon

0/1/2 Waitstates based on 0% mix of 1-wordand 2-word Fetches with Data in the internal DP-RAM

0/1/2 Waitstates based on 0% mix of 1-wordand 2-word Fetches with Data in the internal DP-RAM

MemoryMemory5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



C163 FlashComparsion with C167CR Flash

C163 Flash Module C163 Flash Module

C163 Flash ModuleNew Technology

C167 Flash Module

128 KByte 128 KByte capacitycapacityAnyAny useuse forfor instructioninstruction codecode oror datadata

ProgrammingProgramming and and eraseerase-- 12 V on separate VPP 12 V on separate VPP pinpin-- SW SW controlledcontrolled-- ComplexComplex SW to SW to avoidavoid overover//underunder--

programmingprogramming oror eraseeraseProgrammingProgramming controlcontrol+ Fast: 200 + Fast: 200 msecmsec per 8 KB blockper 8 KB blockEraseErase controlcontrol-- PreprogrammingPreprogramming (all (all zeroszeros) ) necessarynecessary-- SlowSlow: 1 sec per : 1 sec per sectorsector

128 KByte 128 KByte capacitycapacityAnyAny useuse forfor instructioninstruction codecode oror datadata

ProgrammingProgramming and and eraseerase+ Progr. + Progr. voltagevoltage 5V on 5V on standardstandard VCC VCC pinspins+ + IntegratedIntegrated statestate machinemachine+ + DirectlyDirectly controlledcontrolled byby commandscommands

ProgrammingProgramming controlcontrol+ Fast: 125 + Fast: 125 msecmsec per 8 KB blockper 8 KB blockEraseErase controlcontrol+ Simple + Simple eraseerase commandcommand per per sectorsector+ Fast: 10 + Fast: 10 msecmsec per per sectorsector

6

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



InterruptInterrupt ControllerController-- ExtremelyExtremely shortshort interruptinterrupt responseresponse time of minimal 250ns time of minimal 250ns typicaltypical: 400ns : 400ns -- InterruptInterrupt executionexecution in in smallsmall time time segmentssegments-- EnsuresEnsures highesthighest realreal--timetime performanceperformance-- ComprehensiveComprehensive prioritizationprioritization schemescheme

-- EasyEasy schedulingscheduling of of complexcomplex realreal--timetime systemssystems bybyusingusing up to 64 up to 64 prioritypriority levelslevels (4 (4 groupsgroups withinwithin 16 16 levelslevels))--NonNon--maskablemaskable interruptinterrupt inputinput (NMI)(NMI)-- HardwareHardware--TrapsTraps on on runtimeruntime errorserrors and and SoftwareSoftware--TrapsTraps

......

InterruptInterrupt SystemSystem

Overview at 20MHz...

8

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CPU independent CPU independent interruptinterrupt--serviceservice via via PeripheralPeripheral Events Controller (PEC)Events Controller (PEC)--OffOff--loadsloads thethe CPU CPU fromfrom simple simple butbut frequentfrequent interruptinterrupt--

servicesservices-- InterruptInterrupt--drivendriven ““DMADMA--likelike” ” datadata transfertransfer to to anyany locationlocation in in segmentsegment 0, 0, withoutwithout tasktask switchswitch of of thethe CPUCPU--MakesMakes peripheralperipheral datadata transferstransfers Independent of Independent of runningrunningCPU CPU routineroutine-- ResponseResponse--timetime isis minimal 150ns, minimal 150ns, typicaltypical 300ns 300ns withwith a CPU a CPU loadload of 100nsof 100ns

...Overview at 20MHz

8InterruptInterrupt SystemSystem

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



3 2 1 01514131211109876543210

group

L e

v e

l

1

64

Level 15 group 1group 0

group 2group 3


group 2group 3 PEC 0

PEC 6 PEC 5PEC 4

PEC 3PEC 2 PEC 1

PEC 7


group 2group 3

Level 1-12 group 1group 0

group 2group 3


group 2group 3

Priority System, PEC


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Interrupt Processing

INTR Flag is Set

Peripheral Interrupt




External Interrupt*

External Interrupt*

Priority Check

Comparison ofInterrupt Priority

with CPURuntime Priority

16 Priority Levels

ifhigherPriority

Interrupt Control Register of the appropriate peripheralINTR Service:

Save PSW, CSP, IP

Set new priorityin PSW.

Set CSP, IPaccording toperipheralvector orTrap no.

PECService

* External Interrupts are possible, e.g. instead of the Capture Input

36 ext. Interrupts(+ NMI) including 8 which are sampled every 50 ns55 Peripheral Interrupts

4 Groups

Group Check

ClearINTR Flag


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Interrupt has passed priority and group check

Interrupt priority < 14 Interrupt priority 14 or 15and Data Counter > 0Interrupt priority 14 or 15and Data Counter > 0

Interrupt service PEC service

PEC

8 PECChannel

Data CounterSRC PointerDEST Pointer

Contr. Reg.

IR request if Data Counter = 0

MemoryMemory Segment 0Segment 00FFFF

00000

Byte orWordTransfer

INTR Service:

Save PSW, CSP, IP

Set new priorityin PSW.

Set CSP, IPaccording toPeripheralvector orTrap No. IR request if Data Counter = 0priority & group

check

Peripheral Event Controller (PEC)


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



2 General 2 General PurposePurpose Timer Timer unitsunits (GPT1 & GPT2)(GPT1 & GPT2)-- 5 Timers (200/400ns) 5 Timers (200/400ns) withwith enhancedenhanced Input/Output, Input/Output, ReloadReloadand and CaptureCapture functionsfunctions and and complexcomplex concatenationconcatenationcapabilitiescapabilities

2 2 CaptureCapture//CompareCompare unitsunits (CAPCOM1 & 2)(CAPCOM1 & 2)-- 4 Timers (400ns) 4 Timers (400ns) withwith ReloadReload registerregister and 32 independent and 32 independent 1616--bit bit CaptureCapture//CompareCompare channelschannels programmableprogrammable to 6 to 6 modesmodes of of operationoperation

4 high 4 high resolutionresolution PWM PWM channelschannels-- eacheach withwith independent independent timetime--basebase of up to 50ns of up to 50ns resolutionresolutionand and programmableprogrammable operationoperation modesmodes ((edgeedge--alignedaligned, , centercenter--alignedaligned, , burstburst and and singlesingle--shotshot mode)mode)

......

Peripherals Set of theC167...

9PeripheralsPeripherals

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Independent USARTIndependent USART--maxmax 625 625 KBaudKBaud asynchronousasynchronous and and maxmax 2.5 2.5 MbitMbit/sec /sec synchronoussynchronous datadata transfertransfer

Fast Fast SerialSerial SynchronousSynchronous CommunicationCommunication interfaceinterface (SSC)(SSC)--maxmax 5 5 MbitMbit/sec /sec fullfull duplexduplex transfertransfer rate, SPI rate, SPI compatiblecompatibleFast and Fast and accurateaccurate A/D A/D ConverterConverter-- 1010--Bit Bit resolutionresolution, 16 , 16 inputinput channelschannels, 9.7µs , 9.7µs conversionconversion time, time,

enhancedenhanced continuouscontinuous and and scanscan modesmodes withwithchannelchannel--injectioninjection capabilitycapability..

I/O PortsI/O Ports-- 8 Ports 8 Ports provideprovide 111 I/O 111 I/O lineslinesWatchdogWatchdog: 16: 16--Bit Bit ReloadReload--timertimer causescauses resetreset on on overflowoverflow

...Peripherals Set of theC167

9PeripheralsPeripherals

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



ThreeThree 1616--bit up/down bit up/down timerstimers: : 2 2 auxiliaryauxiliary timers(T2,T4) and 1 timers(T2,T4) and 1 corecore timer(T3) timer(T3) Input modeInput mode-- Timer mode: Timer mode: InternalInternal clockclock inputinput withwith prescalerprescaler up to up to

2.5 MHz / 400 ns; 2.5 MHz / 400 ns; ClockClock cancan bebe gatedgated withwith externalexternal signalsignal-- CounterCounter Mode: Mode: externalexternal clockclock up to 1.25 MHzup to 1.25 MHz-- CascadingCascading of of corecore timertimer and and anyany auxaux. . timertimer (33(33--Bit Bit timertimer))CountCount directiondirection ((onlyonly T3 ) T3 ) cancan bebe changedchanged externallyexternallyOutput modeOutput mode-- InterruptInterrupt possibilitypossibility and toggle and toggle functionfunction at at thethe corecore timertimer T3T3-- InterruptInterrupt possibilitypossibility at at auxiliaryauxiliary timerstimers T2 and T4T2 and T4ReloadReload: : CoreCore timertimer cancan bebe reloadedreloaded withwith thethe contentscontents of of anyany auxaux. . timertimerCaptureCapture: : ContentsContents of of thethe corecore timertimer cancan bebe latchedlatched intointoanyany auxaux. . timertimer

General Purpose Timer 1(GPT 1) at 20 MHz

10GPT 1GPT 1

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



GPT 1 Function Diagramat 20 MHz

Clk max2.5 MHzClk max2.5 MHz

GateGate

InputMode

ControlCore Timer T3 Core Timer T3

ToggleLatch

INTRFlag INTRINTRFlag Flag


GateGate

InputMode

ControlAux Timer T2 / T4Aux Timer T2 / T4

Capture

RunEnableRun

Enable


Outp.enablesOutp.

enables

GateGate

InputMode

ControlAux Timer T2 / T4Aux Timer T2 / T4

up / down

RunEnableRun

Enable


Reload

RunEnableRun

EnableClk max2.5 MHzClk max2.5 MHz

33-bit cascaded path

max.1.25 MHz

max.1.25 MHz

max.1.25 MHz

up / down

up / down

10GPT 1GPT 1

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



TwoTwo 1616--Bit up/down Bit up/down timerstimers (T5, T6)(T5, T6)Input modeInput mode-- Timer mode: Timer mode: InternalInternal clockclock inputinput withwith prescalerprescaler up to 5MHz up to 5MHz

(200ns)(200ns)-- CounterCounter mode: mode: ExternalExternal clockclock up to 2.5 MHz up to 2.5 MHz -- T5 T5 cancan also also bebe clockedclocked withwith thethe toggle toggle bitbit of T6of T6Output modeOutput mode-- InterruptInterrupt possibilitypossibility and toggle and toggle functionfunction of a of a portport lineline (via a (via a

toggle toggle bitbit))-- Output of T6 Output of T6 cancan bebe usedused to to clockclock CAPCOM CAPCOM timerstimersCountCount directiondirection of all of all timerstimers cancan bebe dynamicallydynamically changedchanged(C167) (C167) CascadingCascading of of timertimer T6 T6 withwith timertimer T5T5One 16One 16--Bit Bit Capture(forCapture(for T5) / T5) / Reload(forReload(for T6) T6) registerregister--ReloadReload registerregister forfor T6, T6, CaptureCapture registerregister forfor T5T5

General Purpose Timer 2 (GPT 2) at 20 MHz

11GPT 2GPT 2

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



GPT 2 Function Diagramat 20 MHz

11GPT 2GPT 2

Capture / ReloadCapture / Reload

Clk max5.0 MHzClk max5.0 MHz Input

ModeControl

Aux Timer T2 / T4Aux Timer T2 / T4

RunEnableRun

Enable

EnableEnable

InputMode

ControlTimer T5 Timer T5

RunEnableRun


ReloadEnableReloadEnable

Clear

Outp.enablesOutp.

enables

to CAPCOMTimer T0, T1

ToggleLatch

EnableEnable

33-bit cascaded path



INTRFlag INTRINTRFlag Flag max.

2.5 MHz

max.2.5 MHz

up / down

up / down

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



FourFour 1616--bit bit timerstimers (T0/T1 & T7/T8), 16(T0/T1 & T7/T8), 16--bit bit reloadreload reg. reg. eacheach-- Timer mode:Timer mode: Int. Int. clockclock inputinput withwith up to 2.5 MHz (400ns)up to 2.5 MHz (400ns)--CounterCounter mode:mode: ExternalExternal clockclock inputinput to T0/T7 up to 1.25 to T0/T7 up to 1.25 MHz, Output MHz, Output fromfrom T6 T6 cancan bebe usedused as as clockclock inputinput-- CAPCOM 2 CAPCOM 2 cancan bebe synchronizedsynchronized via T0 to CAPCOM 1via T0 to CAPCOM 1

TwoTwo unitsunits withwith sixteensixteen 1616--Bit Bit CaptureCapture//CompareCompare registersregisters-- IndividuallyIndividually programprogram. . forfor CaptureCapture oror anyany CompareCompare modemode-- IndividuallyIndividually allocatableallocatable to to timertimer T0/T1 T0/T1 oror T7/T8T7/T8VariousVarious CompareCompare modesmodes forfor flexibleflexiblePulse Pulse WidthWidth Modulation(PWMModulation(PWM))--OutputOutput--Pin Pin togglestoggles ifif CompareCompare isis truetrue-- 1 1 oror 2 2 CompareCompare registersregisters cancan operateoperate to to oneone OutputOutput--PinPin--One One oror moremore CompareCompare eventsevents cancan bebe detecteddetected in in oneone timertimer

periodperiod-- InterruptInterrupt onlyonly modemode

Capture / Compare Unit 1/2 (CAPCOM 1/2)...

12PWM PWM generationgeneration -- CAPCOM 1/2 CAPCOM 1/2

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAPCOM(1)Function Diagram

InputMode

Control

T0 ReloadT0 Reload

RunEnableRun


T1 ReloadT1 Reload

Timer T1 Timer T1

Timer T0 Timer T0

Mode Mode ControlControlSixteen16 Bit

Capture/CompareRegister

CC0-CC15





from T6

InputMode

ControlRun

EnableRun

Enable


from T6

Edge Selectfor

Capture Input

- Capture Mode- Compare Mode 0- Compare Mode 1- Compare Mode 2- Compare Mode 3- Double RegisterCompare Mode 0

12PWM PWM generationgeneration -- CAPCOM (1) CAPCOM (1)

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAPCOM 2Function Diagram

Edge Selectfor

Capture Input

InputMode

Control

T7 ReloadT7 Reload

RunEnableRun


T8 ReloadT8 Reload

Timer T8 Timer T8

Timer T7 Timer T7

Mode Mode ControlControlSixteen16 Bit

Capture/CompareRegister

CC16-CC33





from T6

InputMode

ControlRun

EnableRun

Enable


from T6

Channel 24 to 27only CaptureInput possible

Channel 31 is able to triggeran ADC Channel Injection

- Capture Mode- Compare Mode 0- Compare Mode 1- Compare Mode 2- Compare Mode 3- Double RegisterCompare Mode 0

12PWM PWM generationgeneration -- CAPCOM 2 CAPCOM 2

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAPCOM 1/2Compare Mode 0 and 1

Mode 0: onlyINTR Flag is set

Mode 1: INTR Flag is setand Port Pin is toggled

Compare Value 2

Compare Value 1

FFFF

Reload Value

NewReload Value

Compare Register X: Value 1 Value 2is changed to

Com

pare

INTR

Timer INTR

Com

pare

INTR

SeveralSeveral CompareCompare eventsevents areare possiblepossible withinwithin a a singlesingle Timer Timer periodperiod

12

Port Level P1.xP8.x (C164)

PWM PWM generationgeneration -- CAPCOM 1/2 CAPCOM 1/2

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Mode 2: onlyINTR Flag is set

Mode 3: INTR Flag is set.Port Pin is set at the firstCompare Event and resetat Timer overflow

CAPCOM 1/2Compare Mode 2 and 3

Compare Value 2

Compare Value 1

FFFF

Reload Value

NewReload Value

Compare Register X: Value 1 Value 2is changed to

Com

pare

INTR

Tim

er IN

TR

OnlyOnly oneone CompareCompare eventsevents isis possiblepossible withinwithin a a singlesingle Timer Timer periodperiod

12



C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Bank1 Compare Register X:(programmed to mode 1)

the associated

Bank2 Compare Register Y:(programmed to mode 0)

CAPCOM 1/2Double Register Compare Mode

Compare Value 2

Compare Value 1

FFFF

Reload Value

NewReload Value

Value X

Value Y

Com

pare

INTR

Reg

. Y

Timer INTR

Com

pare

INTR

Reg

. X

TwoTwo CompareCompare Register Register workwork togethertogether to to controlcontrol oneone Port Port PinPinThisThis mode mode isis selectedselected byby a a specialspecial combinationcombination of of thethemode 0 and 1mode 0 and 1

12



C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Pulse Width Modulation Unit (PWM)

4 4 completelycompletely indepindep. PWM . PWM channelschannels eacheach withwith itsits ownown timetime--basebase-- 50ns 50ns oror 12.8µs 12.8µs timertimer--resolutionresolution providesprovides a a veryvery widewide

frequencyfrequency rangerange to to generategenerate PWM PWM signalssignals-- ProgrammableProgrammable outputoutput polaritypolarity-- Up to 78 KHz at 8Up to 78 KHz at 8--bit PWM bit PWM resolutionresolution

FourFour operationoperation modesmodes-- Standard, Standard, edgeedge--alignedaligned PWMPWM-- SymmetricalSymmetrical, , centercenter--alignedaligned PWM PWM forfor asynchronousasynchronous motormotorcontrolcontrol-- BurstBurst--modemode forfor modulatedmodulated PWM PWM signalssignals-- SingleSingle--shotshot modemode

FPWM = 12 x 50ms8-bit

12

=78 KHz

PWM PWM generationgeneration -- PWM PWM unitunit

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



PWM unitFrequencies and Resolution

PMW Unit Frequencies and Resolution in Mode 1 Operation (SYMMETRICAL)(SYMMETRICAL)

PMW Unit Frequencies and Resolution in Mode 0 Operation (EDGE(EDGE--ALIGNED)ALIGNED)

Resolution Resolution Input Input ClockClock (CPU @ 20 MHz)

8 Bit 10 Bit 12 Bit 14 Bit 16 Bit

CPU Clock (50ns Resolution)

CPU Clock / 64 (3.2µs Res.)

39.1 KHz

610 Hz

9.77 KHz

152.6 Hz

2.44 KHz

38.15 Hz

610 Hz

9.54 Hz

152.6 Hz

2.4 Hz

Resolution Resolution Input Input ClockClock (CPU @ 20 MHz)

8 Bit 10 Bit 12 Bit 14 Bit 16 Bit

CPU Clock (50ns Resolution)

CPU Clock / 64 (3.2µs Res.)

78.1 KHz

1.22 KHz

19.5 KHz

305 Hz

4.88 KHz

76.3 Hz

1.22 KHz

13.1 Hz

305 Hz

4.77 Hz

12PWM PWM generationgeneration -- PWM PWM unitunit

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



RunEnableRun

Enable

Timer PT0-PT3

Comparator

Shadow Register


PWM unitFunction Diagramm

InputMode

Control

Pulse Width Reg. PW0-PW3

Shadow Register

4 identical PWM Channels with common Interrupt Control Register

Period Register PP0-PP3

Output PolarityEnable

Output PolarityEnable

20 MHz

78 KHz

at 20 MHz CPU Clock

PWMOutputs

Comparator

up/down,clear


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



PWM unitMode 0 and 1...

Contents of thePWx Register

Interrupt Request andLatch of the Shadow Register

Contents of the PWxRegister

IR and Latch of theShadow Register

Timer Period

Timer Period Timer Period

Contents of the Period Register (PPx)

PWM Mode 0: Standard PWM’s or Edge-Aligned PWM’s

PWM Mode 1: Symmetrical or Center-Aligned PWM’s

PWM Signal

If all channels are programmed to mode 0,edge-aligned PWM signals will be generated.A duty cycle from 0 to 100% is programmable

If all channels are programmed to mode 1,center-aligned PWM signals will be generated.A duty cycle from 0 to 100% is programmable

PWM Signal

Possible PWM Signals from other channels programmed to the same mode:

PWMx

PWMy


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



... PWM unitModes

Burst Mode :Burst Sequence by combiningPWM channel 0 and 1

Single Shot : Only one PWM Pulse is generatedMode available for channel 2 and 3

Period Value Period Value

Pulse widthValue

PeriodValue

Internal Signalof Channel 0

Period ofTimer PT1

Int. Signalof Channel 1

Output Result: Channel 1 is modulated by Channel 0

OutputSignal

Timer isautomatically

stopped

Timer isreleased by

Software again

The Timer can be dynamically changed tolengthen (retrigger) or shorten the output pulse

Timer Period

Timer Period PT0


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Analog Digital Converter(ADC)

1010--Bit ADC Bit ADC basedbased on on thethe successivesuccessive approximationapproximationprincipleprinciple-- 9.7µs 9.7µs conversionconversion--timetime--OnOn--chipchip samplesample-- & & holdhold--circuitcircuit (1.6 (1.6 usus samplesample--timetime))-- 16 16 MultiplexedMultiplexed inputinput channelschannels-- Automatic Automatic selfself--calibrationcalibration afterafter conversionconversionFlexible Flexible operationoperation modemode-- SingleSingle--channelchannel and and singlesingle--channelchannel--continuouscontinuous forfor periodicperiodic

datadata acquisitionacquisition-- AutoAuto--scanscan and and autoauto--scanscan--continuouscontinuous forfor permanent permanent datadatatrackingtracking-- ChannelChannel--injectioninjection mode mode withwith ownown resultresult--registerregister cancan bebeusedused to to interruptinterrupt thethe scanscan modesmodes

EasyEasy errorerror handlinghandling and and channelchannel identificationidentification-- 1010--bit bit resultresult and and channelchannel numbernumber in in resultresult registerregister-- OverrunOverrun errorerror checkcheck

13ADCADC

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



AnalogInputs

Channel and Mode Control Conversion ControlChannel and Mode Control Conversion Control

ReferenceVoltage

8 (16)ChannelAnalogMUX

C-NETSwitch

Tree

Com-parator



10-Bit A/D ConverterBlock Diagram

13ADCADC

Timing Controland SuccessiveApproximation

Register

ChannelInformation Result Register

ChannelSelection Result Register for Channel Injection Mode

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



SynchronousSynchronous / / asynchronousasynchronous serialserial channelchannel withwith itsits ownownbaudbaud--raterate--generatorgeneratorAsynchronousAsynchronous mode mode withwith maxmax 625 625 KBaudKBaud transfertransfer rate rate -- Full Full duplexduplex ((receivereceive and and transmittransmit at at thethe samesame time)time)-- programmableprogrammable featuresfeatures::-- 1 1 oror 2 2 stopstop bitsbits, 7, 8 , 7, 8 oror 9 9 datadata bitsbits-- Generation of Generation of parityparity-- oror wakewake--upup bitbit at at datadata transmissiontransmission--OddOdd oror eveneven parityparity-- Error Error detectiondetection ((parityparity, , overrunoverrun, , framingframing))--WakeWake--upup check (check (receivereceive int. int. flagflag isis setset ifif wakewake--upup bitbit isis truetrue))SynchronousSynchronous mode mode withwith maxmax 2.5 2.5 MbitMbit/sec /sec transfertransfer rangerange--Half Half duplexduplex operationoperation ((onlyonly transmittransmit oror receivereceive possiblepossible))-- EasyEasy I/O I/O expansionexpansion withwith externalexternal shiftshift registerregister-- OverrunOverrun errorerror detectiondetection

USARTUSART

Asynchronous / SynchronousSerial Channel (USART) at 20MHz

14

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



INTRFlag

Transmit

INTRINTRFlagFlag

TransmitTransmit

INTRFlag

Receive

INTRINTRFlagFlag

ReceiveReceive

INTRFlag

ERROR

INTRINTRFlagFlag

ERRORERROR

to internal Bus

CPU CLK Baud Rate Generator

Control Reg.

ControlUnit

Transmit Shift Register

Receive Shift Register

Receive Buffer

from internal Bus

Shift CLK

Asynchronous/Synchronous

Port Pin

Port Pin

Port Pin

Port Pin

USART Block Diagram

14USARTUSART

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Synchronous Serial Channel(SSC), SPI compatible at 20 MHz

Full Full duplexduplex SynchronousSynchronous SerialSerial ChannelChannel (SSC) (SSC) withwith itsitsownown baudratebaudrate generatorgenerator forfor high high speedspeed communicationcommunicationUp to 5 Up to 5 MbitMbit/sec /sec transfertransfer raterateSPI SPI compatiblecompatibleMaster (Master (clockclock isis outputoutput) ) oror slaveslave mode (mode (clockclock isis inputinput))ProgrammableProgrammable featuresfeatures to to satisfysatisfy variousvarious communicationcommunicationrequirementsrequirements--MSB MSB oror LSB LSB firstfirst-- DataData frameframe fromfrom oneone to 16to 16--bitbit-- ClockClock polaritypolarity and and phasephase

14USARTUSART

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Synchronous Serial Channel - Block Diagram

Baud RateGenerator

ClockControl

Control Unitwith Controland StatusRegisters

Shift Registerprogrammable from 1 - 16-bit

MSB- / LSB-First Selection

Receive Buffer

Transmit Buffer

Internal Bus

InterruptRequest

Slave ModeMaster Mode SSCCLKCPU

Clock Master / SlaveSelection

SSCDI

SSCDO

15SSPSSP

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Differences between SSP and SSCSSP (C163)

Up to 10 MBaud @ 20 MHz CPUclock

Only half duplex communicationpossible;

one bidirectional data lineShift clock can only be generated

(master only)Data width 1 byte

No error detection mechanismsTwo dedicated chip enable lines

Connected to XBUS1 interrupt source dedicated to SSP

Synchronous Serial PortSSCSSC

Up to 5 Up to 5 MBaudMBaud @ 20 MHz CPU@ 20 MHz CPUclockclock

Full Full duplexduplex communicationcommunicationpossiblepossible;;

twotwo datadata lineslines ((TransmitTransmit, , ReceiveReceive))ShiftShift clockclock cancan bebe generatedgenerated((mastermaster) ) oror receivedreceived ((slaveslave))

DataData widthwidth cancan bebe chosenchosen fromfrom 22bitsbits to 16 to 16 bitsbits

Error Error detectiondetection mechanismsmechanismsNo No dedicateddedicated chipchip enableenable lineslines

ConnectedConnected to to InternalInternal BusBus3 3 interruptinterrupt sourcessources dedicateddedicated toto

SSCSSC

SynchronousSynchronous SerialSerial ChannelChannel

SSP vs. SSCSSP vs. SSC16

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAN CAN isis lowlow costcost-- SerialSerial busbus withwith twotwo wireswires: good : good priceprice//performanceperformance ratioratio-- LowLow costcost protocolprotocol devicesdevices availableavailable drivendriven byby high high volumevolumeproductionproduction in in thethe automotiveautomotive and and industrialindustrial marketsmarkets-- AboutAbout 15.000.000 CAN 15.000.000 CAN nodesnodes in in useuse so farso far

CAN CAN isis reliablereliable-- SophisticatedSophisticated errorerror detectiondetection and and errorerror handlinghandlingmechanismsmechanisms resultsresults in high in high reliabilityreliability transmissiontransmission-- ExampleExample: 500 : 500 kbitkbit/s, 25% /s, 25% busbus loadload, 2000 , 2000 hourshours per per yearyear::One One undetectedundetected errorerror everyevery 1000 1000 yearsyears-- ErroneousErroneous messagesmessages areare detecteddetected and and repeatedrepeated-- EveryEvery busbus nodenode isis informedinformed aboutabout an an errorerror-- High High immunityimmunity to to ElectromagneticElectromagnetic InterferenceInterference

......

User Benefits...

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAN CAN meansmeans realreal--timetime-- Short Short messagemessage lengthlength (0 to 8 (0 to 8 datadata bytesbytes / / messagemessage))-- LowLow latencylatency betweenbetween transmissiontransmission requestrequest and and actualactual start start of of transmissiontransmission-- InherentInherent ArbitrationArbitration on on MessageMessage PriorityPriority (AMP) (AMP) --Multi Master Multi Master usingusing CSMA/CD + AMP CSMA/CD + AMP methodmethod

CAN CAN isis flexibleflexible--CAN CAN NodesNodes cancan bebe easilyeasily connectedconnected / / disconnecteddisconnected((i.ei.e. . plugplug & & playplay))-- NumberNumber of of nodesnodes notnot limitedlimited byby thethe protocolprotocol

CAN CAN isis fastfast--maximummaximum datadata rate rate isis 1 MBit/s @ 40 m 1 MBit/s @ 40 m busbus lengthlength(still (still aboutabout 40 40 kBitkBit/s @ 1000 m /s @ 1000 m busbus lengthlength))

......

...User Benefits...

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAN CAN allowsallows MultiMulti--Master OperationMaster Operation-- EachEach CAN CAN nodenode isis ableable to to accessaccess thethe busbus-- Bus Bus communicationcommunication isis notnot disturbeddisturbed byby faultyfaulty nodesnodes-- FaultyFaulty nodesnodes selfself swithswith--offoff fromfrom busbus communicationcommunicationCAN CAN meansmeans BroadcastBroadcast CapabilityCapability--MessagesMessages cancan bebe sentsent to to singlesingle/multiple /multiple nodesnodes-- All All nodesnodes simultaneouslysimultaneously receivereceive commoncommon datadataCAN CAN isis standardizedstandardized-- ISOISO--DIS 11898 (high DIS 11898 (high speedspeed applicationsapplications))-- ISOISO--DIS 11519DIS 11519--1 (1 (lowlow speedspeed applicationsapplications))

...User Benefits

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAN in CAN in motormotor vehiclesvehicles ((carscars, , truckstrucks, , busesbuses))-- EnablesEnables communicationcommunication betweenbetween ECUsECUs likelike engineenginemanagementmanagement systemsystem, , antianti--skidskid brakingbraking, , geargear controlcontrol, , activeactivesuspensionsuspension ... (... (powerpower traintrain))-- UsedUsed to to controlcontrol unitsunits likelike dashboarddashboard, , lightinglighting, , airairconditioningconditioning, , windowswindows, , centralcentral lockinglocking, , airbagairbag, , seatseat beltsbeltsetc. (etc. (bodybody controlcontrol))

CAN in CAN in utilityutility vehiclesvehicles-- e.ge.g. . constructionconstruction vehiclesvehicles, , forkliftsforklifts, , tractorstractors etc.etc.-- CAN CAN usedused forfor powerpower traintrain and and hydraulichydraulic controlcontrol......

Application Examples...

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAN in CAN in trainstrains--High High needneed of of datadata exchangeexchange betweenbetween thethe different different electronicelectronic subsystemsubsystem controlcontrol unitsunits--MainlyMainly datadata aboutabout accelerationacceleration, , brakingbraking, , doordoor controlcontrol, , errorerrormessagesmessages etc. etc. butbut also also forfor diagnosisdiagnosis

CAN in CAN in industrialindustrial automationautomation-- ExcellentExcellent way of way of connectingconnecting all all kindskinds of of automationautomationequipmentequipment ((controlcontrol unitsunits, , sensorssensors and and actuatorsactuators))-- UsedUsed forfor initializationinitialization, , programprogram and and parameterparameter upup--/download, /download, exchangeexchange of of ratedrated valuesvalues / / actualactual valuesvalues, , diagnosisdiagnosis etc.etc.--MachineMachine controlcontrol ((printingprinting machinesmachines, paper, paper-- and textile and textile machinesmachines etc.): etc.): ConnectionConnection of of thethe different intelligent different intelligent subsystemssubsystems-- Transport Transport systemssystems

......

...Application Examples...

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAN in CAN in medicalmedical equipmentequipment--Computer Computer tomographstomographs, , XX--rayray machinesmachines, , dentistdentist chairschairs, , wheelwheel chairschairs

CAN in CAN in buildingbuilding automationautomation--HeatingHeating, , airair conditioningconditioning, , lightinglighting, , surveillancesurveillance etc.etc.-- Elevator and Elevator and escalatorescalator controlcontrolCAN in CAN in householdhousehold appliancesappliances--DishwashersDishwashers, , washingwashing machinesmachines, , eveneven coffeecoffee machinesmachines......CAN in CAN in officeoffice automationautomation-- photophoto copiercopier, , interfaceinterface to to documentdocument handlerhandler, , paperpaper feedingfeeding

systemssystems, , sortersorter-- communicatescommunicates statusstatus, , allowsallows in in fieldfield connectionconnection oror "hot "hot swappingswapping""-- DocuTextDocuText Systems, Systems, i.ei.e. . automaticautomatic printprint, , sortsort and bind on and bind on demanddemand

...Application Examples

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



DevelopedDeveloped in in thethe midmid--eightieseighties byby BOSCHBOSCHAsynchronousAsynchronous serialserial busbus withwith linear linear busbus structurestructure and and equalequal nodesnodes (Multi Master (Multi Master busbus))CAN CAN doesdoes notnot addressaddress nodesnodes ((addressaddress informationinformation isisinsideinside thethe messagesmessages combinedcombined withwith messagemessage prioritypriority))TwoTwo busbus statesstates: dominant and : dominant and recessiverecessiveBus Bus logiclogic accordingaccording to "to "WiredWired--ANDAND" " mechanismmechanism::dominant dominant bitsbits (Zeros) (Zeros) overrideoverride recessiverecessive bitsbits ((OnesOnes))Bus Access via CSMA/CD Bus Access via CSMA/CD withwith NDA (NDA (CarrierCarrier Sense Sense Multiple Access/ Multiple Access/ CollisionCollision DetectionDetection withwith NonNon--DestructiveDestructiveArbitrationArbitration))

Some things worth knowing aboutCAN...

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



...Some things worth knowing aboutCAN

NODE A

NODE B

recessive

dominant

recessive

dominantbus idle

CAN BUS

recessive

dominant

Node B sends out recessivebut reads back dominant level

Node B loses arbitrationand switches to receive

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Typical CAN node structure

CAN_H

CAN_L

e.g.SAE81C90

CAN-Transceiver

CAN-Bus

CAN-Controller

Host-Controller

Application

e.g.80C166

e.g.ABS

e.g.C167CR

orC515C

e.g.EMS

Node A Node B

(more nodes)

UDiff

CAN

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



ThereThere areare mainlymainly twotwo waysways of of communicatingcommunicating::--One One nodenode isis ''talkingtalking', all ', all otherother nodesnodes 'listen''listen'-- NodeNode A A isis askingasking NodeNode B B forfor somethingsomething and and getsgets thetheansweranswer..

To 'To 'talktalk', CAN ', CAN nodesnodes useuse DataData FramesFrames..-- A A DataData Frame Frame consistsconsists of an of an IdentifierIdentifier, , thethe datadata to to bebetransmittedandtransmittedand a a CRCCRC--ChecksumChecksum..

CAN Data Frames...

Identifier CRC-FieldData Field (0..8 Bytes)

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



-- TheThe identifieridentifier specifiesspecifies thethe contentscontents of of thethe messagemessage('('engineengine speedspeed', '', 'oiloil temperaturetemperature', etc.) and ', etc.) and thethe messagemessageprioritypriority-- TheThe DataData FieldField containscontains thethe correspondingcorresponding valuevalue('6000 ('6000 rpmrpm', '110°C', etc.)', '110°C', etc.)-- TheThe CyclicCyclic RedundancyRedundancy Check Check isis usedused to to detectdetecttransmissiontransmission errorserrors..-- All All nodesnodes receivereceive thethe DataData Frame. Frame. ThoseThose whowho do do notnot needneedthethe informationinformation, just , just don'tdon't storestore it.it.

...CAN Data Frames

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



To 'To 'askask' ' forfor informationinformation, CAN , CAN nodesnodes useuse RemoteRemote FramesFrames..-- A A RemoteRemote Frame Frame consistsconsists of of thethe IdentifierIdentifier and and thethe CRCCRC--ChecksumChecksum..ItIt containscontains no no datadata..

-- TheThe identifieridentifier containscontains thethe informationinformation thatthat isis requestedrequested('('engineengine speedspeed', '', 'oiloil temperaturetemperature', etc.) and ', etc.) and thethe messagemessageprioritypriority..-- TheThe nodenode thatthat isis supposedsupposed to to provideprovide thethe requestedrequestedinformationinformation((e.ge.g. . thethe sensorsensor forfor thethe oiloil temperaturetemperature) ) doesdoes so so byby sendingsendingthethe correspondingcorresponding DataData Frame (Frame (samesame identifieridentifier, , thethe DataDataFieldField containscontains thethe desireddesired informationinformation).).

CAN Basics...

Identifier CRC-Field

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



...CAN Basics

Data Frame; Identifier 'oil_tmp';contains desired information

~~~~~~~~~~

Remote Frame; Identifier 'oil_tmp'Node ANode B

(oil temp.-sensor)

How hot is the oil ?

115°C115 °C !

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Standard CAN /Extended CAN...

Most CAN Most CAN nodesnodes talktalk in in thethe ''languagelanguage' ' thatthat mostmost otherother CAN CAN nodesnodes understandunderstand: : TheyThey useuse StandardStandard DataData oror RemoteRemoteFramesFrames..-- A Standard Frame A Standard Frame containscontains an an identifieridentifier whichwhich isis 11 11 bitsbits

longlong..--WithWith thisthis 11 11 bitsbits, 2, 21111 (=2048) different (=2048) different messagesmessages cancan bebeaddressedaddressed..-- CAN CAN nodesnodes usingusing StandardStandard--CANCAN--FramesFrames useuse thethe CAN CAN SpecificationSpecification Version 2.0A.Version 2.0A.

SomeSome CAN CAN nodesnodes talktalk withwith a a specialspecial ''accentaccent':':TheyThey useuse ExtendedExtended DataData oror RemoteRemote FramesFrames..-- An An ExtendedExtended Frame Frame containscontains an an identifieridentifier whichwhich isis 29 29 bitsbits

longlong..-- ......

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



...Standart CAN /Extended CAN...

--OverOver 536 536 millionmillion (2(22929) different ) different messagesmessages cancan bebeaddressedaddressed..-- CAN CAN nodesnodes usingusing ExtendedExtended--CANCAN--FramesFrames useuse thethe CAN CAN SpecificationSpecification Version 2.0B (Version 2.0B (activeactive).).

SomeSome StandardStandard--CANCAN nodesnodes don'tdon't understandunderstand thisthis ''accentaccent', ', butbut theythey toleratetolerate itit and just and just don'tdon't carecare..-- IfIf an an ExtendedExtended Frame Frame isis 'on 'on thethe airair', ', thesethese CAN CAN nodesnodes

cannotcannot storestore thethe datadata, , butbut theythey as well do as well do notnot produceproduceerrorserrors..-- These CAN These CAN nodesnodes useuse CAN Version 2.0A, CAN Version 2.0A, butbut areare also also knownknown as Version 2.0B passive.as Version 2.0B passive.-- TheyThey cancan bebe usedused in a Controller in a Controller AreaArea NetworkNetwork wherewhereExtendedExtended FramesFrames areare usedused..

......

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



...Standart CAN /Extended CAN

SomeSome StandardStandard--CANCAN nodesnodes don'tdon't understandunderstand and also and also don'tdon't toleratetolerate thisthis ''accentaccent'. '. -- IfIf an an ExtendedExtended Frame Frame isis 'on 'on thethe airair', ', thesethese CAN CAN nodesnodes

produceproduce errorserrors..-- These CAN These CAN nodesnodes useuse onlyonly CAN Version 2.0A.CAN Version 2.0A.-- TheyThey cancan notnot bebe usedused in a Controller in a Controller AreaArea NetworkNetwork wherewhereExtendedExtended FramesFrames areare usedused..

16 16 bitbit partsparts: : C167CR, C164CIC167CR, C164CI: V2.0B : V2.0B activeactive

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Basic CAN /Full CAN...

In In somesome CAN CAN controllerscontrollers, , onlyonly thethe basicbasic CAN CAN functionsfunctions areareimplementedimplemented. . TheyThey areare calledcalled BasicBasic--CANCAN controllerscontrollers..--MostlyMostly there'sthere's onlyonly oneone transmittransmit bufferbuffer and and oneone oror twotwo

receivereceive buffersbuffers forfor transmissiontransmission and and receptionreception of of thethe DataData-- / / RemoteRemote FramesFrames..-- EachEach incomingincoming messagemessage isis storedstored. . TheThe hosthost CPU has to CPU has to decidedecide whetherwhether thethe messagemessage datadata isis neededneeded oror not.not.-- ThereforeTherefore thesethese controllerscontrollers shouldshould onlyonly bebe usedused in in CANsCANswithwith veryvery lowlow baudratesbaudrates and/and/oror veryvery fewfew messagesmessagesbecausebecause of of thethe high CPU high CPU loadload. Advantage: . Advantage: TheyThey useuse thetheleast least possiblepossible siliconsilicon areaarea..

...... ReceivedMessages

Receive Buffer

CAN Bus

Host CPU

Transmit Buffer

CPU load

low high

Basic-CAN Controller

Messagesto be sent

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



...Basic CAN /Full CAN...

In In thethe otherother CAN CAN controllerscontrollers, also , also messagemessage managementmanagementand and acceptanceacceptance filteringfiltering areare implementedimplemented. . TheyThey areare calledcalledFullFull--CANCAN controllerscontrollers..-- ThereThere areare severalseveral MessageMessage ObjectsObjects, , eacheach withwith itsits ownown

identifieridentifier..-- OnlyOnly ifif a a messagemessage forfor oneone of of thesethese preprogrammedpreprogrammedidentifieridentifier isis receivedreceived, , itit isis storedstored and and thethe CPU CPU isis interruptedinterrupted..-- In In thisthis way, way, thethe CPU CPU loadload isis lowlow..

......

Full-CAN Controller

Message Object 2CAN Bus

Host CPU

Message Object n CPU load

low high

Message Object 1

.

.

Accep-tance

Filtering

MessageManage-

ment

☺

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



...Basic CAN /Full CAN

All SiemensAll Siemens CANCAN--Controllers Controllers areare FullFull--CANCAN controllerscontrollers..ButBut theythey alsoalso provideprovide BasicBasic--CANCAN functionalityfunctionality-- oneone messagemessage objectobject cancan bebe usedused likelike a Basic CAN a Basic CAN receivereceive

registerregister

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Features of the CAN Module onC167CR / C164CI...

19

FunctionalityFunctionality correspondscorresponds to to AN 82527AN 82527CompliesComplies withwith CAN CAN specspecV2.0B V2.0B activeactive(Standard(Standard-- und und ExtendedExtended--CANCAN))Maximum CAN Transfer RateMaximum CAN Transfer Rate(1 MBit/s)(1 MBit/s)Full CAN Full CAN DeviceDevice-- 15 15 MessageMessage ObjectsObjects withwith

theirtheir ownown identifieridentifier and and theirtheirownown statusstatus-- and and controlcontrol bitsbits-- EachEach MessageMessage ObjectObject cancanbebe defineddefinedas as TransmitTransmit-- oror ReceiveReceiveObjectObject

......

CAN ModuleCAN Module

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Connecting the to CAN

19

CAN-BusTransceiver

Receive

TransmitCAN_H

CAN_L

P4.5

P4.6

CAN_L

P2.0

Pa.b

Pc.d

C167CR/C161CI

CAN_H CAN_RxD

CAN_TxD

R(opt)(Standby)

Vref

n.c.

Connectionto the

Application

CAN ModuleCAN Module

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Watchdog Timer(WDT) at 20 MHz

1616--Bit Bit timertimer overflowoverflow resultsresults in:in:-- Software Software resetreset-- PullsPulls RSTOUT Pin RSTOUT Pin lowlow-- Sets Sets identificationidentification bitbit and and leavesleaves WDT WDT enabledenabledProgrammableProgrammable inputinput clockclockHigh Byte High Byte reloadreload registerregisterTimer Timer periodperiod fromfrom 25.6µs to 470ms25.6µs to 470msCanCan bebe reloadedreloaded withwith a a specialspecial instructioninstruction

WatchdogWatchdog22

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



serviceWDT

8-bitreload zero

RSTOUT

SoftwareReset

16-bit Timerhigh Byte low Byte

WDT control

CPU CLK / 2 onoverflow

WDTBlock Diagram

CPU CLK / 128

22WatchdogWatchdog

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Overview Port Structure

TheThe Port Port lineslines provideprovide thethe connectionconnection to to thethe externalexternal worldworld-- 77 Port 77 Port lineslines on on thethe SAB 80C166SAB 80C166-- 111 Port 111 Port lineslines on on thethe C167C167-- 77 Port 77 Port lineslines on on thethe C165/C163C165/C163-- 59 Port 59 Port lineslines on on thethe C164C164-- 64 Port 64 Port lineslines on on thethe C161V/K/OC161V/K/O-- 77 Port 77 Port lineslines on on thethe C161RIC161RIAll Port All Port lineslines areare individuallyindividually addressableaddressable and all I/0 and all I/0 lineslinesareare independentlyindependently programmableprogrammable forfor inputinput oror outputoutputEachEach Port Port lineline isis dedicateddedicated to to oneone oror moremore peripheralperipheralfunctionsfunctionsEachEach Port Port isis protectedprotected withwith fast fast diodesdiodesProgrammableProgrammable openopen draindrain buffersbuffers-- P2, 3, 6, 7, 8 on P2, 3, 6, 7, 8 on thethe C167C167-- P3, 8 on P3, 8 on thethe C164C164

PortsPorts25

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



DirectionRegister

OutputLatch

AlternateOutput

AlternateEnable

Read Direction

Write

ClockAlternate Input

Inte

rnal

Bus

Overview Port Structure

Buffer

Mux

Mux

Buffer

InputLatch

Open DrainControl

25PortsPorts

VCC

Vss

Port Pin

ESD structure

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



WDTOSC.PEC

CPUROM /

RAM

PORTS

CAPCOM

ADCBusExt.

Processor -System

Interrupt-System

USART GPTs

Peripheral-System

Flash

Control

X-BusSync Communication PWMPeriphrl.

SummarySummary

The Summary of the C166 Family

26

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



High High ComputationalComputational Power: min 80ns Power: min 80ns InstructionInstruction CycleCycleTimeTime-- Fast Fast algorithmsalgorithms ((shortshort samplesample timestimes forfor closedclosed looploop controlcontrol))-- Fast Fast tasktask executionexecutionControlControl OrientedOriented InstructionInstruction SetSet-- BooleanBoolean processingprocessing / / bitbit--handlinghandling and and processingprocessing-- TaskTask switchswitch / / powerpower savingsavingGeneral General PurposePurpose Register Register OrientedOriented ArchitectureArchitecture--ManagingManaging of multiple quasiof multiple quasi--parallel parallel taskstasksPowerfulPowerful AddressingAddressing CapabilitiesCapabilities-- Large Large addressaddress rangerange and and powerfulpowerful addressingaddressing modesmodes

(HLL)(HLL)OnOn--chipchip RAM, OTP/ROM/FlashRAM, OTP/ROM/Flash-- For For veryvery fast fast MemoryMemory AccessAccess-- InIn--System System reprogrammablereprogrammable Flash Flash MemoryMemory-- oneone--timetime programmableprogrammable ROMROM

Processor System

26SummarySummary

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



ExtremelyExtremely Short Short InterruptInterrupt Response TimeResponse Timeof of typicallytypically min. 320nsmin. 320ns-- InterruptInterrupt executionexecution in in smallsmall time time segmentssegments-- EnsuresEnsures highesthighest realreal--timetime performanceperformanceComprehensiveComprehensive PrioritizationPrioritization SchemeScheme-- EasyEasy schedulingscheduling of of complexcomplex realreal--timetime systemssystems byby usingusing up up

to 64 to 64 PriorityPriority levelslevels (4 (4 groupsgroups withinwithin 16 16 levelslevels))CPUCPU--IndependentIndependent InterruptInterrupt Service via Service via PeripheralPeripheral Events Events Controller (PEC)Controller (PEC)--OffOff--loadsloads thethe CPU CPU fromfrom simple simple butbut frequentfrequent interruptinterrupt--

servicesservices-- InterruptInterrupt--drivendriven ““DMADMA--likelike” ” datadata transfertransfer, , withoutwithout tasktaskswitchswitch of CPUof CPU--MakesMakes peripheralperipheral datadata transferstransfers independent independent of of runningrunning CPU CPU routineroutine

Interrupt System

26SummarySummary

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



MultiMulti--functionalfunctional Timer/Timer/CounterCounter UnitsUnits (up to 5 Timers / (up to 5 Timers / CountersCounters) ) withwith ComplexComplex ConcatenationConcatenation PossiblePossibleComprehensiveComprehensive up up tptp 32 32 ChannelChannel CaptureCapture//CompareCompare Unit Unit withwith up to 4 up to 4 AllocatableAllocatable TimeTime--BasesBasesCaptureCapture//CompareCompare unitunit (CAPCOM6) (CAPCOM6) forfor flexible PWM Signal Generationflexible PWM Signal Generation4 high 4 high resolutionresolution PWM PWM channelschannelsup to 10up to 10--bit bit MultiMulti--FunctionalFunctional A/A/DD--ConverterConverter forfor Fast Fast DataDataAcquisitionAcquisition in in ControlControl SystemsSystems

Peripheral System

26SummarySummary

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



BiBi--directionaldirectional, , ProtectedProtected and and IndividuallyIndividually ProgrammableProgrammableExternalExternal PortPort--LinesLinesSerialSerial CommunicationCommunication InterfacesInterfaces-- Standard Standard asynchronousasynchronous communicationcommunication-- Fast Fast synchronoussynchronous communicationcommunication in masterin master-- & & slaveslave--modemode

(SPI)(SPI)EasyEasy Adaptation to Special Adaptation to Special ApplicationApplication oror CustomerCustomerRequirementsRequirements via via InternalInternal XX--BUS BUS ArchitectureArchitecture--CANCAN--Bus, Profibus, SSP, etc.Bus, Profibus, SSP, etc.flexible Power Managementflexible Power Management

Peripheral System

26SummarySummary

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



2-chip Emulation Technology

One One BondoutBondout chipchip supportssupports emulationemulation of all of all relatedrelatedderivativesderivatives, , newnew oror existingexisting ((i.ei.e. C167, C165, C163, C161). C167, C165, C163, C161)New New XX--PeripheralsPeripherals ((XPERsXPERs) ) areare emulatedemulated usingusing thethestandardstandard chipchipIn In emulationemulation mode mode thethe standardstandard IC IC isis sleepingsleeping and and onlyonly thetheXPER XPER isis activeactive. . TheThe BondoutBondout chipchip has has fullfull accessaccess to to thetheXPER XPER overover a a particularparticular portportNo No needneed forfor BondoutBondout redesignredesignUser has User has fullfull emulationemulation controlcontrol overover thethe XPER XPER withoutwithout anyanyintrusionintrusion of of realreal--timetimeFull Full accessaccess to to targettarget systemsystem isis maintainedmaintainedSupportedSupported byby all all majormajor tooltool manufacturersmanufacturers

DevelopmentDevelopment ToolsTools27

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



2-chip Emulation Technology

ROMRAM

Standard Peripherals & I/O

GPT CAPCOM ...

I/O

Port0 Port1 Port4

External Bus Interface

P6

CPUCORE

Bus Contr. PORT

PORT

RAMBUS BUS

P-Bus

X-Bus

to User Application

Sim.ROM

to User Application

Port0 Port1 Port4

External Bus Interface

P6

RAM

Standard Peripherals & I/O

GPT CAPCOM ...

I/O

CPUCORE

Bus Contr.

RAMBUS

P-Bus

ROM /FLASH

X-Bus

XPER

XPERI/O

ROM

BUS

CS#

XPER-Interrupts

X-Bus

to UserApplication

Standardchip

Bondoutchip

DevelopmentDevelopment ToolsTools27

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Sockets / AdaptersYamaichi ET

EMULATION TECHNOLOGY, INC.

DevelopmentDevelopment ToolsTools

KEILSoftware

Debuggerspls

TASKING

Evaluation Boards

KEILSoftware

PHYTEC

RIGELHIGHTEC

ertecertecpls

KEILSoftware

Compilers, Assemblers

HIGHTECTASKING

Flash Programmers

ertecertecCEIBO

hitexpls

CAN/FUZZYi+ME

INFORMstzpMicroFuzzy

RTOS

KEILSoftware CMX

Company

HIGHTECtecsi

WindRiverSystems

Emulators

hitex LAUTERBACH

YOKOGAWA

KONTRON ELEKTRONIK

Major Tool Partners

TektronixdliLogic Analyzers

HEWLETTPACKARD

Simulators

KEILSoftware

hitexTASKING

27

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



• Robotics• PLC’s• Servo-Drives• Motor Control• Power-Inverters• Machine-Tool

Control (CNC)

• EngineManagement

• Transmission Control

• ABS/ASK• Active

Suspension

Automotive Industrial Control

• DVD / CD-ROM• TV / Monitor• VCR / Sat

Receiver• Set Top Box• Games• Video

Surveillance

Telecom/ Datacom

• CommunicationBoards (LAN)

• Modems• PBX• Mobile

Communication

EDP

• Hard Disk Drives

• Tape Drives• Printers• Scanners• Digital Copiers• FAX Machines

Consumer

Applications for the C166 Family

C166 C166 FamilyFamily

WDTOSC. PEC

CPUROM /

RAM

PORTS

CAPCOMADCBus

Ext.

Processor -System

Interrupt-SystemUSART GPTs

Peripheral-System

Flash

ControlX-Bus

Sync Communication PWMPeriphrl.

28

Documents

C166 Family-High Performance 16-Bit Microcontrollersalt.ife.tugraz.at/LV/upprog/Pdfs/Fol167.pdf · C167 HL MC AT, lehmann ... * 10-bit / 8bit ADC * full Bus Support/ MUX Bus only