C55x - perso.esiee.fr

1

ESIEE/SIGTEL - 2006-2007 1

C55x

Processeurs de Traitement du Signal


Système de traitement numérique avec DSP

Monde physique

Cap

teur

s

CAN

CNA

AffichageApplicatifDialogue HM

DSPTraitementet/ouinterprétation

Traitementconditionnementanalogique Activation

Act

ionn

eurs

Protocole

Protocole

2


What Problem Are We Trying To Solve?

Digital sampling of an analog signal:

A

t

Most DSP algorithms can be expressed with MAC:

count

i = 1Y = ΣΣΣΣ ai * x i

for (i = 1; i < count; i++){sum += m[i] * n[i]; }

DACx Y

ADC DSP

Technical TrainingOrganization

T TO


C55x CPU Block Diagram160Mhz-200Mhz• 16Mx8 Unified Memory

Space

• C5510 – 160KW RAM

• 23-bit Addr Regs

• Two ALUs (16-, 40-bit)

• Dual-MAC

• 4x40-bit ACC’s

• 4 Temp Regs

• Variable-length Instr

• 64x8 Instruction Buffer

• “Local” repeat block

• Dual-level RPT blocks

• Multiple Circular Buffers

• Built-in + User-definedparallel instructions

• Pipeline ProtectionUnit (PPU)

3


Package


Low

po

wer

4


C55x Architecture (10km view)

Data Read Buses (D, B, C)

Program A/D Bus

Data Write Buses (E, F)

PC MAC MAC

AC0

AC1

InstrBufferQueue

Decode

IU PU AU DU

ARn CDPAddr

Gen

MAC *AR2+, *CDP+, AC0 :: MAC *AR3+, *CDP+, AC1Technical TrainingOrganization

T TO


Program and Instruction UnitsPC

RETA

PU

Status RegistersProgram Flow

PPUInterrupts

� 4-byte packet fetchedevery cycle

� Variable-length instruction set(8, 16, 24, 32, 40, 48-bit)

InstructionBuffer64 x 8

Decoder

PU AU DU

48

IUProg Addr Gen

FF_FFFF

00_0000

External

Internal PDB[32]

PAB[24]

Now, the A-unit...


T TO

5


Addressing Unit (AU)


T TO

ARAU

CDP

DP

AR0-7

AU

ALU/Shft

T0T1T2T3

16-bit

StackPointers

23/16-bit

CircularBuffers

23/16-bit

� Where else could the data go?...

Addr

Gen

BAB[24]

CAB[24]

DAB[24]

CB[16]

DB[16]

� A-Unit handles all dataaddressing

FF_FFFF

00_0000X

X

X

First 64KW Pg 0

Last 64KW Pg 127

� Xreg: 23 bits, reg: 16 bits


Data Computation Unit (DU)

DU� D-Unit executes most

mathematical operations

40-bit

MAC MAC

AC0AC1AC2AC3

40-bitALUShift

Viterbi HardwareTransition Regs

Bit Operations

BB[16]

CB[16]

DB[16]

� Now, what happens to the result?...

FF_FFFF

00_0000

External

Internal


T TO

6


Writes (E and F buses)

AU

� 32-bit write in one cycle

EAB[24]

FAB[24]

FB[16]

EB[16]

FF_FFFF

00_0000

External

Internal

AC0AC1AC0AC1

DU

AC2AC3


T TO


Principe du pipeline

Temps t t+1 t+2 t+3 t+4 t+5 t+6instruct ions

n F D R En+1 F D R En+2 F D R En+3 F D R E

7


Instruction Fetch PacketPipeline

PU

� Fetch-packet pipeline fetches 4-byte packetsfrom programmemory INTO the IBQ every cycle (unless IBQ is full)

� Fetch packet pipeline operates independentlyfrom execute pipeline

IU AU DU

Data Read Buses (B,C,D)A

DData Write Buses (E,F)

Program Bus

EMIF

IBQ

64x8

PF1 PF2 F

PF1

PF1

PF2

PF2

F

FF - fetch 4-byte packetPF2 PF1 - gen prog address

4 bytes- memory wait


T TO


ExecutePipelineD AD AC1AC2 R X W

D AD AC1AC2 R X W

D

D

D

D

D

AD

AD

AD

AD

AD

AC1AC2 R X W

AC1AC2 R X W

AC1AC2 R X W

AC1AC2 R X W

AC1AC2 R X WW - write to memoryX - execute

D - decode opcode

IBQ

64x8 1-6bytes

� IU performs fetch/decode from IBQ

� AU generates operand addresses

� AU/DU execute instructions

� X: result to registerW: result to memory

� Execute pipeline fetches instructionsFROM the IBQ, then executes them

IU AU DU

Data Read Buses (B,C,D)

Data Write Buses (E,F)

A

D

EMIF

AD - compute addressAC1 - gen read addressAC2 - memory waitR - read operands


T TO

8


Cache - Introduction� A cache is a “buffer of the most recent instructions

accessed by the CPU”� Without a cache, the CPU always fetches instruction s from

external or internal memory:

� With a cache, the CPU first checks to see if the in struction is“in the cache”.

CPUInternal

or External

Memory

RAM

Control

Cache

“hit” “miss”

� YES: “hit” - fetch from cache� NO: “miss” - fetch from ext’l mem, send it to the CPU AND the cache.

Find the “least recently used” location, put the ne w instr there.


T TO


Architetcure mémoire

�Mode d’accès :–orienté registre ou mémoire

�Hiérarchie mémoire :–à plat

–à un niveau

–à deux niveaux

�Agilité donnée :–instruction

–data

Accumulator architecture

Load-store architecture

register file

on-chip memory

9


Architecture harvard modifiée

PROGRAMME /

DONNEES

DONNEESCACHE


C5510 Memory Resources

� Internal : up to 6 accesses per cycle; External : up to 32-bits per cycle

� Manage your resource (code/data) placement wisely t o avoidunnecessary memory delays

DARAM

8 8Kx8

ROM

32Kx8

SARAM

32 8Kx8

Async

SBSRAM

SDRAM

x

Minimum #cyclesto access resource:

2 1

2

1

1

12

D Bus

C Bus

B Bus (internal only)

P Bus

E Bus

F Bus

Internal Buses

E

M

I

F

A

D


T TO

10


C5510 Unified Memory Map

A(24)

D(32)

C55xx core

Internal00_00C0

01_0000

05_0000

MMRs

DARAM (32KW)

SARAM (128KW)

External

Program Data � Program and data sharethe same map

1. Program - (Bytes)

- 16M x 8-bit, linear 24-bitaddresses

- Used by fetch/decode logic

2. Data (Words)

- 8M x 16-bit, segmented into64K pages, 23-bit address

- Most code written by a userwill access data

� 2 ways to view the map:

FF_FFFF

00_0060

00_8000

02_8000

7F_FFFF

00_0000 00_0000

23 0Prog

023 01

Data


T TO


C5510 Peripheral Overview

EHPI- 16-bit host access to memory

DMA- 6 Channels

EMIF- Access to EPROM, SRAM,SBSRAM, SDRAM

BOOT Loader- From external mem, Host, McBSP

3 Multi-Channel Buffered SPs- High speed sync serial comm

General Purpose I/O- 8-bit i/o port

Timer/Counters- Two 20-bit timer/counters

Power-Down Modes

Instruction Cache (24K bytes)

55xxCPU

‘C5510

ExternalMemory

EMIF

DMA

Boot

EHPIHost MCBSP

Timers

Power

GPIO

Cache


T TO

11


What is the problem to solve (1)

Data Read Buses

Amplitude

x4 x3 x2 x1 x0

Time

Data Read Buses

Amplitude

x4 x3 x2 x1 x0

TimeALU

Data Read Buses

Amplitude

x4 x3 x2 x0

Time

z = x4 + x3 + x2 + x1

ALU

Acc A

ADD @x, A ...

� Single-cycle ADD


T TO

x1

x2

x3

x4

data

@x:


What is the problem to solve (2)

Data Read Buses

� Single-cycle MAC

∑ anxn

3

n = 0y0 =

Amplitude

x4 x3 x2 x1 x0

TimeMAC

A

MAC *AR2+, *AR3+, A

Data Read Buses


Data Read Buses



T TO

a0

a1

a2

a3

coef

y0 = a0 x0 + a1 x1 + a2 x2 + a3 x3

x0

x1

x2

x3

data

12


With the C55x dual MAC

AAC0

AC1

tMAC

Data Read Buses

� 2 taps/cycle

::

Amplitude

x4 x3 x2 x1 x0

Time

C55x: MAC *AR2+, *CDP+, AC0 MAC *AR3+, *CDP+, AC1

Data

y0 = a0x0 + a1x1 + a2x2 + a3x3

y1 = a0x1 + a1x2 + a2x3 + a3x4

Results

MAC


T TO

a0

a1

a2

a3

coef

x0

x1

x2

x3

data

x1

x2

x3

x4


Managing Your Resources

Data

Code

CoeffsDARAM SARAM External

?

� Given these mem resources/dual-MAC operation, where shouldyou place data/coeffs/code to achieve single-cycle performance?

DATA

COEFFS

CODE

_______

_______

_______


T TO

DARAM

SARAM

Any

13


Dual MACy0 = a0x0 + a1x1 + a2x2 + a3x3

y1 = a0x1 + a1x2 + a2x3 + a3x4 MAC *AR3+, *CDP+, AC1

::MAC *AR2+, *CDP+, AC0

AC0

AC1

BCD

CDP AR2 AR3

MAC MAC

� Uses 3 buses vs. 4 (saves power)

� Common coefficient (eg. a0) allowsprocessing 2 taps in a single cycle:

� CDP updated once/instruction

� Coefficients must be placed ininternal memory (B bus)

� 2 taps of a single stream� 1 tap each of 2 streams� Ex: mono or stereo streams

Where should we place our data/coeffs to maximize pe rformance?Technical Training

Organization

T TO


C55x-Specific Memory Mgmt Hints/Tips

� Follow these guidelines when managing your memory:� Stacks (SP/SSP) �� DARAM (2 accesses/cycle)

� Data buffers �� DARAM (for dual-MAC, requires 2 access/cycle)

� Input/output buffers in separate 8K blocks of DARAM (pipeline)

� Most frequently used ISRs/code �� SARAM or RAMSET

� Must choose between code/data in internal RAM? Choo se data.(more internal data buses, I-cache can handle exter nal code)

� Init code �� External Memory


T TO

14


Techniques d’adressage

∑−

=

−=1

0

][][][N

k

knxkhny

z-1z-1 z-1

][nx ]1[ −nx ]2[ −nx

]0[h ]1[h

Coefficients

Data


Accessing data memory: addressing mode


T TO

– Direct : random access from a base address

– Indirect : use registers (ARx,CDP) as pointers

– Absolute : specify entire 23-bit address

– MMR : read/write Memory Mapped Registers

– Immediate : Loading constants in registers

– Bit : Set/clear status bits

y = x0 + x1 + x2+ x3

Algorithm

RAM

x[4]

RAM

y

I P

D A

55xxCPU

System Diagram

ROM

tbl[4]

y = x0+x1+x2+x3

This algorithm will again be used as an example for the different addressing modes.

15


Direct addressing - @

x .usect “vars”,4y .usect “vars”,1

.sect “init”tbl .int 1,2,3,4

.sect “code”

RAM

x[4]

RAM

y

I P

D A

55xxCPU

System Diagram

ROM

tbl[4]

y = x0+x1+x2+x3

7-bit @x

=

+

23-bit address

16-bit DP23-bit XDP

X

ADD: MOV @(x+0),AC0ADD @(x+1),AC0ADD @(x+2),AC0ADD @(x+3),AC0

•XDP[22:16]selects 64K page•DP: Data Pointer•@: 7 bit positive offset (CPLST1=0)

AMOV #x,XDP.dp x


T TO


Indirect addressing - *

= 23-bit address

16-bit ARn23-bit XARn

X

•XARn: specifies entire 23-bit address•XARn[22:16] selects 64K Data Page•ARn: 16-bit pointers (AR0-7)

RAM

x[4]

RAM

y

I P

D A

55xxCPU

System Diagram

ROM

tbl[4]

y = x0+x1+x2+x3

x .usect “vars”,4y .usect “vars”,1

.sect “init”tbl .int 1,2,3,4

.sect “code”


AMOV #x,XDP.dp x

AMOV #x,XAR0AMOV #tbl,XAR6

copy: MOV *AR6+,*AR0+MOV *AR6+,*AR0+MOV *AR6+,*AR0+MOV *AR6+,*AR0+

16


Options for Pointer AriModification

*ARn(T0/1) No Modify w/offset *ARn(#k16) No Modify w/offset *(ARn +/- T0/1) Post Modify (+/- by T0/1) *+/- ARn (+/-) Pre Modify *+ ARn(#k16) (+ #k16) Pre Modify *(ARn +/- T0B) Bit reversed using T0 *CDP No Modify *CDP(#k16) No Modify w/offset *CDP +/- Post Modify (+/-) *+CDP(#k16) (+ #k16) Pre Modify

*ARn No Modify *ARn + /- Post Modify (+/-)

�Assumes ST2_55ARMS=0 and ST1_55C54CM=0.

�CDP Coefficient Data Pointer Technical Training

Organization

T TO


MMR Addressing - mmap()


T TO

; write #1234h to ST0_55AMOV #0,XDPMOV #1234h, @(ST0_55 - 0)

; write #1234h to ST0_55MOV #1234h, mmap(@ST0_55)

OR

� MMRs are located between 0 and 5F.

� mmap() forces bits 22:7 to zero.

� Useful only for direct addressing @

� Scratch memory is located between 60 and 7F.

IER0IFR0

ST0_55ST1_55

.

.

.Scratch

Pad RAM

0_00000_00010_00020_00030_0004

0_005F0_00600_007F

@(.-x) ⇔⇔⇔⇔ .dp x

Memory MapRegisters

17


Absolute addressing

STORE: MOV AC0,*(#y)


• *(#) = 23 bit address

• Fast: no initialization,

• But long instruction because it contains the 23 bit address.

• If the address is in the 64K work page, it is possible to specify a 16-bit only address: abs16*(#label)

= 23-bit address

*(#y)


T TO


Access peripheral register – port()

abs: MOV port(#addr),T1

dir: MOV #addr,PDPMOV T1,port(@addr)

indir: AMOV #addr,AR4MOV port(*AR4),T1

0000h

FFFFh

I/O - PeripheralMemory Map

DMA

McBSP

EHPI

EMIF

Timers

Power Dwn

Instr Cache

GPIO

@7bit9bits PDP

�The port() modifier selects the peripheral map

�The I/O space is internal.

�Direct adressing uses PDP register


T TO

18


Memory Outline


T TO

� Managing External Memory� Asynchronous (Flash, SRAM)� Synchronous (SBSRAM, SDRAM)� Instruction Cache

� Managing Internal Memory� Internal Memory Resources� Getting a single-cycle dual-MAC� Pipeline Performance

� Customizing Your Memory Mgmt� Creating custom sections, memory areas� Creating a user linker command file� Overall hints/tips for C55x memory mgmt


Addressing Exemple

x = 02_0106h02_0107h02_0108h

02_0209h XDP30h40h50h

90h

XAR1

T0 2

02_0106h

02_0106h

.dp x

AR1 AC0 T1 02_0106h ST1 M40

MOV @(x+1),AC0MOV @(x+80h),AC0MOV T0,*AR1+MOV *(#x),AC0MOV #4,@(x+128)MOV *(AR1+T0),T1BSET M40 MOV @(x+2),AC0MOV *AR1(T0),AC0MOV *AR1(#100h),T1MOV @(x+129),AR1MOV *+AR1(#-1),AC0

40h30h

107h 230h

4109h 40h

150h

109h 80h109h 90h

40h39h 21h

02_010Bh 80h02_003Fh 21h

19


Data Formats and Numerical Issues

• Common data sizes: 8, 16, 24, 32 bits

• Fixed or floating point

• For a given technology:– Fixed point is faster and less expensive

– But fixed point programming is more difficult

• Processors of the ‘C5000 family are fixed point processors . – 2’s Complement


Binary RepresentationsPositive integers

Positive integers

Signed integers

Signed integers

Signed integers

Signed integers

decimal Binary DecimalOffset binary

DecimalSign +

magnitude7 1 1 1 3 1 1 1 3 0 1 16 1 1 0 2 1 1 0 2 0 1 05 1 0 1 1 1 0 1 1 0 0 14 1 0 0 0 1 0 0 0 0 0 03 0 1 1 -1 0 1 1 0 1 0 02 0 1 0 -2 0 1 0 -1 1 0 11 0 0 1 -3 0 0 1 -2 1 1 00 0 0 0 -4 0 0 0 -3 1 1 1

Weights22 21 20

20


Binary Representations

Signed integers Signed integers Signed integers

Decimal 1's complement 2's complement

3 0 1 1 0 1 12 0 1 0 0 1 01 0 0 1 0 0 10 0 0 0 or 1 1 1 0 0 0-1 1 1 0 1 1 1-2 1 0 1 1 1 0-3 1 0 0 1 0 1-4 1 0 0

Ny 2 x 1= − − Ny 2 x= −


Non-Integer Numbers

• Format Qk : k fractional bits associated with negative power of 2.

• The binary representation of a number x in formatQk is the 2’s complement representation of the integer y:

y xk= 2

Fractional PartInteger Part

N 1 k 1 0 1 kb b b b b,− − − −

6447448 64748L L

1 2 11 2 0 12 2 2 2N k N k k

N k N k kx b b b b b− − − − − −− − − − − −= − + + + +L L

21


Entiers relatifs Cà2

N 1 k 0

N 1k

kk 0

N 1N k

kk 0

N 2N 1 k

N 1 kk 0

x b b b

x 0 x b 2

x 0 y 2 x e t y b 2

x 2 b b 2

−

−

=

−

=

−−

−=

→

≥ ⇒ =

< ⇒ = − =

= − +

∑

∑

∑

L L


Some Properties of2’s Complement Representation

N 1

N-1

N 1 N 1 N 1

Max number=2 1

Min number=-2

Circular Representation: (OVM, SATD)

(2 1) 1 2 2

Sign bit Extension: (SXM, SXMD)

−

− − −

−

− + = ⇔ −

22


Circularité

1

2

3-4

-3

-2

0-1

OV=1

Retenue : Carry

111+ 111--------1 110

010+ 001--------0 011

110+ 011--------1 001

110+ 001--------0 111

Débordements(intermédiaires)


Sign Bit Extension• Example data size 6 bits, Accumulator size 12 bits

1 0 1 0 0 1

1 0 1 0 0 1

1 0 1 0 0 1

1 1 1 1 1 1

0 0 0 0 0 0

Data

Loading of ACCU with sign extension

Loading of ACCU without sign extension

23


Saturation and Overflow• Overflows in 2’s complement create

unexpected sign changes and peaks that are difficult to filter.

• Saturation arithmetic detects the overflow and replaces the result with a saturation value.

0 0.2 0.4 0.6 0.8 1-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Saturation at 0.75

2’s complement overflow

Example, max value = 0.75


Saturation and overflow

0

-1

1 128

-128

AC0 SAT AC0

Two saturation methods exist:

� Manual: using the SAT instruction (ACx only)

� Auto: using the SATA/SATD or OVM control bits

� SATA affects TAx registers (T0-3/AR0-7) in A unit ex: 7FFFh + 2 = 7FFFh

ex: 8001h - 3 = 8000h

� SATD affects AC0-3 registers in D unit (ST1_55 M40 = 0) 00.7FFF.FFFF or FF.8000.0000

(ST1_55 M40 = 1) 7F.FFFF.FFFF or 80.0000.0000

- Affects ST0_55ACxOV and can be tested

24


Operations with Fractional Numbers using Fixed Point Format

• Addition: align on same size N and align bits with same weight.

• Multiplication: product requires 2N bits

k k kQ Q Q+ ⇒

k k' k k'Q Q Q+× ⇒


Accumulator and size of the result

• The final result of a calculation usually uses more than 16 bits (size of memory words).

• ACCUs use 32, 40, 56 ... Bits

• If we want to save the result in a single memory word, the question is:

• Which pack of N bits must be saved from accumulator?– Possibility of overflow and underflow

– Overflow during accumulation or during saving.

25


ACCUMULATOR

• Possibility of overflow and underflow

• Scaling when adding many products

16 bits to save

0 15 16 31 32 39

Guard bi ts ACCU High ACCU Low


Example of Fixed Point Processing y(n)=x(n)+a1y(n-1)

• Data size N=16, product size 32 bits, accumulator size 40 bits

• The coefficient a1 is smaller than 1: format Q15. Format of data = Q15, y(n) smaller than 1 by assumption. Accumulator size 40bits

Accumulator01516313239

aa11yy((nn--11)),, QQ3300

01516313239

++ xx((nn)),, QQ1155

16 bits to save

015163132

aa11yy((nn--11)),, QQ3300

yy((nn)),, QQ115539

26


Rounding$ 1.53$ 0.50$ 2.03$ 2.

How do you round this amount to the nearest $ ?- Add $0.50

� Biased Rounding (ST2_55RDM = 0) or round to the infinite- Direct: ROUND AC0

- Store: MOV uns(rnd(HI(saturate(AC0)))),*AR1

� rnd() and ROUNDperform the following operation:(add 1 to bit 15) and (truncate)(ACx+0x8000) & 0xFFFF0000

- Partial result- Truncate result (to nearest $)

• Instructions RND in C54 DSPs or ROUND in C55 DSPs, rounds the content of the accumulator.

• For the C55, 2 kinds of rounding: biaised or unbiaised, depending on the bit RDM in ST2_55.


C- asm interfacey = func(1,2,3,4,5);

� The compiler will scan the parameters (from left to right)and place them into the following registers (from l eft to right):

� The registers are filled in the order shown:

� All parameters that don’t find a home in a register , areplaced on the stack (SP).

16-bit Integers Pointers Longs

T0-1, AR0-4 XAR0-4 AC0-2

� Return values: 16/32-bit placed in T0/AC0 respectiv ely


T TO

� T0 gets the first 16-bit int, T1 gets the 2nd, etc.

� XAR0 gets the first pointer if available, etc.

� 32-bit values are passed in AC0-2

27


DSK 5510


C5510 DSK Memory Resources

� Internal : up to 6 accesses per cycle; External : max = 32-bits/cycle

� Manage your resource (code/data) placement wisely t o avoidunnecessary memory delays

DARAM

8 8Kx8

ROM

32Kx8

SARAM

32 8Kx8

D Bus

C Bus

B Bus (internal only)

P Bus

E Bus

F Bus

Internal Buses

E

M

I

F

A

D


T TO

2Mx32100MHzSDRAM

256Kx1670ns

FLASH

External

C5510

28


External Memory Interface (EMIF)


T TO

� Supports 3 types of memory (1-async, 2-sync)

CPUData Buses

CPUProg Buses

DMAEMIF

CLKMEM (1x or 1/2x CPU clock rate)

A[21:0] (4Mbytes per CE space)

CE[3:0] (4 independent spaces)

- 8/16/32-bit- programmable timing

Async

- 32-bit- 1/2x or 1x CPU rateSBSRAM

- 32-bit- 1/2x or 1x CPU rate

SDRAM


Chip Support library

WDTIM

RTCDMA

DAT

ADC

USB

PWR

PLL

MCBSP

I2C

IRQ

GPIO

EMIF

CHIP

C55x™ DSP Modules

29


CSL Example (DMA)#include <csl.h>

#include <csl_dma.h>

DMA_Handle hDma0;

DMA_Config dmaCfg0 = { …};

void main() {

CSL_init();

hDma0 = DMA_open(DMA_CHA0, DMA_OPEN_RESET);

DMA_config(hDma0,&dmaCfg0);

DMA_start(hDma0);

while(!(DMA_FGETH(hDma0,DMACSR,FRAME));

// Process data

DMA_close(hDma0);

}

4. Open DMA Channel (returns DMA_Handle to hDma0)

5. Configure Channel (note use of hDma0)

6. Start Transfer

7. Close/Free DMA Channel

3. Initialize Library

2. Declare CSL Data Objects

1. Include Headers


Board Support Library

30


BSL Example


DSPLIB

31


DSPLIB example


IMLIB

• Compression/ Decompression

• Image Analysis

• Filtering/Format conversion

32


IMLIB example

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C55x - perso.esiee.fr