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2www.cadc.c CADEnCE C-To-SiLiCon CompiLER
C-t-Slc Cler tracks each
desg chage ad ts area/errace
act at every desg level, eablg
crehesve desg sace exlrat.
Desgers ca quckly ad easly terate
ultle, deret RTL cr-archtecture
ts t dety the tu
cr-archtecture wth the desred
area ad tg QR.
excu gg chagds wh u
other hgh-level sythess tls rce
desgers t re-sythesze the etre
desg wheever ay chage s ade.
C-t-Slc Cler creetal
sythess eables desgers t leet
chages ad egeerg chage rders
(ECos) creetally, wthut dsturbg
the rest the desg, ad avd
reeatg ther etre desg/vercatfw the whle desg.
oz sus h badsssb s dsgs
other hgh-level sythess tls
tycally aalyze ctrl lgc ad
dataath lgc searately, ad al t
rduce sucetly accurate tg
estates, rcg egeers t desg
the tw tyes lgc searately ad
tegrate the aually. C-t-Slc
Cler aalyzes ad sytheszes
bth ctrl lgc ad dataath lgctgether, ad t errs the trades
ecessary t acheve the tu area
ad errace.
maxz dsg usaby
Cvetal hgh-level sythess tls
requre leetat-secc ragas,
sythess drectves, ad extess t
be ebedded the ut surce cde,
akg t dcult t reuse r deret
leetats. The atet-edg
cstrat uctalty searat
rcess. Ths atet-edg database
techlgy allws desgers t track each
desg trasrat r the rgal
SysteC ut thrugh t RTL ad
eables creetal sythess, all wth
a sgle, tegrated evret.
itegrated wth the Ecuter dgtal
iC leetat fw, C-t-SlcCler uses ull-ctext, gate-level
tg eedback r ebedded lgc
sythess t radly acheve the desred
results. Ebedded lgc sythess als
esures that the geerated RTL wll
sythesze exactly as redcted.
C-t-Slc Cler s the rst hgh-level
sythess techlgy t delver ur crtcal
caabltes e ackage:
Embedded logic synthesis (ELS)
eables arallel tzat
ctrl ad dataath lgc, delvergbetter-tha-average hua qualty
results (QR)
Behavior-structure-timing (BST)
database eables true creetal
sythess ad uch aster desg
ad vercat turarud te
Constraint-functionality separation
(CFS) eables reuse acrss ultle
alcats ad rcess techlges
Auto-generated fast hardware
models (FHMs) accelerate vercatad eable hardware/stware
c-develet
Hardware archtects ad RTL desgers
ca use these caabltes t:
Dv rtl as ad whsgfcay ss
Cvetal hgh-level sythess tls
lack autated dwstrea eedback,
resultg ultle, te-csug
aual terats that lt exlrat.
techlgy C-t-Slc Cler strctly
searates the uctal descrt r
desg cstrats. Searate sythess
drectve les gude C-t-Slc Cler
tward deret leetats,
esurg that the rgal uct
del reas glde.
p as, ab vfca
The atet-edg FHm geerat
techlgy C-t-Slc Cler
creates cycle-accurate FHms, uctally
equvalet t the RTL that sulate
the icsve sulat evret
8090% as ast as the rgal uted
ut del. These FHms eable aster
vercat ad earler hardware-stware
c-desg.
BeneitS Enablescontrolanddatapath
cr-archtecture exlrat t
detere tu desg trades
Providesearlierfeedbackon
leetat easblty, area,
ad errace
Createsbetter-than-manualqualityRTL
r ew desgs wth uch less ert
PerformsfastECOswithoutfull
re-sythess ad re-vercat
Easilyretargetsdesignsfor
deret alcats ad
auacturg rcesses
Acceleratesdesignclosurewithfar
ewer terats
Enablesfastersimulation
ad vercat
Allowsengineerstodevelopsoftware
earler wth FHm vrtual rttye
7/27/2019 Cadence C2Silicon Ds (1)
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2008 Cadc Dsg Syss, ic. A ghs svd. Cadc, ecu, icsv, Suclk, ad Vg
a gsd adaks ad h Cadcg s a adak Cadc Dsg Syss, ic. oSCi ad SysC a
gsd adaks h o SysC iav h U.S. ad hcus ad s usd wh ss. A hs a s h
scv hds.
20552 06/08 mK/lD/CS/pD
a,
ea us a
[email protected]
vs
www.cadence.com
eAtUreS
AcceptsawiderangeofC/C++/
SysteC cdg styles ad cstructs,
cludg telates, classes,
user-deed tyes, ad certa
tyes ters
Automaticallygeneratessynthesizable
iEEE-1364 Verlg ad sythess
scrts r Ecuter RTL Cler
glbal sythess
AutomaticallygeneratesI/O
cycle-accurate sulat dels,
asserts, ad scrts r sulat
BSTdatabasetracksalldata
trasrats r SysteC surce
les all the way t lgc sythess,
eablg aalyss ad ag RTL
data back t lgc SysteC surce cde
CFSmaintainsindependencebetween
uctalty ad desg cstrats
Incrementalsynthesisenablesmore
desg exlrat ad aster ECo
turarud te
ELSenablesparallelcontrol-datapath
tzat--better tha average
hua QR
Integrated,interactiveGUIprovides
clete evret r sythess,
aalyss, ad debug; ards axu
user ctrl the hgh-level sythess
rcess ad vsualzat results
AutomaticallygeneratesSystemC
wraers t eable RTL vercat
wth SysteC testbeches
Providesintegrated/testedowand
scrts r Calyt SLEC
SupportsOSCI 1.0 trasact-level
delg (TLm) cstructs
plAtorm
Linux32/64-bit
CADenCe SerViCeSAnD SUpport
Cadenceapplicationengineerscan
aswer yur techcal quests by
telehe, eal, r iteretthey
ca als rvde techcal assstace
ad cust trag
Cadencecertiedinstructorsteach
re tha 70 curses ad brg
ther real-wrld exerece t
the classr
Morethan25InternetLearning
Seres (LS) le curses allw yu
the fexblty trag at yur w
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SourceLink le custer surt
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questions24hoursaday,7days
a weekcludg the latest quarterly stware rllus, rduct
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