Cadence Integrity

7/29/2019 Cadence Integrity

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Power Integrity: Effective management of timing, power, andsignal integrity

By Pete McCrorie and Harish Kriplani

As device geometries shrink and device densities increase, it has become increasingly difficultto design chips that are robust from the perspectives of timing, power, and noise. Good powerintegrity cannot be achieved by simply modifying power routing just prior to tapeout based onsignoff analysis results. It comes as a result of paying attention to power requirementsthroughout the design flowfrom early design conception, through implementation, all the wayto signoff.

This paper explains how a comprehensive power integrity solution that is integrated with designimplementation and timing/SI analysis is necessary to avoid missed tapeout windows or failedsilicon.

Technology and Design Trends that Impact Power IntegrityPerhaps the most significant technology trend (in the sense that it drives many of the others) isthat process technologies continue to shrink for ASIC and ASSP designs. More than ever,design teams need to be more concerned with minimizing power consumption for the followingreasons:

Smaller geometries enable more functionality to be packed within same area of siliconLarger designs can be physically implemented in a single chipLeakage of the transistors continues to increase with each new technology (Figure 1)

The overall result is that power-per-mm2 continues to increase and therefore the need for power

management increases.

Figure 1: Leakage power increases with advanced technology

Given the growing concerns around managing power consumption, design teams are employingadvanced low-power design techniques to minimize power and help with the cooling issues


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associated with large designs. Advanced low-power design techniques include the use of multi-switching threshold transistors (Multi-Vt), using multiple power supply domains with multiplevoltages (MSMV), power shut-off (PSO) and dynamic voltage and frequency scaling (DVFS).Often, a combination of these techniques must be used to meet the required power targets.

Multi-Vt Transistors

One of way to manage leakage involves using transistors with different switching thresholds.Low-threshold transistors enable high performance but suffer from high leakage. On the otherhand, high-threshold transistors suffer less leakage but offer less performance. Advancedstandard cell libraries now contain cells that are optimized for power or optimized for timing.These cells enable design implementation solutions to automatically optimize timingperformance, while minimizing leakage power.

Multi-Supply, Multi-Voltage (MSMV)

The use of multiple power domains running at different voltages enables power savings, but thisalso makes the life of a design engineer more complex. By reducing the supply voltage, signalstransition over a smaller voltage, which results in reduced switching currents. Designs usingmultiple voltage domains need careful planning (a) to ensure that timing can be met at theselected supply voltages, and (b) because voltage level shifters need to interface signalscrossing from one "voltage domain" to another.

Signal integrity issues become even more complex with MSMV, because nets driven with highersupply voltages (called super-aggressors) can inject more noise into adjacent nets that aredriven by lower voltages.

Power Shut Off (PSO)

Power Shut Off describes the technique of inserting power switches between the power railsand the active logic, thereby allowing the logic to be completely powered off when not currentlyrequired. The impact of PSO on power analysis is obvious, the number of power switches needsto be optimized based on IR drop and power ramp-up time constraints.

Dynamic Voltage and Frequency Scaling (DVFS)

If all of the above weren't complicated enough, advanced design teams use a technique calledDynamic Voltage and Frequency Scaling (DVFS) to further minimize the power consumption oftheir designs. DVFS refers to dynamically changing the supply voltage based on the requiredfrequency of operation of local logic blocks. Logic that needs to run at full speed gets maximumsupply voltage, while logic that can run at reduced speed gets reduced voltages. This designtechnique is most appropriate for complex SoC designs that have multiple modes of operation.However, it dramatically increases the complexity of analysis.

Thermal Analysis

On-chip temperature control has been a known problem for some time; this mainly involvesusing special cooling techniques associated with the packagesfins, fans, liquid cooling, etc. Ingeneral, packages with higher cooling characteristics cost more, so minimizing on-chip powercan result in significant cost reductions if a cheaper package can be utilized.


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Focus around on-chip temperature variations is somewhat new, and increasing with the use ofmultiple modes of operation. Thermal variations directly impact timing and SI analysis bychanging device characteristics, thereby causing additional setup/hold time violations. On-chipthermal analysis also enables a design team to understand if high leakage components arelocated in high temperature areas; relocation of such components could result in a cooler chip

that requires less expensive packaging.

Manufacturing Effects

On top of all the complexities associated with creating the design itself, design teams must alsoaccount for the complexities associated with the manufacturing process, because smallvariations in the process can result in large variations in timing, power, and signal integrity.

Multi-mode, multi-corner (MMMC) analysis is becoming more common, where chip performanceis validated for many modes of operation at multiple process corners. As the number of cornersincreases, a statistical approach is necessary to bound the runtimes. Statistical static timinganalysis (SSTA) is already in use for advanced designs, and there is a growing focus onstatistical leakage power analysis (SLPA) to better optimize power across all process corners.

The end result is that most aspects of designing and verifying modern IC designs are becomingincreasingly challenging, while the cost of missing the schedule continue to grow. Data from theGlobal Semiconductor Association (GSA) shows that 89% of designs miss their deadlines by anaverage of 44%, and that the cost of being even three months late can equate to as much as$500M in lost profits.

Power Integrity Analysis

A comprehensive power integrity analysis solution must enable a design team to understandhow power, timing, and signal integrity interact, potentially resulting in silicon failures. Thissolution must obviously be available for pre-tapeout signoff; however, it is extremely importantthat it is also available during the complete physical design implementation flow, including:

Floorplanning

Physical Implementation

Signoff

This means that the solution must be tightly integrated into the design environment. It isimportant that the integrated power/timing/SI analysis solution provides consistent resultsthroughout the design flow, otherwise there is the potential that significant late-stage re-work willbe required to address newly uncovered problems.

During floorplanning, design teams need to determine the approach to deliver power across thedesign. The two most common approaches are to use tree routing and grid (mesh) routing forthe power rails. Power integrity analysis helps a design team understand the tradeoffsassociated with each approach (typically tree routing uses less area and is less robust withoutcareful attention, while gridded power routing costs more in area and provides a very robust


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network). At the early floorplanning stages, comprehensive design data is not typically available,so the power analysis solution must provide the best accuracy with the available data.

During physical implementation, design teams are trying to complete the placement of theblocks/cells and optimize timing. At this stage, most of the design data is available, and so amore accurate analysis can be accomplished. Because achieving timing closure is tough, a

fixed operating voltage is often assumed at this point the challenge is to create power railsthat meet these requirements.

Once a design is getting close to tapeout, comprehensive, full-chip, full-accuracy analysis isrequired to try to catch any remaining issues that might cause silicon failure or yield issues.

There are five major requirements a power/timing/signal integrity analysis solution must support;the following section discusses these requirements in more detail.

1. Power Rail Design and OptimizationDuring the early stages of power rail design, static power integrity analysis is used to helpensure that the power network is sufficiently robust. Static analysis is used for two reasons, first

because static analysis can be used for both IR drop and power rail electromigration, andsecond because there isnt sufficient design data during floorplanning to enable dynamicanalysis.

It is during the floorplanning stage that design teams must decide on the structure of the powerrouting tree versus grid. Once the optimal structure is determined, power integrity analysis isused to ensure that the width of the routes and the number of vias are sufficient to meet IR dropand electromigration requirements.

2. De-coupling Capacitance Insertion and OptimizationAs a logic gate switches, it draws/sources transient currents of very short duration from/to thepower rails. When large a number of gates simultaneously switch, the resulting large transient

currents could lead to large dynamic IR drops through resistive power network. While non-switching logic acts as a local de-coupling capacitance, to mitigate this problem, de-couplingcapacitance cells are inserted to provide a local charge source that minimizes the local IR dropin the area by reducing the current drawn through the power rails.

The challenge for the design team is to optimize the number, location, and size of the de-coupling capacitance cells too few causes high dynamic IR drops, while too many extends thepower-up time, increases leakage current, impacts yield, and impacts die area.

Achieving optimal de-coupling capacitance utilization requires accurate dynamic analysis duringdesign implementation. It is wise to initially start with de-coupling capacitance around high-drivebuffers in clock and data networks. De-coupling capacitance can then be optimized during early

rail analysis. As more accurate power dissipation information becomes available, when blocksof logic have been created, more accurate dynamic analysis should be used to further tune theamount and location of the added de-coupling capacitors. Figure 2 illustrates a proposed de-coupling capacitance insertion and optimization flow.


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Initial De-coupling Capacitance Insertion(rules-based)

Dynamic IR Drop Analysis

IR Drop-aware Timing Analysis

De-coupling Capacitance Optimization

ECO

Figure 2: Recommended de-coupling capacitance insertion and optimization flow.

3. Power Switch Insertion and OptimizationIn many modern power-sensitive designs, to minimize power consumption it is necessary fordifferent functional blocks to be implemented in such a way that they can be completelypowered-down and isolated when not in use. Power switches are used to isolate the block fromthe power supply, as shown in figure 3.

VDD VDD

Power Switches

PowerSwitches

PowerSwitches

Block UnderPower Management

Power Switches

Figure 3: Power switches connect the block to the un-switched VDD power rail.

When the chips Power Management Unit (PMU) detects that a block is not currently needed, itinitiates a series of events to power-down the block. Before any power-down can occur,however, surrounding logic must be isolated and/or stabilized to prevent possible data


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corruption. Once the surrounding logic has been isolated and/or stabilized, the block ispowered-down by deactivating the power switches.

Once the PMU logic detects that a block is again required, it triggers another sequence ofevents that start the powering-up cycle. Powering-up a block can demand a large, dynamiccurrent, known as rush current, and design teams need to make sure that this rush current does

not create problems in the surrounding logic by causing local IR drop. Controlling the amount ofrush current is achieved by changing the number and size of the power switches and thesequential delay between them, as shown in figure 4.

Time

Rush

Current

Time

Rush

Curr

ent

Fast power-up time

Potential local IR drop

Slower power-up timeminimizes local IR drop

Figure 4: High rush current (top) versus lower rush current (bottom).

An advanced power integrity solution helps a design team determine how to optimize the powerswitches. Too many power switches can increase rush current, while too few can increase theIR drop seen by the logic. There needs to be a careful balance. The planning and optimizationof power switches should be driven by detailed IR drop analyses, where steady state analysis

shows the IR drop when the logic is operating normally, and dynamic power-up analysis showsthe impact on surrounding logic when blocks are re-activated. In practice, the number/size of thepower switches is determined by the maximum tolerable IR drop, and the sequencing delay isused to manage the rush currents.

4. Impact of IR drop on timing, including clock jitterDynamic IR drop varies from cycle-to-cycle, depending on the amount of switching activity. ThisIR drop variation in-turn causes delay variation in both clock networks and signal paths, leadingto clock jitter, increases in clock skew, and additional setup and/or hold violations.

Clock Jitter is defined as the variation in the arrival time of the clock edge as illustrated in Figure5. Clock jitter analysis identifies the difference in late and early arrival times of clock edges at

various register clock pins. The late pathsare calculated based on high-activity or max IR dropresults, while early pathsare calculated based on low-activity or min IR drop results.


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Figure 5: Clock Jitter due to IR drop-induced delay variation.

Clock Skew analysis identifies the difference in arrival times of the launch and capture registersas illustrated in Figure 6. Clock Skew analysis uses high activity IR drop for late path delaycalculation and low activity IR drop for early path delay calculation.

Figure 6: Clock Skew due to IR drop-induced delay variation.

In addition to IR drop induced clock skew, IR drop on the gates within the signal paths causesdelay variation for the signals, which in turn causes additional setup and hold time violations.Hopefully, it is now clear why it is increasingly important that IR drop-aware static timinganalysis be performed, to account for the impact of IR drop on clock jitter, clock skew, and setupand hold times.


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5. Impact of IR drop on Signal integritySignal integrity issues are caused when a switching net (aggressor) injects noise onto anadjacent net (victim). Signal integrity analysis determines whether the injected noise will bepropagated into a downstream latch/flip-flop and captured as an incorrect logic state. IR dropcan decrease the drive strength of a victim net, making it even more prone to signal integrityissues. Because of this, it is important to take into account IR drop during signal integrity

analysis.

SummaryDesign teams are increasingly facing parallel challenges of minimizing power while at thesame time continuing to close timing and avoid signal integrity issues under complexconditions. While timing closure remains the number number-one issue that challenges mostdesign teams, power management has rapidly ascended to become the number number-twoconcern.

Physics dictates that power, timing and signal integrity are all inter-related, and that independentanalysis of each of these components will not catch all of the potential issues. The conclusion isthat effective management of timing, power, and signal integrity requires an integrated analysissolution within the design environment, enabling analysis from early floorplanning to pre-tapeoutsignoff.

Pete McCrorie is currently focused on product marketing for power rail analysis and mixedsignal implementation at Cadence. Before joining Cadence, McCrorie was managing allextraction and analysis products at Simplex. McCrorie has his Masters degree in Physics withElectronics from Liverpool University, UK.

Harish Kriplani is currently an R&D Group Director at Cadence, where he is responsible forarchitecting and managing solutions for power/power grid analysis and design. Kriplani received

his BTech from IIT Kanpur and PhD from University of Illinois at Urbana-Champaign and holds 5US patents.

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