NMI FPGA Network Meeting

Jan 21, 2015

Cadence SystemC Design and Verification

2 © 2015 Cadence Design Systems, Inc..

• Raising Abstraction Improves Design & Verification – Optimizes Power, Area and Timing for Front End & Back End Tools

– Moves Verification and Debug up to where it is more efficient

– Greatly Improves Design Reuse/Retargeting

• HLS is Proven on Wide Variety of Cutting-Edge Designs – Hand-RTL Quality for: Datapath, Control and Mixed Designs

– Common for designs over 30M gates and >1GHz

• HLS Provides Significant Competitive Advantages – Leading Semiconductor Companies are Changing their Design

Methodologies for Productivity and Performance

– Reduces Costs and Provides Fastest Path to Verified Silicon

The High Level Synthesis Opportunity…

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What is High Level Synthesis (HLS)

• High Abstraction SystemC describes

functionality without micro-arch or

implementation details

• This SystemC is always golden, and is the

primary functional verification target

− Less code to write/debug/maintain

• HLS is used to explore various

implementations

− Explore and trade-off area, timing, power,

pipelining, clocks, tech nodes, etc.

• Outputs functionally equivalent RTL (or

gates) plus simulation models/wrappers

− Fits into existing flows

Scripts, Wrappers

RTL

High-Level Constraints SystemC

TLM

Cadence HLS

RTL Compiler Or

FPGA synthesis

“Performance”

Tech Lib

What How

“Area/Power”

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Cadence HLS targeting FPGA

• Integrated with Xilinx/Altera logic

synthesis tools (since 2008)

− Supports all end devices

− Provides accurate timing/area

estimates

• Flexible scheduling to meet QoR

needs

• Utilization vs max clock speed

• Supports DSP48 blocks

• Outputs standard RTL to be

synthesized by Quartus/Vivado

FPGA synthesis

C-to-Silicon Compiler

API to Altera/Xilinx logic synth

SystemC

Design

constraints

RTL

XST/POF

Area/Timing

Estimates

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• Untimed SystemC is more abstract than RTL

This eliminates:

– Breaking down logic into clock cycles

– Manual creation of the FSM

– Explicit memory management

– Explicit register management

– And more….

• HLS automates all low-level RTL

requirements

How does HLS improve productivity

Architecture

Functionality

Constraints

User

Manages

FSM encoding

Schedule of operations

Sharing components

Clock gating

Pipeline balance Consistent RTL style

HLS

Automatically

Manages

Timing

Area reduction "We don't want our engineers writing Verilog, we want them inventing concepts and transferring them into silicon and software using automated processes.”

Yoshihito Kondo – GM, Sony Corporation in EDA Graffiti, July 2009

6 © 2015 Cadence Design Systems, Inc..

Parallel Design and Verification

SystemC model stays golden – HLS ensures its always in sync with RTL

Parallel design and verification yields large productivity improvement!

With HLS verification can

start at the same time as

the design

With RTL flows, the

verification cannot start

until the design is ready,

many months after the

start of the project

SystemC design

RTL design

RTL coding

RTL verification

SystemC verification

time to completion

time to completion

productivity

improvement

time

RTL verification

RTL

flow

HLS

flow

*

* = time of first test vectors running

*

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• Algorithm may be the same, but the implementation has different needs

– Interface specification and verification

– Data organization, flow, and storage

• Software models do not have enough information for aggressive HW

– Software can assume infinite storage with equal (fast) access time, but Hardware must

trade off storage size vs. access time

• SystemC required if QoR and predictable RTL closure is important

– Similar RTL-style block partitioning, but leverages higher abstraction

High-level synthesis is not same as software...

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SystemC enables System Design

ANSI C provides syntax for Computation

− Functions and arithmetic expressions

− Verify the math fast with no timing

− Great for pure algorithms

C++ adds Object-Orientation

− Classes, objects, and templates

− Great for managing complexity

SystemC adds System-Level constructs

− Structure: hierarchy, modules and ports

− Concurrency: processes

− Communication protocols: transaction-level queues, signals, events and waits

− Precision: fixed-point & bit accurate data types

− Great for hardware design and verification

SystemC

“system-level”

C++

ANSI C

“function-

level”

High Level Synthesis

9 © 2015 Cadence Design Systems, Inc..

Cadence synthesizable SystemC IP Pre-verified building blocks accelerate design and verification

Memory IP Generator

CellMath Floating-Point IP

Interface IP Generator

Category Available IP Blocks

Data types

Fixed point

Complex

Floating point

Building blocks

Computational math

FIFOs

Line buffers

CDCs

Memories

Generic

communication

Point-to-point channels

with put()/get() APIs

Configurable

bus interfaces

Simple bus

AXI3

AXI4-Lite, AXI4

Custom interfaces Can be created by users

Design services available

10 © 2015 Cadence Design Systems, Inc..

IMG Accelerator

Error Diffusion

High-level verification With SystemC Verify algorithms, interfaces, synchronization

AXI 4

AXI Slave Interface

Decoder and Registers

32-bit pix-24 pix-3 32-bit

Line Buffer

24-bit pixels

5x5

Line Buffer

24-bit pixels

2x2

Configuration

Register

Synchronization

Channel

Unpack Pack Filter Zoom

C D C

Feedback RAM

Dual Port

Adapter

IP Blocks Design Blocks

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DSP IP

Graphics processing

Video processing

Image processing

Wireless signal processing

Security

Error correction

Automotive

Wireless infrastructure

Ethernet

Microcontroller

Memory I/F control

Printer control

Cache controller

DVD/CD Controller

High-level synthesis applications

Datapath

Control

Mixed

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Cadence High-Level Synthesis

Cadence HLS

Flow Automation & Integration

Synthesizable Behavioral Models

Control Datapath IP

Optimized RTL

Power Performance Area

SystemC IDE

Directives

Technology Library

Interface IP Generator

Memory IP Generator Floating Point IP

Results Visualization

Combined strengths of Cynthesizer and CtoS

Worlds most proven HLS technology

Cadence HLS

RTL Compiler

Inside

13 © 2015 Cadence Design Systems, Inc..

20% better quality of results

(mW

) Summary: Why use high-level synthesis?

SystemC RTL in 10 days

vs. manual RTL in 3 months

I/F controller IP Motion-detection IP

FPGA retargeting in

1-2 days vs. 2-3 weeks (manual)

10x+ productivity increase

5x-10x faster, better verification

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Systems, Inc. All others are the property of their respective holders.