Calibrating Achievable Design - vlsicad.ucsd.eduvlsicad.ucsd.edu/GSRC/SLIDES/sanjose_2002.pdf · The MARCO/DARPA Gigascale Silicon Research Center for Design & Test Executive Review

The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test

Executive ReviewSan Jose, September 19th, 2002

Page 1

DUSD(Labs)

Calibrating Achievable DesignCalibrating Achievable Design

Andrew B. KahngAndrew B. KahngGSRC Executive ReviewGSRC Executive Review

9/19/029/19/02

Theme Members: Wayne Dai, Theme Members: Wayne Dai, TsuTsu--JaeJae King, King, WojciechWojciechMalyMaly, Igor Markov, Herman , Igor Markov, Herman SchmitSchmit, Dennis Sylvester, Dennis Sylvester

OutlineOutline

The Problem: Design The Problem: Design TechnologyTechnology ProductivityProductivity

The Value Proposition: Focus x TTM x QOR x Impact x …The Value Proposition: Focus x TTM x QOR x Impact x …

Specific Projects: Accomplishments and PlansSpecific Projects: Accomplishments and Plans

Collaboration and RoadmapCollaboration and Roadmap



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Problem: Design Problem: Design TechnologyTechnology Productivity GapProductivity GapITRSITRS--2001: “Cost of design is the greatest threat to the 2001: “Cost of design is the greatest threat to the semiconductor roadmap”semiconductor roadmap”

interoperability, design quality and cost metrics, design procesinteroperability, design quality and cost metrics, design process optimizations optimization

Design Productivity Gap = Design Design Productivity Gap = Design TechnologyTechnology Productivity GapProductivity Gap

This Theme: improve Design Technology Productivity by providingThis Theme: improve Design Technology Productivity by providingopen, shared infrastructures that change how we open, shared infrastructures that change how we specifyspecify, , developdevelop, , and and measuremeasure andand improveimprove Design TechnologyDesign Technology

Address both design complexity Address both design complexity and design technology complexityand design technology complexity

Synergy: {Correct R&D focus} x {Faster TTM} x {Validated QOR imSynergy: {Correct R&D focus} x {Faster TTM} x {Validated QOR improvement}provement}

Living Roadmap: Living Roadmap: Shared Shared ““red bricksred bricks”” to optimize SEMI R&D investmentto optimize SEMI R&D investment

New cultures: openNew cultures: open--source publication, CADsource publication, CAD--IP reuse, METRICS benchmarkingIP reuse, METRICS benchmarking

Calibrating Achievable Design (C.A.D.) ThemeCalibrating Achievable Design (C.A.D.) ThemeGTX / Living Roadmap: Where to Focus?GTX / Living Roadmap: Where to Focus?

What is the benefit of lowWhat is the benefit of low--k?k?Achievable global signaling quality?Achievable global signaling quality?Optimal memory integration and architecture?Optimal memory integration and architecture?http://http://vlsicad.ucsd.eduvlsicad.ucsd.edu/GTX/GTX

CADCAD--IP Reuse: Faster and Better R&DIP Reuse: Faster and Better R&DIndustryIndustry--compatible, opencompatible, open--source, backsource, back--end flowsend flowshttp://vlsicad.eecs.umich.edu/BKhttp://vlsicad.eecs.umich.edu/BKRemote execution “Remote execution “autogradingautograding” infrastructure” infrastructure(VLSI design education, common data model, …)(VLSI design education, common data model, …)

METRICS: Measure & ImproveMETRICS: Measure & ImproveDesign metrics, design project metricsDesign metrics, design project metricsClock speed, frontClock speed, front--end acceptance, tool noise, end acceptance, tool noise, ……Deployed in industryDeployed in industryhttp://http://vlsicad.ucsd.eduvlsicad.ucsd.edu/METRICS/METRICS



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The Value PropositionThe Value PropositionNot Business As UsualNot Business As Usual

Design (Technology) Productivity Gap is Design (Technology) Productivity Gap is thethe critical challengecritical challenge

Launch FRCLaunch FRC--scale initiatives that impact entire community, industryscale initiatives that impact entire community, industryCulture changes: publication standards and evaluation methodoloCulture changes: publication standards and evaluation methodologies, gies, creation of reusable CADcreation of reusable CAD--IP, openIP, open--source, selfsource, self--consistent consistent roadmappingroadmapping, … , … Living Roadmap and proactive involvement within ITRS community: Living Roadmap and proactive involvement within ITRS community: ORTCsORTCs, , System Drivers, analyses of “shared red bricks”, …System Drivers, analyses of “shared red bricks”, …Bookshelf: 30 slots, 100+ entries, 1000’s of downloads, clear iBookshelf: 30 slots, 100+ entries, 1000’s of downloads, clear impact across mpact across academic literature (DAC, ICCAD, ISPD, IWLS, …), in industry (Caacademic literature (DAC, ICCAD, ISPD, IWLS, …), in industry (Capo source is po source is free and open; actively used at > 10 companies)free and open; actively used at > 10 companies)METRICS: integrated into commercial METRICS: integrated into commercial iCadenceiCadence platform, used at TI, 20+ platform, used at TI, 20+ attendees at DACattendees at DAC--2002 BOF meeting2002 BOF meeting

Next: Education, CostNext: Education, Cost--Driven Design, …Driven Design, …

Specific Projects (1)Specific Projects (1)

GSRC Technology Extrapolation (GTX)

“Living Roadmap”



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Progress in Technology ExtrapolationProgress in Technology Extrapolation““Living ITRS”Living ITRS”

ITRSITRS--2001 (December 2001): consistency of power, die size, density, 2001 (December 2001): consistency of power, die size, density, performance parameters, spanning PIDS, A&P, Test, Design, performance parameters, spanning PIDS, A&P, Test, Design, ORTCsORTCsGTX distribution on SEMATECH website (linked to ITRSGTX distribution on SEMATECH website (linked to ITRS--2001)2001)Integrated with other models (SUSPENS, BACPAC, …)Integrated with other models (SUSPENS, BACPAC, …)Mantra: “Shared Red Bricks” (synergy among SEMI R&D programs)Mantra: “Shared Red Bricks” (synergy among SEMI R&D programs)

New understanding of key axes in achievable design envelopeNew understanding of key axes in achievable design envelopeCostCost--driven integration and packaging (UCSC)driven integration and packaging (UCSC)Interconnect (Michigan, UCB, UCSD, UCSC)Interconnect (Michigan, UCB, UCSD, UCSC)Variability (Michigan, UCSD)Variability (Michigan, UCSD)Power (via PED Theme, UCB, Michigan)Power (via PED Theme, UCB, Michigan)

CostCost--Driven Integration and Packaging (UCSC)Driven Integration and Packaging (UCSC)

AreaArea--IO advantagesIO advantagesPreserves onPreserves on--chip electrical environment in chip electrical environment in the SIP contextthe SIP contextMinimizes size of ESD protection device for Minimizes size of ESD protection device for intraintra--package package IO’sIO’sImproved signal integrity due to power and Improved signal integrity due to power and ground pad structureground pad structure

TestbedTestbed: Single: Single--Package ComputerPackage ComputerIntegrated CPU, North Bridge, graphics chip, Integrated CPU, North Bridge, graphics chip, DDR SDRAMDDR SDRAMBalance: core logic, memory access speedsBalance: core logic, memory access speedsOther issues: rerouting Other issues: rerouting wirelengthwirelength, IO , IO performance, thermal performance, performance, thermal performance, costcost, …, …

Conventional IO

Area-IO

Logic&Buffer

PAD

PAD

ESDProtection

Circuit

Logic&Buffer



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ChipChip--LaminateLaminate--Chip Memory Integration Chip Memory Integration Attractive CLC electrical characteristicsAttractive CLC electrical characteristics

Maximum offMaximum off--chip delay << IO buffer delay (3.5ns)chip delay << IO buffer delay (3.5ns)Signal round trip time < rise time (500ps)Signal round trip time < rise time (500ps)InterInter--chip skew < board skew (500ps)chip skew < board skew (500ps)No terminating resistors requiredNo terminating resistors requiredSmaller IO buffer size and minimized ESD protectionSmaller IO buffer size and minimized ESD protection

LaminateLogic

Area-IO DRAM

Decoupling C

Chip-Laminate-Chip (CLC) architecture

Source: SyChip Inc.

BGA ball

( 3.34M Tr., 570 Area-IO )6.80 mm

3.85

mm

∆∆ Achievable envelope = ?Achievable envelope = ?RoutabilityRoutability of IO redistribution?of IO redistribution?Optimal powerOptimal power--ground structure on ground structure on laminate?laminate?Optimal clock structure on laminate?Optimal clock structure on laminate?Model of junction temperature in SIP?Model of junction temperature in SIP?Cost?Cost?

Design calibrationDesign calibrationConfigurable AreaConfigurable Area--IO SRAMIO SRAM

MultiMulti--GHz OnGHz On--Chip Interconnects (UCB)Chip Interconnects (UCB)LoopLoop--based model for fullybased model for fully--shielded global clock structure*shielded global clock structure*

Highly efficient extraction of loop RLC valuesHighly efficient extraction of loop RLC valuesModels verified with fullModels verified with full--wave simulation and measurement data wave simulation and measurement data Available in GTXAvailable in GTX

ClosedClosed--form interconnect performance model**form interconnect performance model**Driver delay and rise timeDriver delay and rise timeInterconnect delay, rise time and overshootInterconnect delay, rise time and overshootAvailable in GTXAvailable in GTX

Design Optimization***Design Optimization***Design guidelines for best interconnect structure for optimal deDesign guidelines for best interconnect structure for optimal delay and power lay and power

UCB, 2002

* Xuejue Huang, Phillip Restle, Thomas Bucelot, Yu Cao, and Tsu-Jae King, "Loop-based Interconnect Modeling and Optimization Approach for Multi-GHz Clock Network Design", Custom Integrated Circuits Conference (CICC), pp. 19-22, 2002

** Xuejue Huang, Yu Cao, Dennis Sylvester, Tsu-Jae King, and Chenming Hu, "Analytical Performance Models for RLC Interconnects and Application to Clock Optimization", to be presented at International ASIC-SoC conference, September 2002, Rochester, USA.

*** submitted to JSSC



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Active Shields (Michigan)Active Shields (Michigan)

Repeater, shielding paradigms Repeater, shielding paradigms entrenched in highentrenched in high--perfperf flowflow

Seek complementary “dropSeek complementary “drop--in” in” techniques that improve delay, slope, techniques that improve delay, slope, power, noise immunitypower, noise immunity

ActivelyActively useuse shields to minimize shields to minimize capacitance or inductancecapacitance or inductance

Switch shields to improve signal Switch shields to improve signal propagation and/or noise immunitypropagation and/or noise immunityFor RC lines, switch shields in phase For RC lines, switch shields in phase with signal net to reduce effective with signal net to reduce effective coupling cap, delaycoupling cap, delayFor inductive lines, switch shields in For inductive lines, switch shields in opposite phase with signal net to opposite phase with signal net to produce better return path, reduce produce better return path, reduce loop inductanceloop inductance

in out

CL

Passive Shielding

in out

CL

Active Shielding for RC Wires

inout

CL

Active Shielding for Inductive Wires

in

RC RC Wire ResultsWire Results

0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

0.75

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

Dela

y / S

lope

(nor

mal

ized

to fa

t wire

)

Wire Thickness (t) (µm)

Delay (Active shields) Delay (Passive shields) Fat wire (Delay and slope) Slope (Active shields) Slope (Passive shields)

Active shields resulted in reduced transition times (~25% reduction over fat wire) and reduced delays

Active shields result in increased power compared to passive shields

Noise immunity degraded slightly with active shields due to driver resistance

Optimal delay/slope vs. wire thickness for copper wire of length 7.5mm



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Interconnect Architecture Metrics, Optimization (UCSD)Interconnect Architecture Metrics, Optimization (UCSD)Example motivation: “Is low k worth it?”Example motivation: “Is low k worth it?”

New New interconnect architecture metricinterconnect architecture metric allows quantified comparison of allows quantified comparison of design, process, and materials technology improvementsdesign, process, and materials technology improvements

Sensitive to entire interconnect stack, repeater area budget, deSensitive to entire interconnect stack, repeater area budget, design sign wirelengthwirelengthdistribution, clock frequency, perdistribution, clock frequency, per--connection delay targets, …connection delay targets, …

0.096

0.101

0.106

0.111

0.116

0.121

0.126

0.131

0.136

0.141

1 1.5 2 2.5 3 3.5 4 4.5

Value of k / Miller coupling factor

Nor

mal

ized

rank

TSMC 90nm node:Improving Miller coupling factor by 38% (better design, shielding) equivalent to 40% improvement in k


CAD-IP Reuse via The GSRC Bookshelf

Pervasive Automation via bookshelf.exe



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Previous Mindset: CADPrevious Mindset: CAD--IP ReuseIP Reuse

CADCAD--IP Reuse: One of three original initiatives in CAD ThemeIP Reuse: One of three original initiatives in CAD Theme““Trivial ideaTrivial idea”” GSRC BookshelfGSRC Bookshelf

Reuse helps, but is not a panaceaReuse helps, but is not a panaceaConsider: Moore’s Law + Design Productivity Crisis Consider: Moore’s Law + Design Productivity Crisis required required aasymptoticssymptotics of computational and design effortof computational and design effort

NearNear--linear memory: design hierarchy, coarse viewslinear memory: design hierarchy, coarse viewsNearNear--linear runtime: fast global optimization heuristicslinear runtime: fast global optimization heuristicsNearNear--linear design effortlinear design effort: auto: auto--installation, allinstallation, all--pairs benchmarking, pairs benchmarking, design flow health monitoringdesign flow health monitoringNearNear--linear learning curvelinear learning curve: “: “autogradersautograders”, open”, open--sourcesource

CADCAD--IP Reuse is one asymptotic requirementIP Reuse is one asymptotic requirement

The VLSI CAD BookshelfThe VLSI CAD BookshelfGSRCGSRC--provided service that supports nearprovided service that supports near--linear scaling of complexity in linear scaling of complexity in EDA (= a repository)EDA (= a repository)Growing popularity is seen from downloads and contributionsGrowing popularity is seen from downloads and contributions

Algorithm descriptions and analyses; openAlgorithm descriptions and analyses; open--source CAD toolssource CAD toolsOpen design benchmarks and algorithm comparisonsOpen design benchmarks and algorithm comparisonsCurrently 30 slots, 100+ entries: Currently 30 slots, 100+ entries: Verilog ToolsVerilog Tools through through Clock Skew SchedulingClock Skew Scheduling

Described in IEEE Design and TestDescribed in IEEE Design and Test, May/June 2002, May/June 2002Growing adoption within academic literature, review processGrowing adoption within academic literature, review process

ISPD 2002 papers from UCLA, UCSD, Michigan ISPD 2002 papers from UCLA, UCSD, Michigan DAC 2002 papers from Michigan and UICDAC 2002 papers from Michigan and UICICCAD 2002 papers from IBM, UCSB and MichiganICCAD 2002 papers from IBM, UCSB and MichiganOngoing work at CMU, UCSD, Minnesota, etc.Ongoing work at CMU, UCSD, Minnesota, etc.

Many fresh Ph.D.s in CAD are now familiar with the BookshelfMany fresh Ph.D.s in CAD are now familiar with the Bookshelf



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Industry Usage of the GSRC BookshelfIndustry Usage of the GSRC BookshelfCommon denominator in discussions with academiaCommon denominator in discussions with academiaIntelIntel (Santa Clara) and (Santa Clara) and IBMIBM (Austin and T.J. Watson)(Austin and T.J. Watson)

Downloaded and compiled several tools from the BookshelfDownloaded and compiled several tools from the BookshelfWrote parsers/converters (~2 weeks of time), distributed internaWrote parsers/converters (~2 weeks of time), distributed internallyllyCompared to internal tools on internal benchmarks Compared to internal tools on internal benchmarks ⇒⇒ ““results on par or better”results on par or better”Tools in use for comparisons and algorithm design experimentsTools in use for comparisons and algorithm design experiments

Cadence Design SystemsCadence Design Systems (San Jose and NJ)(San Jose and NJ)Downloaded and compiled several tools from the Bookshelf Downloaded and compiled several tools from the Bookshelf In some cases (where LEF/DEF was not available) wrote convertersIn some cases (where LEF/DEF was not available) wrote convertersUsed for prototyping and evaluation of new commercial toolsUsed for prototyping and evaluation of new commercial tools

Other companiesOther companiesPrototyping design flows before fullPrototyping design flows before full--blown tools are readyblown tools are ready

Many repeated downloads, but little technical feedbackMany repeated downloads, but little technical feedback (no feedback or (no feedback or fee required by our license)fee required by our license)

Academic Usage of the GSRC BookshelfAcademic Usage of the GSRC Bookshelf

New New floorplanningfloorplanning methodology for pipelined array designs methodology for pipelined array designs developed at developed at CMUCMU, based on “wire path length” metric, based on “wire path length” metricBookshelf usageBookshelf usage

“Classic” = Bookshelf Block “Classic” = Bookshelf Block FloorplannerFloorplanner“Classic+LSP” and “New” methods built on same Bookshelf code“Classic+LSP” and “New” methods built on same Bookshelf code

Discovery: new Discovery: new floorplanningfloorplanning methodology yields faster and methodology yields faster and smaller pipelined designssmaller pipelined designs

Less area wasted on hold time fixing than in Less area wasted on hold time fixing than in unfloorplannedunfloorplanned designsdesignsMany substantial contributions back into the BookshelfMany substantial contributions back into the Bookshelf

Software: New modifications to existing Bookshelf componentSoftware: New modifications to existing Bookshelf componentApplications (LEF/DEF): 1Applications (LEF/DEF): 1--D DCT, 2D DCT, 2--D DCT, 1D DCT, 1--Round IDEA encryptionRound IDEA encryptionLikely future additions: AES, FFT, LowLikely future additions: AES, FFT, Low--Density Parity Check, …Density Parity Check, …



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OneOne--Round IDEA Encryption BenchmarkRound IDEA Encryption Benchmark

Floorplan

Dead Space

WPL Speed Initial P&R Util.

Final P&R Util.

No Floor X X 2.02 82.3% 98.1%

Classic 3.34% 7.82 2.13 61.8% 68.7%

Classic + LSP 4.00% 7.51 2.08 65.4% 72.9%

New 2.56% 4.27 2.02 89.4% 97.8%

Hold area used to fix holdHold area used to fix hold--time violations: 9.5% (No Floor) vs. 1.8% (New)time violations: 9.5% (No Floor) vs. 1.8% (New)

New Mindset: OnNew Mindset: On--Demand, Pervasive AutomationDemand, Pervasive Automation

Another “trivial” idea: Automate Another “trivial” idea: Automate allall design activities design activities that cost time/$$$that cost time/$$$

BottomBottom--up: “intelligent” solversup: “intelligent” solversTopTop--down: goaldown: goal--driven, platformdriven, platform--based methodologiesbased methodologiesSideways: “intelligent” VLSI design environmentSideways: “intelligent” VLSI design environment

“We automate what you do” (if we can understand it “We automate what you do” (if we can understand it ☺☺))Fundamental techniques for automation (e.g., OOFundamental techniques for automation (e.g., OO--based design based design patterns for EDA)patterns for EDA)Generic, reusable, highGeneric, reusable, high--performance SW and HW components performance SW and HW components (e.g., Capo, (e.g., Capo, PipeRenchPipeRench))Common practices and methodologies for automationCommon practices and methodologies for automation



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““We Automate What You Do”We Automate What You Do”

Goal: Reconfigurable and robust Goal: Reconfigurable and robust design flows design flows modular implementation platformsmodular implementation platformslanguage support for rapid flow prototypinglanguage support for rapid flow prototypingWebWeb--based script composers for design flowsbased script composers for design flowsfilefile--system support for distributed flowssystem support for distributed flowsdesign flow health monitoringdesign flow health monitoringautomatic extraction of statistically significant resultsautomatic extraction of statistically significant results

Additional motivationsAdditional motivationsRelated research: Related research: PUNCHPUNCH from Purdue, from Purdue, SatExSatEx from CNRS/U. Parisfrom CNRS/U. Paris--SudSud (France), (France), NEOSNEOS from Argonne National Lab, from Argonne National Lab, PBSPBS from NASA, from NASA, OmniFlowOmniFlow from NCSU/CBLfrom NCSU/CBLBenchmarking and regression testingBenchmarking and regression testingExperience in education: Experience in education: autoauto--graders graders (large(large--scale infrastructure for evaluation)scale infrastructure for evaluation)Experience with infrastructure for collaborative research (basedExperience with infrastructure for collaborative research (based on the Bookshelf )on the Bookshelf )

bookshelf.exebookshelf.exeBest existing featuresBest existing features

Reporting style of Reporting style of SatExSatExVersatility of PUNCHVersatility of PUNCHScalability of NEOSScalability of NEOSControl as in Control as in OmniFlowOmniFlow

New featuresNew featuresMIMEMIME--like data typeslike data typesFlow scriptingFlow scriptingAutomatic submission of binaries and source codeAutomatic submission of binaries and source code

Scalable: distributed computation, automated maintenanceScalable: distributed computation, automated maintenance“Adapts to users”“Adapts to users”

Multiple levels of expertise, commitment Multiple levels of expertise, commitment Sharing of public data, protection of proprietary dataSharing of public data, protection of proprietary data“Screen“Screen--saver” grid computation mode, cf. SETI@Home, saver” grid computation mode, cf. SETI@Home, EntropiaEntropia, etc., etc.



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Usage and Data ModelsUsage and Data Models

Consistent data models needed for serious flows, experimental reConsistent data models needed for serious flows, experimental researchsearchE.g., integrated RTLE.g., integrated RTL--toto--layout implementation, industry interoperabilitylayout implementation, industry interoperabilityPlan to use Plan to use OpenAccessOpenAccess 2.02.0 (spec available 2Q02, source expected 1Q03)(spec available 2Q02, source expected 1Q03)Adjustments expected within Bookshelf for openAdjustments expected within Bookshelf for open--source / industry SP&R flowssource / industry SP&R flows

Infrastructure proposal (IBM/Cadence, Infrastructure proposal (IBM/Cadence, IWLS02): Study IWLS02): Study netlistnetlist changes changes for improved routing congestionfor improved routing congestion

IWLS benchmark APIIWLS benchmark APIInterface to Bookshelf formatsInterface to Bookshelf formatsLayout generation (in Bookshelf)Layout generation (in Bookshelf)Placement (several in Bookshelf)Placement (several in Bookshelf)Congestion maps (in Bookshelf)Congestion maps (in Bookshelf)


Design Process Optimization

METRICS



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METRICS ArchitectureMETRICS Architecture

WebServer

DataminingInterface

Servlet

SQLTables

SQL results

Tablesrequestresults

DB

Metrics Data Warehouse

DataMining

Reporting

Tables

Inter/Intra-net

JavaApplets

Flow Wrapper Transmitterwrapper

T1 Tool Tool

TransmitterAPI

XML

T2 T3

Recent ProgressRecent Progress

DACDAC--2002 Birds2002 Birds--ofof--aa--Feather MeetingFeather Meeting20 attendees (18 from industry, including HP, IBM, Intel, Motoro20 attendees (18 from industry, including HP, IBM, Intel, Motorola)la)

Industry adoption:Industry adoption:Cadence Design SystemsCadence Design Systems

METRICS integrated into BlockMETRICS integrated into Block--Based Design Methodology for FrontBased Design Methodology for Front--End End Acceptance, Clock Planning and flow quality tracking Acceptance, Clock Planning and flow quality tracking Used within Used within iCadenceiCadence (web(web--based design flow)based design flow)

Texas InstrumentsTexas InstrumentsMETRICS used for flow/design quality trackingMETRICS used for flow/design quality tracking



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Front End AcceptanceFront End Acceptance

Chip AssemblyChip Assembly

Block DesignBlock Design

Chip Design Planning

Verif

icat

ion

Customer Data ValidationCustomer Data Validation

Design Feasibility AssessmentDesign Feasibility Assessment

Project Planning and Design BudgetingProject Planning and Design Budgeting

Floor plan & Estimation

Bus TimingTest AMS PowerClock

Design Input

Block Design

Block-Based Design is a patented technology by Cadence Design Systems, Inc.

BlockBlock--Based Design (BBD) MethodologyBased Design (BBD) Methodology

1. Create IP clock reference library– store historical information on previous IP

2. Define basic clock speed– find master clock frequency that satisfies

constraints for all blocks3. Generate clock budgets

– determine target gate count and target freq.to drive synthesis:

– define insertion delays and skews from DB4. Determine clock structures, variants

– balanced buffered, grid, unbuffered H5. Verify clock structures

– timing correctness– adjust clock frequency,

padding, PLL taps, …

Buffered Tree

Grid

H-tree

LoadingDel

ay

Clock Planning MethodologyClock Planning Methodology

Ref: K. Venkatramani, S. Mantik and R. Adhikary, “A Predictive and Analytical Clock Planning Methodology for Hierarchical Block Based Design”, DATE-2002

14001400550.970.979.69.62432436633

200200330.120.121.21.227273322

3030220.030.030.30.3991.51.511

# Regs# Regs# Pipeline # Pipeline StagesStages

Skew Skew (ns)(ns)

Delay Delay (ns)(ns)

Clock Clock LoadsLoads

Size Size (mm)(mm)

Block Block No.No.

140%140%20020066143143200200606066

129%129%133.3133.344103103150150606055

157%157%133.3133.3448585140140202044

171%171%13313366.6766.6722787839396868101033

155%155%13313366.6766.67228686434375755522

117%117%13313366.6766.672211411457571001005511

Master Master MarginMargin

New New AuxAux

New New MasterMaster

nnAux Aux HzHz

Ideal Ideal HzHz

Max Max HzHz

Min Min HzHz

Blk Blk NoNo

( ) ( )freqfreq

freqfreqgatecntgatecntgatecntgatecnt

minmaxmintarget minmax

mintarget

−−×−

+=

Early TapEarly Tap0.0770.07711N/AN/AN/AN/AHardHard66

PadPad--0.170.170.750.75N/AN/AN/AN/AHardHard55

Early TapEarly Tap0.2770.2771.21.2N/AN/AN/AN/AHardHard44

FasterFaster0.5030.5031.4251.4254.34.3243243SoftSoft33

GoodGood--0.010.010.910.913.33.39797SoftSoft22

PadPad--0.670.670.2510.2511.31.32222SoftSoft11

DecisionDecisionDiffDiffDelay Delay (ns)(ns)

Size Size (mm)(mm)

Clock Clock LoadsLoads

TypeTypeBlk Blk No.No.



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Front End Acceptance (FEA) FlowFront End Acceptance (FEA) Flow• FEA preparation

– data gathering, classification and certification

• Customer data validation– project checklist (docs, specs,

testbenches, models, etc.)– data completeness (readability,

execution readiness, etc.)– simulations (block interconnect, chip-

level functional model)– primary block selection– project directory structure

• Design feasibility assessment– analysis of proposed design to

determine acceptance risks– assess key project parameters (cost,

area, performance, power)• Project planning and design budgeting

– Project schedule, human/machine resources, cost/expense, etc.

Customer Data & Specifications

Customer Data Validation

Design Feasibility Assessment

MeetRequirements?

Renegotiate Specification or

Terminate Project

Project Planning and Design Budgeting

Design and Project Data

To Chip Planning and Block Design

No

Yes

FEA Preparation

Ref: K. Venkatramani and S. Mantik, “Managing Risk in Block Based Designs: A Front End Acceptance Methodology”, EDP-2002

METRICS Impact at CadenceMETRICS Impact at Cadence

Clock Planning and FrontClock Planning and Front--End AcceptanceEnd AcceptanceMETRICS used as design data (IP) repositoryMETRICS used as design data (IP) repositoryClock planning applied to a wireless modem design consisting Clock planning applied to a wireless modem design consisting of 8 main IP blocks (total of 1M cells) achieves 54MHz speed on of 8 main IP blocks (total of 1M cells) achieves 54MHz speed on ARM architectureARM architectureFEA achieves more accurate coarseFEA achieves more accurate coarse--grain assessment, reducing grain assessment, reducing design risk without sacrificing design timedesign risk without sacrificing design time

Flow quality trackingFlow quality trackingMETRICS keeps track of design quality and timing in a webMETRICS keeps track of design quality and timing in a web--based SP&R flow for timing convergencebased SP&R flow for timing convergence



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C.A.D. Theme DeliverablesC.A.D. Theme Deliverables

Most C.A.D. Theme research is available as Most C.A.D. Theme research is available as open sourceopen sourceIntegrated as GTX modelsIntegrated as GTX models

Research at UCSC, UCB, CMU, Michigan all captured and interoperaResearch at UCSC, UCB, CMU, Michigan all captured and interoperablebleGTX is also available with the ITRSGTX is also available with the ITRS--2001 release (SEMATECH website)2001 release (SEMATECH website)

Released in the GSRC BookshelfReleased in the GSRC BookshelfMany point optimization codes; CMU libraries and reference desigMany point optimization codes; CMU libraries and reference designsns

Released in the METRICS systemReleased in the METRICS system

Our open source is Our open source is really openreally open source source MIT license; MIT license; can be used for ANY purpose (many positive can be used for ANY purpose (many positive comments from major companies such as Intel, IBM)comments from major companies such as Intel, IBM)

60+ publications also posted on GSRC website60+ publications also posted on GSRC website

Roadmap and CollaborationRoadmap and Collaboration

Identified challenges

and issues inUDSM design

Exploredpotential

methodologysolutions

DevelopedConcept ofPlatform-

Based Design(PBD)

Select Design Drivers:•Ambient intelligence

•In-home networks•Radar-on-a-chip

Formulatedvalidation

problem forPBD

Developed andpublished

taxonomy for PBD

Explored and developedunderlying tools and

methodologies

Develop and integrateassociated tools and

methodologies (capture,synthesis, optimization,

verification, test)

Develop prototypeplatforms (architecture,

implementation) thatmeet design driver

needs

Identify missingcomponents /

emerging challenges(mixed signal,

reliability)

Refine and transfermethodology

Joint project betweenthemes to develop

prototypeimplementation

Develop solutionsfor emerging

problems

Jan 1999 Today Jan 2003 Jan 2004 Jan 2005

TransferTo

Sponsors

Collaborate with C2S2 FCRP

Exploration

GTX + Living ITRS: What is the design problem?

GTX + Living ITRS: What is the design problem?

Bookshelf, METRICS and bookshelf.exe (design process opt)

Bookshelf, METRICS and bookshelf.exe

Bookshelf, METRICS

bookshelf.exe (auto-flow opt)

Interfaces to other FRCs: GTX + Living ITRS, Cost modeling Other interfaces to SRC and Sponsors:

Education, Living ITRS “Shared Red Bricks”

Documents

Calibrating Achievable Design - vlsicad.ucsd.eduvlsicad.ucsd.edu/GSRC/SLIDES/sanjose_2002.pdf · The MARCO/DARPA Gigascale Silicon Research Center for Design & Test Executive Review