Call for Proposals - Huawei

HIRP OPEN 2016 Storage Technology

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Call for Proposals

Storage Technology

HIRP OPEN 2016


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Copyright © Huawei Technologies Co., Ltd. 2015-2016. All rights reserved.

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Application Deadline: 09:00 A.M., 18th July, 2016 (Beijing Standard Time, GMT+8).

If you have any questions or suggestions about HIRP OPEN 2016, please send Email

([email protected]). We will reply as soon as possible.

mailto:[email protected]).


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Catalog

HIRPO20160401: Windows SMB Client Behavior Analysis ...................................................... 4

HIRPO20160403: Low Latency and Distributed Network Communication Component

Research based on RoCE ......................................................................................................... 8

HIRPO20160404: Double the Energy Density of the Lithium Ion Battery ............................... 12

HIRPO20160405: Unify Interface Reduced ECC Scheme for Hybrid Memory ....................... 14

HIRPO20160406: Cross Layer Co-design for Flash Memory based Storage Systems .......... 17

HIRPO20160407: Design of an Error Aware Framework for Flash Memory based Storage

Systems ................................................................................................................................... 20


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HIRPO20160401: Windows SMB Client Behavior

Analysis

1 Theme: Storage Technology

2 Subject: storage protocol

3 Background

SMB NAS storage is essential and very widely used protocol, developed

rapidly in recent years; the latest version has been developed to 3.02. In

addition, Windows Azure public cloud also vigorously promotes the SMB

protocol, within a few years, SMB is still in the stage of constant evolution and

optimization.

SMB protocol itself has related specifications, but this specification is not very

transparent, a lot of compatibility issues occur because we do not know the

windows client behavior. Currently more than 60 SMB compatibility issues

were found at our product, In addition to contrast the rival company and

consult Microsoft, there is no effective way to resolve the compatibility issues,

and Microsoft Consulting cycle is very long, at least a month, and Microsoft

response effect is not ideal, problem-solving rate is less than 10%.

Through this cooperation project, we can quickly learn the client knowledge

and improve the analysis efficiency of compatibility issues, it is very import to

the developing and developed products.

In addition, through this cooperation project, we plan to achieve the following

objectives:

Processing time of compatibility issues reduce 30%-50%, compatibility issues

reduce 10%-20%;


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Increasing the technical reserves of client knowledge, providing technical

assistance to the development of new features;

4 Scope

In this paper, the Windows client API interface is the windows file system API,

for the common mainstream applications (vdbench, office software, etc.) used.

The Windows client in this paper includes Windows XP, Windows Server 2003,

Windows Server2008 R2, Windows 7, Windows Server 2012, Windows Server

2012 R2.

In this paper, the testing tool development language is preferred C/C++.

1) Windows client API compatibility testing tools, including：

Support graphical interface;

Support API interface concurrent operation, maximum 10000, 1 by

default;

Support API interface and flexible configuration parameters;

Support API interface call cycle;

Support API interface number set;

Support running at Windows XP, windows Server 2003, Windows

Server 2008 R2, Windows 7, windows server 2012, windows server

2012 R2;

2) Windows client API compatibility reports, including:

Detailed description and difference analysis of all API interface and

parameter at mainstream windows client(Windows XP and windows

Server2003, Windows Server 2008 R2, Windows 7, windows

server2012, windows server 2012 R2, the same bellow);


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All API call trace analysis form filesystem layer to SMB protocol layer

at mainstream windows client;

SMB package analysis triggered by All API at mainstream windows

client;

Behavior analysis when receiving different error code at mainstream

windows client;

Office software (office2003, office2007, Office2010) API call trace

analysis form filesystem layer to SMB protocol layer;

3) Windows client cache analysis report, including：

The principle of windows client cache and the relationship with SMB

oplock/lease;

Cache size, failure time and cache configuration analysis at

mainstream Windows client;

Difference analysis of mainstream windows client behavior when open

or close client cache;

4) Windows client performance testing tools, including:

Support basic performance statistics to all Windows client API,

statistical values including the maximum delay, minimum delay,

average delay , number of errors, request number for each API;

Support API interface concurrency with maximum 10000, default value

is 1;

5) Windows client performance test report, including:

The mainstream windows client API performance test value in the

same set of SMB server, test scenarios is 2 windows client with 2000

concurrent API;


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Difference analysis of API performance of different clients.

5 Expected Outcome and Deliverables

Technical reports of energy efficiency model and analysis for Massive MIMO;

The Windows client API compatibility test tool;

The Windows client API compatibility report;

The Windows client cache Analysis report;

The Windows client performance testing tools;

The Windows client performance test report.

6 Phased Project Plan

Phase1 (~3 months): deliver Windows client cache Analysis Report

Phase2 (~4 months): deliver Windows client API compatibility testing tools and

windows client performance testing tools

Phase3 (~4 months): deliver Windows client API compatibility report and

windows client performance test report

Click here to back to the Top Page


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HIRPO20160403: Low Latency and Distributed

Network Communication Component Research based

on RoCE


2 Subject: non volatile memory

3 Background

In recent years, non-volatile memory (such as RRAM, PCM, MRAM,

STTRAM,etc) technologies have made great progress, their high persistence,

high performance, low latency, high density and low power consumption bring

us more hope for enhancing the storage system capabilities.

The commercial progress of NVM is much faster, some product will be

released in 2018, the persistent capability of NVM is much better than DRAM,

the performance and latency of NVM is much better than Flash(1000x better),

NVM is very strong in performance, persistent and capacity, NVM will be

widely used in future distributed system.

In future distributed system, we will face some great challenges in using NVM

features sufficiently:

1). NVM’s write/read latency is decreasing ceaselessly, lower than 1

microsecond, the existing network communication technology latency is higher,

that will impact NVM capability in distributed system, so we need more

high-speed network communication technology to support using NVM in

distributed system.


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2). NVM can guarantee data persistent, different with DRAM, but there are

great challenges to guarantee data safe and reliable in each node NVM during

data transmission (when transport data through network, the data may reside

in CPU L2,L3 Cache, data doesn’t arrive NVM immediately, when nodes break

down, the data may lose),we need to guarantee data safe and reliable when

written to NVM through network and keep data consistency when host node

breaks down.

4 Scope

Build network communication component for NVM based on RoCE, supply

control and data plane API, guarantee low latency, high performance, high

scalability and high data reliability.

1. Provide APIs for application(such as distributed cache)

Provide connection management API(such as create connection, cancel

connection, etc.), when connection errors, that can be solved normally without

impacting application;

Provide register API for NVM address space, when connection errors,

ensure there is no influence for application to use these NVM address;

Provide write/read API base on RDMA，these APIs can transport data

among NVMs in each node directly, and guarantee data arrives NVM safely

and reliably(support single IO data consistency and multi IOs data

consistency);

Provide Send/Receive msg API based on RDMA, so the network

communication component will be with ability to send and receive messages;

2. Support high scalability, low latency, high performance and

guarantee data high reliability, when system break down, guarantee data


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transported through network communication component consistency

Support high scalability(1K nodes, through test and theoretical derivation

to verify it);

In 4KB IO scenario, single concurrent IO latency <= 4us; 32 concurrent

80W IOPS 99% IO latency < 40us, use 4 CPU cores, total consumption lower

40%;

guarantee data arrives NVM safely and reliably and guarantee data

transported through network communication component consistency, when

system break down;

The green area is the scope of this study, Network transport level provides

interface for application (distributed cache). In order to guarantee performance

and reliability, you can modify the driver and hardware to form a combination of

software and hardware solutions.


1) Design document and Prototype code


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Provide a design document to describe detail design and describe

how and why this design can solve above issues;

Provide Prototype code with clear instructions, prototype code can

work smoothly;

2) Test and analysis Report

Test Code with clear instructions;

Technical report to prove the result;

3) Patents idea

At least 2 patents.

6 Acceptance Criteria& Method

All deliverables must be reviewed by Huawei and presented to Huawei directly;

Service Deliverables will be document deliverables (e.g. word, Excel,

PowerPoint, etc.);

Guidance documents and report must be detailed enough and can guide

Huawei engineers verifying on soft platform;

The performance of New NVM Programming Model should meet the

requirements.


Phase1 (~3 months): Provide a design document to describe detail design and

describe how and why this design can solve above issues;

Phase2 (~4 months): Provide Prototype code with clear instructions, prototype

code can work smoothly;

Phase3 (~5 months): Test Code with clear instructions; Technical report to

prove the result.



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HIRPO20160404: Double the Energy Density of the

Lithium Ion Battery


2 Subject: battery energy storage technology

3 Background

Lithium ion batteries are widely used as power sources and energy storage

devices in our daily life. Despite the great success of lithium ion batteries up to

now, higher demand has been raised with the emergence of new-generation

electronic products, such as ultrathin and ultra-light devices. Innovation in

battery technology is thus highly desired to fulfill the ever increasing demand of

higher power/energy density, better rate capability.

4 Scope

High energy density batteries are urgently needed for the consumer electronic

applications. The value of energy density of commercial lithium ion batteries

with 650Wh/L can’t meet the customer’s expectation. The traditional electrode

material and design nearly reach its theory limitation. High capacity

cathode/anode electrode materials and battery system need be investigated.


Prototype batteries with energy density of 1300Wh/L (with 200cycles) are

provided.


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6 Acceptance Criteria

Energy density of 1300Wh/L (with 200cycles) is achieved.


Expected project Duration (year): 2 years;

Phase1 (~12 months): Energy density 1000Wh/L with 200cycles;

Phase2 (~12 months): Energy density 1300Wh/L with 200cycles



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HIRPO20160405: Unify Interface Reduced ECC

Scheme for Hybrid Memory


2 Subject: reliability-error detecting and correcting

3 Background

Tradition CPU side memory Controller read and write DRAM media in directly,

because DRAM media bit error rate is high, so the reliability requirement is

high.

NVM access difference: Module is responsible for the NVM storage and

transmission error, the MC just need to detect DDR bus error, thus Reduced

ECC requirements are put forward.

Figure1 the difference ECC requirement between DRAM and NVM

DRAMChip

DDR BUSTransmit

error only

NVM dataStorage

error

ECCFor Both

Bus&Storage

MC

X3DModule

Controller

NVM BUSTransmit

error

DDR BUSTransmit

error only

ECCFor

right

ECCFor DDR

BUS Trans

MC

NVM dataStorage

error

ReducedECC


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4 Scope

Main application scenarios: Hybrid channel in NVDIMM and standard DRAM

DIMM, NVM some information needs to occupy the original ECC transmission,

such as DRAM as a Cache for NVDIMM, the Cache Tag is in DRAM ECC

space. the traditional 64 byte of DATA provided by the additional 8 bytes of

DATA at the SEC/DED (single bit error correction, double bit) ability of ECC

into 68 byte DATA (64 byte DATA + 4 byte TAG) provided by ECC 4 bytes of

additional DATA protection, and must at least do the at least do the detection

error function and retransmission the data.

Commercial value: benefit NVDIMM and standard DRAM DIMM mixed

interpolation, DRAM as a Cache for NVDIMM scenario for system

performance.

5 Main challenges:

1). The proportion of the ECC data protection turn <64 bytes: 8 bytes> into a

<68 bytes: 4 bytes>, or <64 bytes: 4 Byte> at least, and must at least do the

detection function and retransmission the data;

2). The ECC algorithm can't too slow, shall meet the DDR4 requirement in

nanosecond level;

3). Little expenses of hardware implementation as far as possible.


1). The reduced ECC scheme design report which include: coding and

decoding scheme, error-detecting capacity Evaluation, Error detection circuit

design;


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2). Reduced ECC：The reduced ECC experiment and simulation report,

simulate the improvement degree RBER circuit delay.


Phase1 (~2 months): The reduced ECC scheme design report which include:

coding and decoding scheme, error-detecting capacity Evaluation;

Phase2 (~4 months): Error detection circuit design;

Phase3 (~6 months): The reduced ECC experiment and simulation report,

simulate the improvement degree RBER circuit delay.



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HIRPO20160406: Cross Layer Co-design for Flash

Memory based Storage Systems


2 Subject: flash memory

List of Abbreviations

eMMC: Embedded Multi Media Card

UFS: Universal Flash Storage

PCIe: Peripheral Component Interconnect Express

3 Background

Flash memory has been developed for several decades. In order to provide

unified storage interface to applications, flash memory also use the block

interface. In this case, flash memory acts like a block device. This scheme has

boost the fast deployment of flash memory in the early days. For example,

most of the flash device interfaces, such as eMMC, UFS and PCIe, embedded

controllers to manage the flash storage. However, due to complex

characteristics of flash memory, its controller design becomes complicated.

For example, several modules need to be implemented in controller, including

address mapping, garbage collection, wear leveling, error correction, bad

block management, buffer management, parallelism exploration and so on.

The complicated design of flash controller introduces several issues, including

high controller design cost, un-matching design between flash storage and

host systems, which still remain challenging for further deployment of flash

memory especially coming to the advanced flash memory with limited


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performance and lifetime. What’s worse, several designs at the host even may

conflict with the designs in the flash controller, because flash controller always

acts like a block box to host designers. Clearly, simply providing the block

interface to host system is not the best way for designing flash storage

systems.

One good chance for flash memory based storage systems is to do cross layer

co-design to match the requirements between host systems and flash

controllers, and release burden on the controller design. With this in mind, the

cost on the controller design can be reduced and the host system can well

match with the storage system design. For this purpose, the cross layer

co-design should be able to reduce cost and simplify controller design, besides

achieving good performance. However, how to identify the un-matching of host

systems and flash controller and how to design for matching is still not clear.

What’s more, how to release the burden of the flash controller design is also

unclear. The objective of this proposal is to identify the mismatch between

flash controllers and host system design for flash memory, determine what

kind of functions should be crossly co-designed, and then provide an efficient

flash controller design.

4 Scope

The scope of this project includes but not limited to:

Understanding the mismatch in the design of flash memory controller and

host system;

Co-design framework of flash memory controller and host systems;

Optimization on flash memory controller.


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One paper and one patent;

A report describing the detailed design and implementation of the

proposed method.


Pass:

1 paper is accepted at the top international conference in related area

such as FAST, DAC, DATE, ISCA, and HPCA;

1 patent passes Huawei’s review;

Fail: Cannot deliver a patent or a paper;

Excellent:

One or more patents are delivered, AND

One or more paper is accepted.


Phase 1 (~6 months): Deliver a patent;

Phase 2 (~6 months): Deliver a paper.



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HIRPO20160407: Design of an Error Aware Framework

for Flash Memory based Storage Systems


2 Subject: flash memory

List of Abbreviations

NAND: Negative-AND

3D: Three Dimension

3 Background

NAND flash memory has been widely used in smartphone, embedded systems,

personal computer, and data centers. During the last decades, the

development of flash memory relies on two approaches: technology scaling

and bit density improvement, which may be no longer applicable now. Instead,

recent 3D-based technology extends the development of flash. However, even

though 3D NAND flash memory is able to relax the reliability issue, its

performance and lifetime are still pending to be improved. Considering

reliability, performance, and lifetime, all these issues are related to errors in

flash memory. In order to solve them, traditional schemes use strong error

correcting mechanisms, such as BCH, LDPC and so on. However, these

schemes are not only costly, but also induce bad performance. For example,

high error correcting capability of BCH requires a large code word and longer

decoding latency. LDPC decoding latency is also bad at the high error rates.

Therefore, optimizing error correction mechanism for 3D NAND flash memory

is necessary.


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One good chance for the state-of-the-art flash memory such as 3D NAND flash

to handle errors is to design error-aware mechanisms, which minimize these

errors based on the their characteristics. The main challenge is to understand

the specific characteristics of error sources of flash memory, and then design

solutions for each type of errors. Hence, the objective of this proposal is to

understand the error characteristics of flash memory, and to provide a set of

approaches to avoid the errors or boost the performance and lifetime of 3D

NAND flash.

4 Scope

The scope of this project includes but not limited to:

Understanding the error characteristics of 3D NAND flash memory;

Error correction framework for 3D NAND flash memory;

Error reduction mechanism for 3D NAND flash memory;

Optimizations on improving the performance, lifetime and reliability of 3D

NAND flash memory.


One paper and one patent;

A report describing the detailed design and implementation of the

proposed method.


Pass:

1 paper is accepted at the top international conference in related area

such as FAST, DAC, DATE, ISCA, and HPCA;


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1 patent passes Huawei’s review;

Fail: Cannot deliver a patent or a paper;

Excellent:

One or more patents are delivered, AND

One or more paper is accepted.


Phase 1 (~6 months): Deliver a patent;

Phase 2 (~6 months): Deliver a paper.


Documents

Call for Proposals - Huawei