CAN-PCIH Hardware Manual - Janz Tec...CAN-PCIH (Hardware Manual) • Installation 2 - 7 2 Installation When opening the shipping package of the CAN-PCIH you should immediately check

PROPRIETARY NOTICE All rights reserved by Janz Automationssysteme AG. No parts of this technical manual may be modified, copied or reproduced in any form or by any means for commercial use without the prior written permission of Janz Automationssysteme, Germany. All instructions, information and specifications contained in this manual are for reference only and remain subject to change without announcement.

CAN-PCIH

PCI CANbus Controller

(Hardware Manual)

Version 1.0

refers to product revision no. V 1.0

Title: CAN-PCIH Hardware Manual File: j:\as\entwicklung\projekte\hw\pc\can-pcih\doc\manual\canpcih.doc Pattern: \\ntserv1\novelln\daten\entwicklung (ew)\formblätter\entwicklung (ew)\f_manual.dot Created: be, 01.03.2004 Last Update: as, 12.08.2005

© Janz Automationssysteme AG 2005 Im Dörener Feld 8 PO Box 1906 D-33 049 Paderborn, Germany Tel.: +49-5251-1550-0 FAX: +49-5251-1550-90 email: [email protected] Internet: www.janz.com

CAN-PCIH (Hardware Manual) • Contents i

Rev. 1.0 © Janz Automationssysteme AG

Contents

1 Introduction 5 1.1.1 Hardware ........................................................................................................................5 1.1.2 Software..........................................................................................................................5 1.2 Functional Overview ............................................................................................................5

2 Installation 7 2.1 Handling Instructions ...........................................................................................................7 2.2 Components Locations ........................................................................................................8 2.3 Software Considerations......................................................................................................9

3 CPU, Memory and Device 10 3.1 Processor ...........................................................................................................................10 3.2 Main Memory .....................................................................................................................10 3.3 Bootflash memory ..............................................................................................................11 3.4 Devices at the CAN-PCIH..................................................................................................11 3.5 CAN-Controller SJA1000 ...................................................................................................12 3.5.1 CAN-Interface ...............................................................................................................13 3.6 Serial Interface...................................................................................................................13

4 Programming Information 14 4.1 PCIbus configuration space ...............................................................................................14 4.2 On-board Registers............................................................................................................15 4.2.1 Control Register ............................................................................................................15 4.2.2 Interrupt Status Register...............................................................................................16 4.2.3 Feature Register ...........................................................................................................16 4.2.4 Power-on reset Register ...............................................................................................16 4.2.5 PCI Interrupt Registers .................................................................................................17 4.2.6 Local Interrupt Registers...............................................................................................17 4.2.7 Scratchpad register.......................................................................................................18

5 Appendices 19 5.1 Technical Data ...................................................................................................................19 5.2 References.........................................................................................................................21 5.3 Pin Assingment D-Sub connector (CAN-1 and CAN-2).....................................................22 5.4 Pin Assingment Flat Cable Header (CAN-3 and CAN-4) ..................................................23 5.5 Product History...................................................................................................................24 5.6 Manual History ...................................................................................................................24

ii CAN-PCIH (Hardware Manual) • Contents

© Janz Automationssysteme AG Rev. 1.0

List of Figures figure 1:CAN-PCIH block diagram............................................................................................................6 figure 2: Mounting of CAN-PCIH/EXT on CAN-PCIH...............................................................................7 figure 3:CAN-PCIH with major components .............................................................................................8 figure 4:CAN-PCIH/EXT with major components .....................................................................................8 figure 5: Board Dimensions ....................................................................................................................20

List of Tables table 1:Local Chipselect of the CAN-PCIH.............................................................................................11 table 2: Address assignment On-board registers ...................................................................................15 table 3:Pin assignment of 9-pol DSub ....................................................................................................22 table 4:Pin assignment flat cable header ...............................................................................................23

CAN-PCIH (Hardware Manual) • Contents iii

About this Manual This is the hardware reference manual for the CAN-PCIH PCI expansion board. It gives all necessary information to users and programmers of the CAN-PCIH. We have tried to keep it compact, so there are no specialized sections just for users or programmers, i.e. everything that can be said about the serial port is said in one place (connector layout, signal levels and programming hints). Users that are not programmers might therefore only read the first sections (Introduction and Installation), and come back to the detailed sections when they need specialized information. This manual assumes that the users, especially programmers, have knowledge and experience of programming. Where not specific to the CAN-PCIH, we do not give basic information about programming, computer hardware or describe operations of bus-systems. Should you wish to do low-level programming of the CAN-PCIH then you will need to refer to secondary detailed documents that describe the PPC405 PowerPC and the other components that are used on the CAN-PCIH. You will find pointers to these documents in section 5.2. The manual starts off with an Introduction to the CAN-PCIH. This describes the features and architecture of the CAN-PCIH. It then explains some topics about Installation of the product. The rest of the manual will then cover technical details about the CAN-PCIH.

Conventions If numbers are specified in this manual, they will be either decimal or hexadecimal. We use C-notation to identify hexadecimal numbers (the 0x prefix). If we refer to low active signal names, they will suffixed by a “#” character. Some parts of the text are really important. These are visually marked with the following signs:

Indicates information that, when not fully understood or followed, might cause permanent damage to the system. You should not start using the product before you have read this information.

Indicates information that we think you should have read to save your time by avoiding problems. Important suggestions that should be followed will also be marked with this sign.

Acronyms and Abbreviations CAN Controller Area Network. CPLD Complex Programmable Logic Device. EEPROM Electrically erasable PROM. Capable of individuall in-circuit re-programming of each

cell (in contrast to FLASH) EMC Electromagnetic capability. ESD Electrostatic discharge. FLASH Electrically erasable PROM. Capable of in-circuit re-programming with the capability of

erasing considerably large blocks (in contrast to EEPROM). FPC Flat Printed Circuit PCI Peripheral Component Interconnect.


CAN-PCIH (Hardware Manual) • Introduction 1 - 5


1 Introduction

The CAN-PCIH is a PCI compatible intelligent CAN field bus controller card. It can be plugged into PCI slots of all kind of computer systems.

1.1.1 Hardware • Intelligent PCI CAN fieldbus controller • Local IBM PowerPC405GPR processor with 266 MHz • 1Mbyte Flash EPROM, 16 bit organized • 64Mbyte SDRAM, 32bit organized • 2 x SJA1000 CAN controllers on base board, 2 additional SJA100 CAN controllers on the CAN-

PCIH/EXT expansion board. • 1Mbit high speed transfer rates • ISO/DIS 11898 interface • Compatible to CAN Spec. 2.0B • 2 x 9pin DSUB connectors at front bezel • CAN interface optionally isolated • CANbus termination software switchable • Optional RS232 serial interface • PCI specification version 2.2 compliant, for 5V and 3,3V signal environment • Short form factor PCI add in-card • Dimensions 95mm x 130mm

1.1.2 Software • Supported by drivers for various operating systems (Windows, VxWorks, Linux and others) Contact Janz Automationssysteme for more information about the available software packages.

1.2 Functional Overview The CAN-PCIH offers a powerful scalable CAN connection for host systems with PCI sockets. The CAN-PCIH supplies 2 CAN connections which are controlled by the on board IBM PowerPC405GP processor. It can be expanded by an expansion module with 2 additional CAN interfaces. The block diagram of the CAN-PCIH is shown in figure 1. It shows the heart of the module with the PowerPC405GPR processor, the Bootflash and with the SDRAM. A PCI-BUS interface integrated in the PPC405GPR allows the user to access the SDRAM and the Bootflash from the PCI-BUS as well as from the local processor. The address window accessible from the PCI-BUS is programmable. The two CAN interfaces are equipped with the SJA1000 basic CAN controllers. Both CAN busses are connectable via 9pin D-Sub connectors at the front bezel. Optionally the CAN busses on the CAN-PCIH can be isolated. In this case the CAN interfaces are supplied with galvanic isolated on-board DC/DC-converters, so that they are isolated from logic potential and isolated of each other. Additionally two user programmable general purpose LED´s are available on the front panel. Furthermore a optional RS232 serial interface can be used for debugging purposes. With the PPC405GP, 1MByte Flash and with 64MByte SDRAM, the module is able to manage large-scale applications. The employment of the Flash EPROM allows the user to download his own firmware through the PCI bus.

1 - 6 CAN-PCIH (Hardware Manual) • Introduction

The CAN-PCIH comes default with the ICANOS firmware. ICANOS manages all base functions for a CAN network, such as the management of the timers and the CAN interfaces. All interrupt handling for a real-time clock and the CAN controller is also carried out by ICANOS. ICANOS multiplexes time-out indications, receives CAN messages and bus events and transmits confirmations to it’s user. Software filtering of received CAN messages may be requested. It is possible to request that single identifiers or ranges of identifiers be accepted or not. The CAN-PCIH offers enough power to run on-board CAL (CAN Application Layer) and CANopen (Communication Profile). The interfacing is done by e.g. CAL/CANopen service request/indications and by a DPM hosted real-time-data process image. The services can be used in a very convenient way by an OS independent library, so that migration between different operating systems can be done easily.

BootFLASH

16bit wide1MByte

32bit wide64MByte

SDRAM

PPC405GPRProzessor

(266MHz)

CPLD

SJA1000µ-CouplerCANTransceiver

(optional)

CAN-2

SJA1000CANTransceiver

(optional)

CAN-1

Front Panel

statusLEDs


(optional)


(optional)

CAN-4

CAN-3

ExpansionConnector

Flat CableHeader

IO Header

seriellesEEPROM

1Kbit

RS232

(optional)

CAN-PCIH

CAN-PCIH/EXT(optional)

Local Bus

PCI Bus33MHz32Bit

3.3/5V

µ-Coupler

µ-Coupler

µ-Coupler

figure 1:CAN-PCIH block diagram


CAN-PCIH (Hardware Manual) • Installation 2 - 7

2 Installation

When opening the shipping package of the CAN-PCIH you should immediately check the contents of the package. In the package you will find information about the scope of delivery, as this depends on the options that you have ordered.

2.1 Handling Instructions

When installing the CAN-PCIH onto a mezzanine carrier board you need to obey some handling precautions to avoid damaging your card with an electrostatic discharge.

When taking the card from the anti-static bag, in which it is delivered, you should wear a grounded anti-static wrist strap. The strap should also be connected to your working environment. It is recommended to first touch the card at the front panel, as this has a defined resistive path of about 1MΩ to the sensitive card electronics, thereby a controlled discharge will take place. Before placing the card onto your mezzanine carrier board, you should check that the power supply has enough strength to provide the extra load for the CAN-PCIH. You should also check whether the supplied voltage levels are appropriate. See section 5.1 for the specification. Before inserting the CAN-PCIH into a PCI slot, you must turn the power off. When mounting the CAN-PCIH/EXT, please note that you must lock the extension board with the three screws that are delivered with the extension board.

1 1

2 2

figure 2: Mounting of CAN-PCIH/EXT on CAN-PCIH


2 - 8 CAN-PCIH (Hardware Manual) • Installation

2.2 Components Locations

0S1

CAN-OSC

CAN-Transceiver

CAN-Transceiver

DC/DCConverter

DC/DCConverter

PLDFPGA

IO header

CAN-

1CA

N-2

CPU

-OSC

SDR

AM

SDR

AM

SJA1

000

FLAS

H

SJA1

000

PPC405GPR

JTAG

Conn

ector

Powe

rRe

gulat

or

Expa

nsion

Con

necto

rr

LED

figure 3:CAN-PCIH with major components

SJA1

000

SJA1

000

Expa

nsion

Con

necto

rr

DC/D

CCo

nver

ter

DC/D

CCo

nver

ter

CAN-Transceiver

CAN-Transceiver

CAN-OSC

Flat cable header

CAN-3 CAN-4

U2

U4

figure 4:CAN-PCIH/EXT with major components


CAN-PCIH (Hardware Manual) • Installation 2 - 9


2.3 Software Considerations For any information about installing drivers and other software packages related to the CAN-PCIH, refer to the documentation that comes with this software.

3 - 10 CAN-PCIH (Hardware Manual) • CPU, Memory and Device


3 CPU, Memory and Device

3.1 Processor The CAN-PCIH mezzanine module is equipped with the PowerPC405GP processor with the following properties:

• Thirty-two, 32bit general purpose register • Code compatible with PowerPC User Instruction Set Architecture and Development Tools • Separate 16KB Instruction cache and 16KB write-back or write-through Data cache • Hardware multiply and divide • On-Chip clock generator and power management 266MHz CPU core • Four timers (64bit time base, programmable interval timer, fixed interval timer and watchdog

timer) • Memory Management Unit provides translation of logical address space into physical

addresses • Integrated PCI V2.2 Compliant 32-Bit 33MHz Controller • Four DMA channels with scatter/gather support. • PCI-Host, Target, and Initiator Capability • Programmable Interrupt Controller

The PPC405GPR includes a distributed processing architecture, a high speed PCI system bus, a high performance processor, efficient memory management, flexible I/O device interface, high performance burst mode data transfers and efficient I/O transaction management. Most of the features of the PPC405GPR processor core are compatible with the PowerPC Virtual Environment and Operating Environment Architectures, as implemented in PowerPC processors such as the 6xx/7xx family. The PPC405GPR processor core also provides a number of optimizations and extensions to these layers of the PowerPC Architecture. The full archutecture of the PPC405GPR is defined by the PowerPC Embedded Environment and the PowerPC User Instuction Set Architecure. The primary extensions of the PowerPC Architecture defined in Embedded Environment are:

• A simplified memory management mechanism with enhancements for embedded applications • An enhanced, dual level interrupt structure • An architected DCR address space for integrated peripheral control • The addition of several instructions to support these modified and extended resources

Finally, some of the specific implementation features of the PPC405GP are beyond the scope of the PowerPC Architecture. These features are included to enhance performance, integrate functionality, and reduce system complexity in embedded control applications.

3.2 Main Memory The CAN-PCIH is equipped with 64Mbyte SDRAM. This memory is 32bit wide organized and is accessible from the local PPC405GPR Processor or from the PCI-Bus. It is organized in one Bank. The SDRAM controller of the PPC405GP provides a 32bit interface to SDRAM memory with optionaI Error Checking and Correction (ECC). The controller supports page mode operation and maintains up to four open pages. To improve performance, the controller features separate 32-byte read and 128-byte write buffers.

CAN-PCIH (Hardware Manual) • CPU, Memory and Device 3 - 11


3.3 Bootflash memory The CAN-PCIH is supplied in the default configuration with 1MByte Bootflash. From this, various Software can be loaded into the main memory. The Bootflash is 16Bit organized. Maximum 4Mbyte FlashEPROM can be supported by the CAN-PCIH.

3.4 Devices at the CAN-PCIH On the CAN-PCIH various devices are connected to the local bus of the PPC405 processor. The following table shows the devices corresponding to the used PPC405 chip-select signals.

Device LCSx Access width

Bootflash LCS0 16bit CAN-controller1 LCS3 8bit CAN-controller2 LCS3 8bit CAN-controller3 LCS3 8bit CAN-controller4 LCS3 8bit

On-board-registers LCS2 32bit

table 1:Local Chipselect of the CAN-PCIH

3 - 12 CAN-PCIH (Hardware Manual) • CPU, Memory and Device


3.5 CAN-Controller SJA1000 The CAN-PCIH2 is equipped with four Stand-alone CAN-controller SJA1000 from Phillips Semiconductors for connection to the CAN-fieldbus. It provides:

• Bus access priority (determined by the messages identifier) • Guaranteed latency for high priority messages • Data length form 0 to 8 bytes • Multicast and Broadcast message facility • Non destructive bit-wise arbitration • NRZ coding/decoding with bitstuffing • Programmable transfer rate (up to 1Mbite/s) • CAN 2.0B protocol compatibility • Supports 11bit identifier as well as 29 bit identifier • Extended receive buffer (64-byte FIFO) • Single/dual acceptance filter with mask and code register for standard and extended frame • Powerful error handling capability • Arbitration lost interrupt with detailed bit position • Single-shot transmission (no re-transmission on error or arbitration lost) • Listen only mode (no acknowledge, no active error flags) • Hot plugging support (software driven bit rate detection)

To allow fast access to the SJA1000 with it’s multiplexed address/databus, an external multiplexer is implemented in the CPLD. This allows the PPC405GP processor to read or write data registers in one bus-cycle. Thereby, no interrupt locking is necessary when accessing the CANbus controllers. When the LCS3# is low, the CPLD generates the chip select signals for the CAN controllers and the PPC405 can access one of the SJA1000.

CAN-PCIH (Hardware Manual) • CPU, Memory and Device 3 - 13


3.5.1 CAN-Interface The SJA1000 CAN-controllers are connected by two wire bus lines via the CAN transceivers (82C251). These are connected directly to the 9pin D-Sub connectors on the front panel. The CAN interfaces conforms with ISO/DIS 11898 and with CiA/DS102-1. Optionally on the CAN-PCIH the CAN-busses can be opto-isolated from the CAN-controllers. In this case DC/DC converters are used to supply the interface logic with 5V and the two wire busses between SJA1000 and the CAN-transceivers are opto-isolated. If the CAN-PCIH is an end node on the CAN bus, then the CANbus needs to be terminated at this node. A 120Ohm resistor can be activated at each CAN interface by software for this purpose. Refer to section 5.3 for the connector pin assignment. Refer to section 5.4 for the connector pin assignment on the CAN-PCIH/EXT for CAN-3 and CAN-4.

3.6 Serial Interface Optional to the CAN-interface the modul can be equipped with a serial RS232 interface which can be used for debugging purposes. For this the UART0 of the PPC405 is used. Then the TxD and RxD signals of UART0 are conducted via a RS232 transceiver to the 25pol. D-Sub connector.

4 - 14 CAN-PCIH (Hardware Manual) • Programming Information


4 Programming Information

This and the following chapters details the methods needed for working with the CAN-PCIH.

4.1 PCIbus configuration space The board (the interface chip) is identified by a set of IDs in PCI configuration space as listed below:

Purpose Value Found in Vendor ID 0x1014 CFG space register 0 Device ID 0x0156 CFG space register 0 Subsystem Vendor ID 0x13C3 CFG space register 0x2c Subsystem ID 0x12?? CFG space register 0x2c

The LSB of the Subsystem ID codes the hardware revision of the CAN-PCIH module. Currently the following version coding is used:

LSB of Subsystem ID

CAN-PCIH revision

0x00 V1.0

The PPC405GP provides address spaces to access the local configuration registers (in both I/O and memory range). These registers are used to configure the PPC405 behaviour. Additionally two address spaces are configured through which the local memory space and some board-registers can be accessed.

PCI base address register

Description

Size

0 unused 1 Dual port memory address space 512Kbyte 2 On-board registers 64kbyte

The actual addresses for these memory spaces are configured by the PCI-BIOS of your system every time the computer is booted. If you wish to access one of these spaces, then you need to read the actual addresses from the PCI configuration space!

CAN-PCIH (Hardware Manual) • Programming Information 4 - 15


4.2 On-board Registers This address space provides some local on-board-registers that are outside of the scope of the PPC405GPR local configuration registers and the CAN-controller registers. The On-board registers are as follows:

Address Offset Device Access

0x00 Control-register read/write 0x04 Interrupt-status-register read 0x08 Feature-register read 0x0c Power-on-reset-register read/write 0x10 PCI-interrupt-set-register read/write 0x14 PCI-interrupt-clear-register read/write 0x18 Flag-set-register write 0x1c Flag-clear-register write 0x20 Local-L-interrupt-set-register read/write 0x24 Local-L-interrupt-clear-register read/write 0x28 Local-T-interrupt-set-register read/write 0x2c Local-T-interrupt-clear-register read/write 0x30 Scratchpad-register read/write

table 2: Address assignment On-board registers

The on-board registers can be accessed by the PPC405GPR processor and by the host. The host can access these registers relative to PCI-BAR2. The PPC405GPR can access these registers relative to local chip select 2.

4.2.1 Control Register On the front bezel of the CAN-PCIH are located two user programmable LED´s. These LED´s can be switched by bit D24 and D25 of the control-register. Furthermore the CAN-termination can be switched on/off by the bits D26 and D27. The control register should normally not be used by the host, as the LEDs and the CAN-termination are controlled by the firmware of the CAN-PCIH.

CTR_REG 0x00 (lword, r/w) 31 30 29 28 27 26 25 24 23 – 0 Reserved T3 T2 T1 T0 LED1 LED0 not used

LED[1..0] Theses bits controls the LED´s on the front bezel of the CAN-PMC.

LED0 = 1 LED0 (green) is on. LED0 = 0 LED0 (green) is off. LED1 = 1 LED1 (orange) is on. LED1 = 0 LED1 (orange) is off.

T[3..0] Theses bits controls the CAN-termination of the four CAN interfaces. T0 = 1 CAN-termination CAN_1 is on. T0 = 0 CAN-termination CAN_1 is off. T1 = 1 CAN-termination CAN_2 is on. T1 = 0 CAN-termination CAN_2 is off. T2 = 1 CAN-termination CAN_3 is on. T2 = 0 CAN-termination CAN_3 is off. T3 = 1 CAN-termination CAN_4 is on.



T3 = 0 CAN-termination CAN_4 is off.

Reserved Reserved positions are undefined, and must not be considered. Software must mask them off.

4.2.2 Interrupt Status Register The two CAN-controllers are able to generate interrupts to the PPC405 processor. Both interrupt lines are logical ored and connected to the IRQ0 signal of the processor. For differentiation of the interrupt source a bit in the Interrupt Status Register (ISR) is activated (active low). The ISR is readable under the address 0x04. Following is shown the bit assignment of the ISR:

INT_STAT 0x04 (lword, ro) 31 30 29 28 27 26 25 24 23 – 0

Reserved I3 I2 I1 I0 not used

I[3..0] Interrupt status info. Each defined bit in this register reflects the status of the INT# pin of the corresponding CAN-Controller. A zero will be read when an interrupt is pending. I0 coresponds to CAN-controller 1; I1 coresponds to CAN-controller 2


4.2.3 Feature Register The feature register is used for identification of additional features in further versions. By reading this register it is possible to distinguish different versions or extensions. The bits D24 – D31 of the feature register are zero on the CAN-PCIH.

FTR_REG 0x08 (lword, ro) 31 30 29 28 27 26 25 24 23 – 0 F7 F6 F5 F4 F3 F2 F1 F0 not used

F[3..0] Feature info. Each bit combination defines the corresponding feature in

future designs. On the CAN-PCIH these bits are all zero. F[7..4] These bits are reserved to read on further versions the position of a hex

switch, if implemented. On the CAN-PCIH these bits are all zero.

4.2.4 Power-on reset Register The power –on reset register has the feature, that the contents are not cleared by a local reset. The implemented bit R0 is only cleared by a power-on reset.

PWOR_REG 0x0c (lword, r/w) 31 30 29 28 27 26 25 24 23 – 0

Reserved R0 not used

R0 The content of R0 is not affected by a local reset, but is only cleared by a power-on reset.

Reserved Reserved positions are undefined, and must not be considered. Software

CAN-PCIH (Hardware Manual) • Programming Information 4 - 17


must mask them off.

4.2.5 PCI Interrupt Registers On the CAN-PCIH are several registers to generate interrupts from the local PPC405 processor to the PCIbus. PCI requests can be masked off by the CPU. This is done through the Flag set/clear registers. PCI interrupts from the local CPU are disabled after RESET, and must be enabled before using.

FLAG_SET 0x18 (lword, wo) 31 30 29 28 27 26 25 24 23 – 0

Reserved P0 not used

FLAG_CLEAR 0x1c (lword, wo) 31 30 29 28 27 26 25 24 23 – 0

Reserved P0 not used

P0 Writing this bit enables/disables interrupts from the local CPU to the PCIbus. Both registers are accessed in hot-1 technique: Writing a one to P0 enables/disables further interrupts to the PCIbus, writing zero to P0 does not affect the interrupt mask status.


If the PCI Interrupt is enabled, the bits PI0 – PI3 in the PINT_SET and PINT_CLEAR Register can be used to generate interrupts to thePCIbus.

PINT_SET 0x10 (lword, r/w) 31 30 29 28 27 26 25 24 23 – 0

Reserved PI3 PI2 PI1 PI0 not used

PINT_CLEAR 0x14 (lword, r/w) 31 30 29 28 27 26 25 24 23 – 0

Reserved PI3 PI2 PI1 PI0 not used

PI[3..0] Writing one of these bits sets/resets interrupt requests from the local CPU to the PCIbus. Both registers are accessed in hot-1 technique: Writing a one to PI[3..0] sets/resets the corresponding bit in the registers.


4.2.6 Local Interrupt Registers Local Interrupts on the CAN-PCIH module can be generated from the host in two different ways. The registers LINT_SET, LINT_CLEAR and TINT_SET, TINT_CLEAR are available to set/clear host interrupt requests to the local CPU.



The bits LIO-LI3 and TI0 - TI3 are ored and connected to the IRQ1 line of the PPC405 processor. An interrupt is generated, if a bit in the LINT or TINT register is set.

LINT_SET 0x20 (lword, r/w) 31 30 29 28 27 26 25 24 23 – 0

Reserved LI3 LI2 LI1 LI0 Not used

LINT_CLEAR 0x24 (lword, r/w) 31 30 29 28 27 26 25 24 23 – 0

Reserved LI3 LI2 LI1 LI0 Not used

LI[3..0] Writing one of these bits sets/resets interrupt requests from the host to the local CPU. Both registers are accessed in hot-1 technique: Writing a one to LI[3..0] sets/clears the corresponding bit in the registers.


TINT_SET 0x28 (lword, r/w) 31 30 29 28 27 26 25 24 23 – 0

Reserved TI3 TI2 TI1 TI0 Not used

TINT_CLEAR 0x2c (lword, r/w) 31 30 29 28 27 26 25 24 23 – 0

Reserved TI3 TI2 TI1 TI0 Not used

TI[3..0] Writing one of these bits sets/clears interrupt requests from the host to the local CPU. Both registers are accessed in hot-1 technique: Writing a one to TI[3..0] sets/clears the corresponding bit in the registers.


4.2.7 Scratchpad register The scratchpad register is implemented on the CAN-PCIH for storage of hardware specific driver informations. This register is an read/write register and is accessible under the address 0x30

SCPR_REG 0x30 (lword, r/w) 31 30 29 28 27 26 25 24 23 – 0 S7 S6 S5 S4 S3 S2 S1 S0 not used

S[7..0] The bits can be used to store firmware specific driver informations.

CAN-PCIH (Hardware Manual) • Appendices 5 - 19


5 Appendices

5.1 Technical Data

CPU Type AMCC PPC405GPR Clock Frequency 266 MHz Bus Clock Frequency: 133MHz SDRAM, 33MHz local bus Memory SDRAM 64Mbyte (32bit wide) accessible from PCI and local bus. Boot FLASH 1MB, in-circuit programmable EEPROM 1KBit Interfaces CANbus 9 pin D-SUB connector, 1Mbit SJA1000 Stand-alone CAN-

controllers. Serial Interface 9 pin D-SUB connector, Baud rate 9600 bps. RS232 level. PCIbus interface specification Interface Controller PCI V2.2 compliant Integrated 32 bit PCI interface,

operating up to 33 MHz. 5V and 3.3V signalling environment. FIFOs for decoupling of transactions.

Form factor Short interface card Physical Dimensions Modul Size See figure 5 Slot requirements Single slot (includes CAN-PCIH/EXT expansion board) Weight TBD Power Requirements +3V3 (±5%) 660mA +5V (±5%) 200mA, 400mA with CAN-PCIH/EXT Power dissipation 3.2W, 4.2W with CAN-PCIH/EXT Environmental Specifications Temperature range 0..+70°C (operating) Humidity 0%..80%, non condensing CAN-bus isolation barrier 500V (with CAN isolation option only)

5 - 20 CAN-PCIH (Hardware Manual) • Appendices

12mm

15mm

95mm

93mm

130mm

figure 5: Board Dimensions




5.2 References These references direct you to manuals and specification that might help you when you attempt programming the CAN-PMC. Most of the documents can be downloaded from the Internet. Look for the WWW servers of the chip manufacturers. 1] PCI local bus specification, PCI Special Interest Group, Revision 2.2, 1997. [2] PMC, P1386, Draft 2.0 April 1995; P1386.1, Draft 2.0 April 1995. [3] PPC405GPR Databook The following titles are books for more in depth reading. If a book is in the list, it does not explicitly say that it is a good one. However, there is no book that we haven’t learned something from ... [4] John Bunda, Terence Potter & Robert Shadowen: PowerPC Microprocessor, SAMS

Publishing, 1. Auflage, 1995 Address List PCI Special Interest Group P.O. Box 14070 Portland, OR 97214 Phone: (503)797-4207 FAX: (503)234-6762 WWW: www.sigpci.com WWW-References Janz Automationssysteme AG: www.janz.deAMCC www.amcc.comPhilips www.semiconductors.philips.com

http://www.janz.de/

http://www.amcc.com/

http://www.semiconductors.philips.com/



5.3 Pin Assingment D-Sub connector (CAN-1 and CAN-2)

Pin Signalname Direction 1 EXVCC1) 2 CAN_L in/out 3 CAN_GND 4 RxD2) In 5 TxD2) out 6 CAN_GND 7 CAN_H in/out 8 - - 9 - -

table 3:Pin assignment of 9-pol DSub 1) optional EXVCC (+5V) voltage is available on pin1 (if

R100 for CAN1 and R201 for CAN2 are equipped). 2) optionally available RS232 signals at connector for

CAN1. With isolated CAN interface, CAN_GND is not a suitable GND reference for the RS232 signals.



5.4 Pin Assingment Flat Cable Header (CAN-3 and CAN-4) This section show the pin assignment for the flat cable header on the CAN-PCIH/EXT.

Pin Signalname Direction 1 - - 2 CAN_GND - 3 CAN_L in/out 4 CAN-H in/out 5 CAN_GND - CAN3 6 - - 7 - - 8 EXVCC1) - 9 - - 10 - - 11 - - 12 CAN_GND - 13 CAN_L in/out 14 CAN-H in/out 15 CAN_GND - CAN4 16 - - 17 - - 18 EXVCC1) - 19 - - 20 - -

table 4:Pin assignment flat cable header 1) optional EXVCC (+5V) voltage is available on pin1 (if

R100 for CAN3 and R201 for CAN4 are equipped). The CAN-PCIH/EXT comes with a fan-out cable that provides two 9pin D-SUB mounted on a standard PCI bracket.



5.5 Product History Note that changes in the major version number are related to a PCB redesign. Though, PCB redesign need not be related to functional changes, but might have been carried out for manufacturing purposes only.

Version Release Date

Name Changes

V1.0 25.07.2005 as • initial version

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5.6 Manual History

Version Release Date

Name Changes

V1.0 12.08.2005 as • initial version

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Documents

CAN-PCIH Hardware Manual - Janz Tec...CAN-PCIH (Hardware Manual) • Installation 2 - 7 2 Installation When opening the shipping package of the CAN-PCIH you should immediately check