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Institut de RadioAstronomie Millimétrique
IRAM-COMP-009 Revision: 1 29 JUN 2004 Contact Author
CanAna: CAN DAC/ADC Board
Owner Francis Morel ([email protected])
Keywords:
Approved by: Date Signature:
A.Perrigouard December 2005
IRAM PdB CAN Specification
Change Record
REVISION DATE AUTHOR SECTION/PAGE AFFECTED
REMARKS
1 Apr 26 2005 Francis Morel
Content
DESCRIPTION OF THE “CANANA” BOARD: .................................................................3 1.1 CANANA functionalities:.................................................................................... 3 HARDWARE:.............................................................................................................................3 1.2 CANANA description:......................................................................................... 3
1.2.1 Controller enclosure: .......................................................................... 3 1.2.2 Controller front-panel: ........................................................................ 3 1.2.3 Controller schematics ......................................................................... 4 1.2.4 Adjustments: ..................................................................................... 10 1.2.5 Performances: ................................................................................... 11
SOFTWARE:............................................................................................................................12 1.3 Brief description of the CAN protocol used on the Plateau de Bure:................. 12 1.4 CANANA Background task:.............................................................................. 12 1.5 CAN commands used by the CANANA board:................................................. 12
1.5.1 Summary of Control and Monitor points:......................................... 12 1.5.2 Detailed Control points:.................................................................... 13 1.5.3 Detailed monitor points: ................................................................... 13
1.6 CAN messages used for Receiver control: ......................................................... 14 1.
Create Date:June 2004 Author: F.Morel PdBNG Receiver CAN Interface Page 2 of 14
IRAM PdB CAN Specification
DESCRIPTION OF THE “CANANA” BOARD:
This board was designed to allow analog voltage generation and readout through the CAN Bus.
1.1 CANANA functionalities:
The CANANA outputs 16 analog 14-bit voltages (0-10Volt) and inputs 16 analog 16-bit voltages (0-10 Volt).
HARDWARE:
1.2 CANANA description:
The board is built around a DIP-164 module developed by Systec. This module is a 40-pin DIP component, it includes Microprocessor, 32k RAM, 32k Flash-EPROM, RS-232 interface, Full-CAN interface. The CAN is not opto-isolated. A 14-bit SPI DAC (AD5390) is in charge of the 16 analog outputs. All outputs share a common ground reference. A 16-bit SPI ADC (AD977) is used for reading the 16 differential inputs. Each input has its own ground reference.
1.2.1 Controller enclosure:
The controller is enclosed in a small metal box, which may be plugged on a DIN rail. The box is powered (24V, 100 mA) through the CAN connector.
1.2.2 Controller front-panel:
3 LEDS monitor: -Power (green) -CAN Message (yellow) -CAN Error (red). 2 DB-9 male connectors are used for connection to the CAN bus. The 2 connectors are tied pin-to-pin. Connections: 2: CAN Low 7: CAN High 3: CAN Gnd 5: +24 Volt 9: 0 Volt 2 high-density SMC 50-pin connectors are used for analog I/O. Connections: Pin number ADC input connector DAC output connector 1 IN0- GND 2 IN0+ OUT0 3 IN1- GND
Create Date:June 2004 Author: F.Morel PdBNG Receiver CAN Interface Page 3 of 14
IRAM PdB CAN Specification
4 IN1+ OUT1 5 IN2- GND 6 IN2+ OUT2 7 IN3- GND 8 IN3+ OUT3 9 IN4- GND 10 IN4+ OUT4 11 IN5- GND 12 IN5+ OUT5 13 IN6- GND 14 IN6+ OUT6 15 IN7- GND 16 IN7+ OUT7 17 IN8- GND 18 IN8+ OUT8 19 IN9- GND 20 IN9+ OUT9 21 IN10- GND 22 IN10+ OUT10 23 IN11- GND 24 IN11+ OUT11 25 IN12- GND 26 IN12+ OUT12 27 IN13- GND 28 IN13+ OUT13 29 IN14- GND 30 IN14+ OUT14 31 IN15- GND 32 IN15+ OUT15 33 GND GND 34 GND GND 35-50 UNUSED UNUSED
1.2.3 Controller schematics
Create Date:June 2004 Author: F.Morel PdBNG Receiver CAN Interface Page 4 of 14
IRAM PdB CAN Specification
Date: February 23, 2005Sheet 5of 5
SizeDocument Number
REV
B
Title
BLOCK DIAGRAM
CANANA BOARD
Sheet 2
/ADCSEL
/ADC-CVRT
SERCLK
SERDAT
DACREF
A[0..4]
Sheet 1
/ADCSEL
/ADC-CVRT
SERCLK
SERDAT
DACREF
/DACSEL
/DAC-RST
SERCLK
SERDAT
DACREF
A[0..4]
Sheet 3
/DACSEL
SERCLK
SERDAT
DACREF
/DAC-RST
16 ANALOG OUTPUTS
uCONTROLLER
16 ANALOG INPUTS
A[0..4]
Create Date:June 2004 Author: F.Morel PdBNG Receiver CAN Interface Page 5 of 14
IRAM PdB CAN Specification
1
2
3 4
LL101
1 2
C103
1 2
C102
1
2
3
4
U104
1 2
C101
1
2
3
10
11
12
1314
15
22
23
24
U103
R111
1
2
3
4
5 6
7
8
U105
12C115
12C114
12C113
1 2
C116
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
2122
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
U101 1
2
C104
1 2 3
K101
1 2 3
K102
2 1
D101
2
3 1
Q101
J101
R101
R102
2
3 1
Q102
2 1
D102
R106
15
16
14
11
7
10
12
13
9
8
1
3
2
6 4
5
U102
R107
R104
R105
R103
1 2
DZ101
1 2
DZ102
1 2
C105
1 2
C106
1 2
C107
1 2
C108
R108
R109
R110
J102
S101
S102
12C109
12C110
12C111
12C112
MURATA
0.1uF
0.1uF
DBR
4.7uF/35V
+VIN
-VOUT
CMN
CMN
+VOUT
-VIN
-VIN
+VOUT
CMN
CMN
-VOUT
+VIN
TEL3-2422
47 1/2W
LBO
SET
GND
OUT
IN
GND
OFF
LBI
MAX883CSA
0.1uF
4.7uF
1uF
0.1uF
P3.11
P3.10
P3.4
BOOT
P3.6
GND
GND
GND
VAREF
VAGND
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
RESIN
GND
P8.0
P8.1
P1H.0
P1H.1
P1H.2
P1H.3
P1H.4
P1H.5
P1H.6
P1H.7
P8.2
P8.3
GND
GND
GND
P4.5
CAN-L
CAN-H
P4.6
VCC
DIP164
0.1uF
VN10
12
34
56
78
91011
1213
1415
1617
1819
20
HEADER 10X2
1K5
1K5
VN10
4K7
GND
VCC
T1O
T1I
T2O
T2I
R1O
R1I
R2O
R2I
C1+
C1-
V+
V-
C2+
C2-
MAX202CPE
4K7
4.7
4.7
1K5
5V1
5V1
0.1uF
0.1uF
0.1uF
0.1uF
00
0
12
34
56
78
910
3M 3591
/BOOT
RESET
0.1uF
0.1uF
0.1uF
1uF
Date: June 27, 2005Sheet 1of 5
SizeDocument Number
REV
BF. MOREL
Title
CAN CONTROLLER
CANANA BOARD
Polarity of 24V1 is irrelevant
Low-drop 5 VoltRegulator
TO MSG LED
TO ERR LED
A[0..4]
SERDAT
SERCLK
/ADCSEL
/DACSEL
/DAC-RST
/ADC-CVRT
GND
CAN-L
CAN-H
BOOT
RESET
+24V1
-12V
-12V
+12V
VCC
+12V
+12V
0V1
EARTH
VCC
VCC
CAN-ERR
CAN-MSG
VCC
/BOOT
/ADC-CVRT
/DAC_RST
VCC
CAN-H
CAN-L
A3A2
SERDAT
SERCLK
A4
A[0..4]
A1A0/DACSEL
/ADCSEL
VCC
RSTIN
VCC
VCC
+24V1
0V1
V24-TX
SERIN
VCC
V24-RX
SEROUT
ADCDGND
DACDGND
V24-TX
V24-RX
VCC
VCC
Create Date:June 2004 Author: F.Morel PdBNG Receiver CAN Interface Page 6 of 14
IRAM PdB CAN Specification
13
2
P202
1
2
C233
1
2C234
1
2
3
4
5 6 7 8
U205
12C232
12C231
3
2
6
5
81
74U203
R207
R206
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1516
17
18
19
20
21
22
23
24
25
26
27
28
U201
1
2
3
4
5
6
7
8
910
11
12
13
14
15
16
RR201
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RR202
R208
R209
2
3
7 4
6
158U207
1
2
C204
12C235
R201
12C230R204
1
2
3
4
5
6
7
8
9
10
11121314151617181920
U204
1
2C206
R202
R203
1 2C205
1
2 C203
1 2
C202
1
2
3
4
5
6
7
8
910
11
12
13
14
15
16
RR203
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RR204
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1516
17
18
19
20
21
22
23
24
25
26
27
28
U202
1 2
C201
13
2P201
1 2
C217
1 2C236
L203
L201
1
2C221
J201
1 2
C207
1 2
C208
1 2
C209
1 2
C210
1 2
C211
1 2
C212
1
2C222
1
2C223
1
2C224
1 2C228
L202
1 2C237
L204
12C238
1
2
3
4
5 6 7 8
U206
12C220
12C219
R205
1 2C229
1
2C225
1
2C226
1
2C227
1 2
C213
1 2
C214
1 2
C215
1 2
C216
1 2
C218
1 2
C239
1 2
C240
1 2
C241
1 2
C242
1 2
C243
50K
4.7uF
4.7uF
NC+VIN
TEMP
GND
TRIM
VOUTNC
2.5/3
AD780
1uF
0.1uF
AD620BR
680K
680K
VDD
OUTB
NC
IN8B
IN7B
IN6B
IN5B
IN4B
IN3B
IN2B
IN1B
GRND
NC
NC
A2A1
A0
ENA
IN1A
IN2A
IN3A
IN4A
IN5A
IN6A
IN7A
IN8A
VSS
OUTA
DG407DY
8x470 1%
8x470 1%
1K
1K
AD8671AR
2.2nF 1% Pol
10nF
100
2.2uF
1M
R1IN
AGND1
R2IN
R3IN
CAP
REF
AGND2
SB/BTC
EXT/INT
DGND
SYNC
CLK
DATA
TAG
R/C
CS
BUSY
PWRD
VANA
VDIG
AD977
NO
200
33K2
2.2nF 1% POL
NO
NO
8x470 1%
8x470 1%
VDD
OUTB
NC
IN8B
IN7B
IN6B
IN5B
IN4B
IN3B
IN2B
IN1B
GRND
NC
NC
A2A1
A0
ENA
IN1A
IN2A
IN3A
IN4A
IN5A
IN6A
IN7A
IN8A
VSS
OUTA
DG407DY
NO
50K
2.2uF
4.7uF
2.2uH
2.2uH
0.1uF
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
4142
4344
4546
4748
4950
SMC-B 50
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
4.7uF 2.2uH
4.7uF
2.2uH
1uF
LBO
SET
GND
OUT
IN
GND
OFF
LBI
MAX883CSA
0.1uF
4.7uF
0
4.7uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
Date:September 1, 2005Sheet 2of 5
SizeDocument Number
REV
BF. Morel
Title
16-CHANNEL 16-BIT ADC
CANANA BOARD
GAIN
16-bit settling time: 100 usec
2.5 V REFERENCE
/ADCSEL
/ADC-CVRT
DACREF
OFFSET
16-BIT SPI ADC
Full Scale: 0-10 Volt
SERDAT
SERCLK
A[0..4]
Low-drop 5V Regulator
ADCAGND
ADCAVCC
ADCAGND
ANIN-
ANIN+
ADCVSS
ADCGND
ADCVSS
ADCAGND
ADCVDD
IN-8
IN-9
IN-10
AIN-8
AIN-9
AIN-10
AIN+8
AIN+9
AIN+10
AIN+11
AIN-11
AIN-12
AIN-13
AIN-14
AIN-15
IN+8
IN+9
IN+10
IN+11
IN-11
IN-12
IN-13
IN-14
IN-15
IN-15
IN-14
IN-13
IN-12
IN-11
IN-10
IN-9
IN-8
OUT-
OUT+
A0
A1
IN+15
IN+14
IN+13
IN+12
IN+11
IN+10
IN+9
IN+8
A3
ADCVDD
ADCVDD
ADCAGND
ADCAVCC
ADCREF
ADCDVCC ADCDGND
ADCAGND
ADCVSS
ADCAGND
ADCAVCC
ADCAGND
A2
ADCAGND
IN+12
IN+13
IN+14
IN+15
IN-0
IN-1
IN-2
IN-3
AIN+12
AIN+13
AIN+14
AIN+15
AIN-0
AIN-1
AIN-2
AIN-3
AIN-4
AIN-5
AIN-6
AIN-7
AIN+0
AIN+1
AIN+2
AIN+3
IN-4
IN-5
IN-6
IN-7
IN+0
IN+1
IN+2
IN+3
IN-7
IN-6
IN-5
IN-4
IN-3
IN-2
IN-1
IN-0
OUT-
ADCVDD
OUT+
A0
A1
IN+7
IN+6
IN+5
IN+4
IN+3
IN+2
IN+1
IN+0
A4
ADCVSS
ADCAGND
ADCAGND
ADCDGND
ADCDVCC
ADCDVCC
A[0..4]
A2
I N + [ 0 . . 1 5 ]
ADCAGND
I N - [ 0 . . 1 5 ]
IN+4
IN+5
IN+6
IN+7
AIN+4
AIN+5
AIN+6
AIN+7
A I N - [ 0 . . 1 5 ]
A I N + [ 0 . . 1 5 ]
AIN-0
AIN-1
AIN-2
AIN-3
AIN-4
AIN-5
AIN+0
AIN+1
AIN+2
AIN+3
AIN+4
AIN+5
IN-15
IN-14
IN-13
IN-12
IN-11
IN-10
IN+15
IN+14
IN+13
IN+12
IN+11
IN+10
ADCVDD
ADCVDD
ADCVDD
ADCAGND
ADCVSS
ADCVSS
ADCVSS
ADCAGND
ADCAGND
ADCVDD
ADCVSS
+12V
-12V
ADCAGND
ADCDGND ADCAVCC
ADCVDD
ADCDGND
ADCAGND
ADCDVCC
ADCDVCC
ADCAVCC
ADCAGND
ADCDGND
ADCDGND
IN+9
IN+8
IN+7
IN+6
IN+5
IN+4
IN+3
IN-9
IN-8
IN-7
IN-6
IN-5
IN-4
IN-3
AIN+6
AIN+7
AIN+8
AIN+9
AIN+10
AIN+11
AIN+12
AIN+13
AIN+14
AIN+15
ADCAGND
AIN-6
AIN-7
AIN-8
AIN-9
AIN-10
AIN-11
AIN-12
AIN-13
AIN-14
AIN-15
ADCAGND
IN-2
IN-1
IN-0
IN+2
IN+1
IN+0
ADCAGND
Create Date:June 2004 Author: F.Morel PdBNG Receiver CAN Interface Page 7 of 14
IRAM PdB CAN Specification
J202
1 2C315
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
2728293031323334353637383940414243444546474849505152
U301
1
2C312
1
2C313
1
2C307
1
2C308
1
2C303
1
2C304
L303
1 2C320
1
2
3
4
5 6
7
8
U302
1
2C305
1
2C306
1
2C310
1
2C314
L302
1 2C302
L301
1 2C301
12C318
L304
R301
12C316
12C317
1 2C319
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
4142
4344
4546
4748
4950
SMC-B 50
2.2uF
CLR
NCNCREF-GND
REF
SIG-GND1
DAC-GND1
AVDD1
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
AGND1
VOUT5
VOUT6
VOUT7
MON-IN1
MON-IN2
MON-OUT
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
DAC-GND2
SIG-GND2
VOUT13
VOUT14
VOUT15
AGND2
AVDD2NCNCNCNC
RESET
BUSY
LDAC
DCENPD
SPI/I2C
DGND
DVDD
DVDD
DGND
DVDD
SDOUT
SCLK
SDIN
SYNC
DGND
AD5390BST-5
4.7uF
4.7uF
0.1uF
0.1uF
0.1uF
0.1uF
2.2uH
4.7uF
LBO
SET
GND
OUT
IN
GND
OFF
LBI
MAX883CSA
4.7uF
4.7uF
0.1uF
4.7uF
2.2uH
4.7uF
2.2uH
4.7uF
1uF
2.2uH
0
0.1uF
4.7uF
4.7uF
Date: June 16, 2005Sheet 3of 5
SizeDocument Number
REV
B
Title
16-CHANNEL 14-BIT DAC
CANANA BOARD
5V to 10V Amplifiers
AMPLIS
DACOUT[0..15]
VOUT[0..15]
14-BIT DAC
Full Scale: 0-5 Volt
SERDAT
SERCLK
/DACSEL
DACREF
/DAC-RST
Low-drop 5 Volt Regulator
DACAGND
DACDVCC
DACAGND
DACDGND
DACDVCC
DACOUT0
DACOUT1
DACOUT2
DACOUT3
DACOUT4
DACOUT5
DACOUT6
DACOUT7
DACAVCC
DACAGND
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
DACAGND
VOUT13
VOUT14
VOUT15
DACAGND
DACOUT8
DACOUT9
DACOUT10
DACOUT11
DACOUT12
DACAGND
DACOUT15
DACOUT14
DACOUT13
DACAGND
DACAVCC
DACAGND
DACDVCC
DACDGND
DACDGND
DACDVCC
DACAVCC
DACAGND
DACOUT[0..15]
VOUT[0..15]
DACAGND
DACAVCC
+12V
DACAVCC
DACAVCC
DACAVCC
DACAGND
DACAGND
DACAGND
DACDVCC
DACDVCC
DACDGND
DACDGND
DACDVCC
DACDVCC
DACDGND
DACDGND
+12V
DACAGND
DACVDD
-12V
DACAGND
DACVSS
DACDGND
DACDGND
DACAGND
DACDVCC
Create Date:June 2004 Author: F.Morel PdBNG Receiver CAN Interface Page 8 of 14
IRAM PdB CAN Specification
R418
3
2
1
4 1 1
U403A
R402
3
2
1
4 1 1
U401A
5
6
7U401B
R401
R404
5
6
7U403B
R420
R417
1
2C401
1
2C402
1
2C403
1
2C404
R422
R419
R421
10
9
8U403C
12
13
14U403D
R406
10
9
8U401C
12
13
14U401D
R403
R405
3
2
1
4 1 1
U402A
R407
R408
3
2
1
4 1 1
U404A
R424
R423
1
2C405
1
2C406
1
2C407
R426
R425
R410
R409
5
6
7U402B
10
9
8U402C
R411
R412
R414
5
6
7U404B
10
9
8U404C
R428
R430
R427
1
2C408
R432
R429
R431
12
13
14U404D
R416
12
13
14U402D
R413
R415
10K
LT1369
10K
LT1369
LT1369
10K2
10K
LT1369
10K
10K2
0.1uF
0.1uF
0.1uF
0.1uF
10K
10K2
10K2
LT1369
LT1369
10K
LT1369
LT1369
10K2
10K2
LT1369
10K2
10K
LT1369
10K
10K2
0.1uF
0.1uF
0.1uF
10K
10K2
10K
10K2
LT1369
LT1369
10K2
10K
10K
LT1369
LT1369
10K
10K
10K2
0.1uF
10K
10K2
10K2
LT1369
10K
LT1369
10K2
10K2
Date: June 27, 2005Sheet 4of 5
SizeDocument Number
REV
B
Title
AMPLIFIERS
CANANA BOARD
16 AMPS WITH GAIN = 2
VOUT[0..15]
DACOUT[0..15]
DACOUT8
DACVDD
DACAGND
VOUT8
DACOUT0
DACAGND
DACVDD
VOUT0
VOUT1
DACVSS
DACOUT1
DACAGND
VOUT9
DACOUT9
DACVSS
DACAGND
DACVDD
DACAGND
DACAGND
DACAGND
DACAGND
DACVSS
DACVDD
DACVSS
DACOUT10
DACOUT11
DACAGND
VOUT10
DACOUT2
DACOUT3
DACAGND
VOUT2
VOUT[0..15]
VOUT3
DACVDD
DACAGND
VOUT11
DACVDD
DACAGND
DACOUT[0..15]
DACAGND
DACAGND
DACVSS
DACVDD
DACOUT12
DACVSS
DACAGND
VOUT12
DACOUT4
DACAGND
DACVSS
VOUT4
VOUT5
VOUT6
DACOUT5
DACOUT6
DACAGND
DACAGND
VOUT13
VOUT14
DACOUT13
DACOUT14
DACAGND
DACAGND
DACVSS
DACVDD
DACAGND
DACAGND
DACOUT15
DACAGND
VOUT15
DACOUT7
DACAGND
VOUT7
Create Date:June 2004 Author: F.Morel PdBNG Receiver CAN Interface Page 9 of 14
IRAM PdB CAN Specification
1.2.4 Adjustments:
The ADC is iram-adjusted for offset and gain. This initial adjustment is made with 2 potentiometers, which should not be modified. An automatic software adjustment is available; the offset and gain correction parameters for each channel are stored in the EEPROM of the controller. A similar DAC software adjustment procedure can then be run, using both DAC and ADC, connected pin-to-pin through the front-panel connectors with a turn-around cable. These commands are protected and can be performed only with the right software key. They are normally used once, and should not be necessary later. They require anyway special equipment, a precision voltage generator and a precision voltmeter. The calculated corrections stored in the EEPROM are immediately applied to the DAC outputs and to the ADC inputs. They will be recalled and applied upon each reset or startup. Sending CAN message [CAN-ID + 0x190] allows temporary (until next reset) disabling these corrections.
1.2.4.1 ADC offset adjustment:
This adjustment is to be made first, prior to ADC Gain adjustment. Connect all ADC inputs to a 10.0 milliVolt source. Send to the board the CAN message [CAN-ID+0x190], with DLC = 1 (dummy data). Send to the board the CAN message [CAN-ID+0x1A0], with DLC = 4 and bytes[0-3] containing the software key. Reset the board.
1.2.4.2 ADC gain adjustment:
This adjustment should be made after ADC Offset adjustment only. Connect all ADC inputs to a 9.9900 Volt source. Send to the board the CAN message [CAN-ID + 0x1B0], with DLC = 4 and bytes[0-3] containing the software key. Reset the board.
1.2.4.3 DAC offset and gain Adjustment:
This adjustment should be made after the ADC adjustments only. Connect the special pin-to-pin cable, thus connecting each DAC output [x] to the mating ADC input[x]. Send then the CAN message [CAN-ID+0x1D0], with DLC=4 and bytes[0-3] containing the software key, to the board. This will perform automatically the offset and gain calibration of the DAC, using the ADC as a reference. The calibration may last about one second. After calibration, all 16 DAC output voltages should be 5.000 Volt +/- 1.22 mV. This helps for checkout. Reset the board.
1.2.4.4 ADC and DAC correction parameters:
The calculated corrections are stored in a non-volatile EEPROM, and can be read: Gain/offset corrections are readable for each channel [0-15] sending following CAN messages: ADC correction parameters readout: [CAN-ID + 0x1C0 + Channel Number]. DAC correction parameters readout: [CAN-ID + 0x1E0 + Channel Number]. The reply message is 7 bytes long and has following structure: Byte0 Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Gain[31-24] Gain[23-16] Gain[15-8] Gain[7-0] Offset[15-8] Offset[7-0] CAN Error
Report Offset correction format: 16-bit signed (-32768 to +32767), LSB = 1. Offset correction parameter should always be in the range +/- 15 (between 0xFFF1 and 0x000F).
Create Date:June 2004 Author: F.Morel PdBNG Receiver CAN Interface Page 10 of 14
IRAM PdB CAN Specification
Gain correction format: 32-bit unsigned, fix format (0 to 65536), LSB = 1/ 65536. Value 0x00 00 00 00 = 0.00000 Decimal Value 0x00 00 FF F9 = 0.99989 Decimal Value 0x00 01 00 00 = 1.00000 Decimal Value 0x00 01 00 06 = 1.00009 Decimal Value 0xFF FF FF FF = 65536 Decimal Gain correction parameter should always be close to 1 (between 0x00 00 F0 00 and 0x00 01 11 11). All these corrections are automatically fetched from the EEPROM upon startup or reset. They will be applied by default, and will be suspended (until reset) if the command [CAN-ID + 0x190] is sent to the board.
1.2.5 Performances:
DAC/ADC offset and gain errors (including the analog chain errors) are within +/- 2 LSB after calibration. For the ADC, this calibration is made by averaging 16 readouts of the same input. The ADC and the DAC use the same external high precision 3 ppm/C reference (AD780). The ADC has a 16-bit resolution; the LSB value is thus 153 microVolt. The conversion time is 32 microseconds when reading repeatedly the same channel. It will increase to 110 microseconds when reading randomly different channels. The CAN frames (2, one for command and one for reply) introduce a delay of the same order. The ADC has a guaranteed linearity of +/- 2 LSB and drift of +/-2 ppm/C (200 microVolt for 10C). The input amplifiers introduce a 3 microVolt/C error. The total worst case error is in the range (+/- 3 LSB), which means that the maximum ADC readout error will be +/- 500 microVolt in a 10C temperature range. The DAC is a 14-bit device, with a 610 microVolt LSB. The settling time of the outputs is around 100 microseconds, for a 10 Volt step. A complete output setting will thus take 230 microseconds (one CAN frame plus one conversion). The DAC has a guaranteed relative accuracy of +/- 3 LSB, and neglictible drift. The maximum DAC output voltage error will be +/- 2 mV. Here is a table of the DAC outputs and the ADC inputs voltages. For that measurement, DACs and ADCs are connected in a back-to-back configuration. These voltages are compared to the actual value, read with a precision H-P voltmeter: Value written to DAC Actual (measured) value Value read from ADC 0 mV 1.0 mV 1.0 mV 9.7 mV 10.0 mV 10.1 mV 39.0 mV 39.2 mV 39.2 mV 78.1 mV 78.6 mV 78.6 mV 0.3125 V 0.3131 V 0.3131 V 0.6250 V 0.6252 V 0.6251 V 1.2500 V 1.2504 V 1.2503 V 2.5000 V 2.5011 V 2.5011 V 5.0000 V 5.0013 V 5.0011 V 9.9902 V 9.9922 V 9.9919 V 10.0000 V 10.0000 V 10.0000 V The full scale is adjusted at 10 Volt for DAC and ADC. N.B: The ADC input differential impedance is > 1Mohm, its common mode voltage is +/- 10 Volt. This implies that the source impedance of the measured voltage must be < 15 Ohm to guarantee a valid LSB readout. The DAC outputs share the same ground. They should always be loaded with R > 10 kOhm, in order to avoid cable-induced offset errors or overloading the output amplifiers.
Create Date:June 2004 Author: F.Morel PdBNG Receiver CAN Interface Page 11 of 14
IRAM PdB CAN Specification
SOFTWARE:
1.3 Brief description of the CAN protocol used on the Plateau de Bure:
N.B: A detailed description of the CAN protocol used on Plateau de Bure is available as document /netapp1/computer/doc/can/canPdBNG/canPdBNG.pdf. Alain Perrigouard wrote it. Each CAN message includes a header. Inside this header, receiving nodes, to decide whether they are concerned with the current message, use 2 fields: The CAN ID (unique message identifier on 29 bits), and the DLC (Data Length Count) which declares the number of data bytes of the message. If both these parameters match the values expected by a node, it will accept the message. Each CAN controller has a unique NODE ID, and uses it to filter the incoming CAN messages. The CAN2I2C Controller accepts 3 kinds of message: Broadcast messages, Control messages and Monitoring messages. Broadcast messages contain no data. Upon receipt of a Broadcast message, the CAN Controller replies with a message using its own NODE ID as CAN ID. Control messages must contain at least one byte of data, eventually dummy data if the command is completely defined by the identifier. When receiving a control message, the CAN2I2C Controller will reply with an acknowledge message containing NO data, and having the same CAN-ID as the previously received message. Monitoring messages contain NO data (DLC = 0). When receiving a monitoring message, the CAN2I2C Controller replies with a message containing a strictly defined number of data bytes, still using the CAN-ID of the received command message.
1.4 CANANA Background task:
The controller acts a slave device: It receives CAN messages from the CAN master PC, does the requested job, and replies with CAN acknowledge/data messages. The incoming CAN messages have higher priority than the background task, triggering the CAN interrupt of the C164. A buffer allows storing up to 16 CAN messages.
1.5 CAN commands used by the CANANA board:
1.5.1 Summary of Control and Monitor points:
“i” [0-15] is the channel number. Function CAN ID Data
Size Description
Get Analog Input[i] NODE_ID+0x100+i 3 Get analog input [i] Set Analog Output[i] NODE_ID+0x110+i 2 Set Analog output [i] Get Analog Output[i] NODE_ID+0x120+i 3 Get Analog output [i] Set corrections OFF NODE_ID+0x190 1 Disable ADC/ADC corrections Set ADC Offset auto-calibration NODE_ID+0x1A0 4 Set ADC Offset calibration start Set ADC Gain auto-calibration NODE_ID+0x1B0 4 Start ADC Gain calibration Get ADC Channel[i] correction parameters
NODE_ID+0x1C0+i 8 Get ADC Channel[i] gain and offset calculated corrections
Set DAC auto-calibration NODE_ID+0x1D0 4 Start DAC Offset and Gain calibration
Get DAC Channel[i]correction parameters
NODE_ID+0x1E0+i 7 Get DAC Channel[i] gain and offset calculated corrections
Set Serial Number NODE_ID+0x1FD 8 Set 64-bit board Serial Number Set NODE_ID NODE_ID+0x1FE 8 Set the new board NODE_ID Create Date:June 2004 Author: F.Morel PdBNG Receiver CAN Interface Page 12 of 14
IRAM PdB CAN Specification
Set reset NODE_ID+0x1FF 1 Reset the board
1.5.2 Detailed Control points:
Function CAN ID Data Size
Description
Set Analog Output[i] NODE_ID+0x110+i 2 Set 14-bit Analog output [i] requested value. MAX value: 0x3FFF 0x3FFF == 10.000 Volt Byte[0,1]: data unsigned value
Set correction parameters OFF NODE_ID+0x190 1 Disable ADC/ADC corrections, applies until next Reset. All Offset corrections = 0 All Gain corrections = 1.0
Set ADC Offset auto-calibration NODE_ID+0x1A0 4 Start ADC Offset calibration. Adjusts automatically all 16 channels. All ADC inputs must first be connected to a 10.0 mVolt reference voltage. Bytes[0-1]: Security key1. Bytes[2-3]: all zeros
Set ADC Gain auto-calibration NODE_ID+0x1B0 4 Starts ADC Gain calibration. Adjusts automatically all 16 channels. All ADC inputs must first be connected to a 9.9900 Volt reference voltage. Bytes[0-1]: Security key1. Bytes[2-3]: all zeros
Set DAC auto-calibration NODE_ID+0x1D0 4 Start DAC Offset and Gain calibration. Each DAC output channel must first be connected to the same ADC input channel. Bytes[0-1]: Security key1. Bytes[2-3]: all zeros
Set Serial Number NODE_ID+0x1FD 8 Set 64-bit board Serial Number Byte[0-1]: Security key1. Byte[2-7]: New Serial Number.
Set NODE_ID NODE_ID+0x1FE 8 Set the new board NODE_ID Byte[0-3]: Security key2. Byte[4-7]: New NODE_ID.
Set reset NODE_ID+0x1FF 1 Reset the board, similar to shutdown/restart.
1.5.3 Detailed monitor points:
Function CAN ID Data Size
Description
Get Analog Input[i] NODE_ID+0x100+i 3 Get analog input [i] actual value: Max value: 0xFFFF 0xFFFF == 10.000 V Byte[0-1]: data unsigned value. Byte[2]: transaction report: Bit[2]: CAN Error.
Get Analog Output[i] NODE_ID+0x120+i 3 Get Analog output[i] requested value:
Create Date:June 2004 Author: F.Morel PdBNG Receiver CAN Interface Page 13 of 14
IRAM PdB CAN Specification
Max value: 0x3FFF 0x3FFF == 10.000 V Byte[0-1]: data unsigned value. Byte[2]: transaction report: Bit[2]: CAN Error.
Get ADC Channel[i] correction parameters
NODE_ID+0x1C0+i 7 Get ADC Channel[i] gain and offset calculated corrections. Bytes[0-3]: Gain correction. Unsigned, LSB = 1/65536. Bytes[4-5]: Offset correction. Signed. Byte[6]: Transaction report. Bit[2]: CAN Error.
Get DAC Channel[i]correction parameters
NODE_ID+0x1E0+i 7 Get DAC Channel[i] gain and offset calculated corrections. Bytes[0-3]: Gain correction. Unsigned, LSB = 1/65536. Bytes[[4-5]: Offset correction. Signed. Byte[6]: Transaction report. Bit[2]: CAN Error.
1.6 CAN messages used for Receiver control:
See document “CANpdBNG”
Create Date:June 2004 Author: F.Morel PdBNG Receiver CAN Interface Page 14 of 14
