Car park Digital controller

CAR PARK DIGITAL CONTROLLER

2010

MOHAMAD MUDDASSIR

GHOORUN

TP018073



2

DIGITAL ASSIGNMENT:

CAR PARK CONTROLLER

BY

MOHAMAD MUDDASSIR GHOORUN

MODULE CODE: EE008-3-5-2-DELC

LECTURER: MR. HUSSEIN FADHIL

HAND OUT DATE:14 DEC 09

HAND IN DATE:15 JAN 10


3

TABLE OF CONTENTS:

1.OBJECTIVE

2.INTRODUCTION

3.SCHEMATIC OF DESIGN

4.CONSTRUCTION OF THE SYNCHRONOUS BCD UP/DOWN

COUNTER

TRUTH TABLE

K-MAPS

5.THE UP DOWN COUNTER

6.TRUTH TABLE AND K-MAP FOR DECODER

7.BCD TO 7-SEGMENT DECODER CIRCUIT

8.THE DISPLAY OUTPUT

NUMBER OF SLOTS

FULL DISPLAY

9.FINAL CIRCUIT

10.EXPLANATION OF OTHER PARTS USED

11.PRACTICAL DESIGN

12.CONCLUSION

13.SPECIFICATIONS

14.REFERENCES


4


5

1. OBJECTIVE:

The objective of the assignment is to design and construct a car

park digital controller circuit for 99 car parking slots using sequential and

combinational logic circuits which will receive the digital signals from two

sensors, one allocated in the ENTRANCE and another one in the EXIT of

the car park to display the number of empty slots or to display the word

FULL in case no more empty slots are available .


6

2.INTRODUCTION:

The car parking digital controller is a device usually

implemented in order to reduce daily parking commotion by indicating how

many parking slots are available. We could implement this technique in

APIIT’s parking as recently we have been facing some parking issues. This

controller will not only help us to ease the traffic parking issues but will also

drastically reduce the traffic jams due to over-parking sometimes people

face when they want to go out from their parking slots.

This controller may be of great use in public places like universities, malls,

condominiums, and crowded places amongst many others.

This design is based on two BCD up/down counters which receive clock

pulse from the ENTRANCE (EN) and EXIT (EX). The output of these

sensors is HIGH whenever there is a car either entering or leaving the car

park. Both these sensors are connected to a sequential digital circuit and

its output is connected to a decoder which in turn is connected to the 7

segment display to show how many empty slots are available or to display

the word “F U L L” when there is no more available empty slots.


7

3.SCHEMATIC OF THE DESIGN:

This schematic is based on three principles:

1. The inputs:

As we’ve mentioned before, the circuit receives signals (or

clock pulse) from both the EN (entrance) and the EX (exit).

2. The combinational logic comprising of the decoder and the counter:

By using K-maps and logic equations, we can either count up

or down according to the incoming input signal from the EX and the

EN. The output of the circuit is then sent to the decoder.

3. The output:

The output of the decoder is then connected to the 7

segment display for the final stage of our design.


8

COUNTER

DECODER

7- SEGMENT

DRIVER

EN EX

INPUTS

PROCESSING

STAGE

OUTPUT


9

4.CONSTRUCTION OF THE SYNCHRONOUS

BCD UP/DOWN COUNTER:

STEP1#

The synchronous BCD up/down counter will count up and down from 0 to

9. The amount of bits required for this design is given by the formula below:

(2n – 1). Therefore, (2

n – 1) must be equal to 9.

2n = 10

n = log 10/log 2

n = 3.3

Therefore, the amount of bits required is 4.

Another more simpler method to calculate the amount of bits is to

write the number in binary form. Thus, the number 9 is denoted by

1001. From here also, we can see that we need 4 bits for this

design.

Moreover, the importance of these bits is that each bit will have to

be represented by a flip flop. Hence, we’ll need 4 flip flops.


10

STEP 2#

As we can see from the above diagram, counting is done in both

directions, meaning that when the counter reaches 9 (1001) while

counting up, the next number will be 0 (0000). Also, when counter

is counting down and is at 0 (0000), the next number will be 9

(1001).

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001


11

STEP 3#

TRUTH TABLE FOR THE BCD UP/DOWN COUNTER:

PRESENT

STATE

NEXT STATES JK INPUTS

UP DOWN UP DOWN

𝑄𝐴 𝑄𝐵 𝑄𝐶 𝑄𝐷 𝑄𝐴 𝑄𝐵 𝑄𝐶 𝑄𝐷 𝑄𝐴 𝑄𝐵 𝑄𝐶 𝑄𝐷 𝐽𝐾𝐴 𝐽𝐾𝐵 𝐽𝐾𝐶 𝐽𝐾𝐷 𝐽𝐾𝐴 𝐽𝐾𝐵 𝐽𝐾𝐶 𝐽𝐾𝐷

0 0 0 0 0 1 0 0 0 1 9 1 0 0 1 0 0 0 1 1 0 0 1

1 0 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1

2 0 0 1 0 3 0 0 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1

3 0 0 1 1 4 0 1 0 0 2 0 0 1 0 0 1 1 1 0 0 0 1

4 0 1 0 0 5 0 1 0 1 3 0 0 1 1 0 0 0 1 0 1 1 1

5 0 1 0 1 6 0 1 1 0 4 0 1 0 0 0 0 1 1 0 0 0 1

6 0 1 1 0 7 0 1 1 1 5 0 1 0 1 0 0 0 1 0 0 1 1

7 0 1 1 1 8 1 0 0 0 6 0 1 1 0 1 1 1 1 0 0 0 1

8 1 0 0 0 9 1 0 0 1 7 0 1 1 1 0 0 0 1 1 1 1 1

9 1 0 0 1 0 1 0 1 0 8 1 0 0 0 1 0 0 1 0 0 0 1

10 1 0 1 0 X X X X X X X X X X X X X X X X X X







12

STEP 4#

GETTING THE MOST SIMPLIFIED EXPRESSIONS FROM THE K-

MAP:

PART 1: FOR THE DOWN COUNT:

JKA =B’C’D’ JKB = BC’D’ + AD’

JKC = BD’+CD’+AD’

JKD = 1

𝑄𝐶𝑄𝐷

𝑄𝐴𝑄𝐵 00 01 11 10

00 1

01

11 X X X X

10 1 X X

𝑄𝐶𝑄𝐷

𝑄𝐴𝑄𝐵 00 01 11 10

00

01 1

11 X X X X

10 1 X X

𝑄𝐶𝑄𝐷

𝑄𝐴𝑄𝐵 00 01 11 10

00 1

01 1 1

11 X X X X

10 1 X X

𝑄𝐶𝑄𝐷

𝑄𝐴𝑄𝐵 00 01 11 10

00 1 1 1 1

01 1 1 1 1

11 X X X X

10 1 1 X X


13

PART 2: FOR THE UP COUNTER:

JKA = BCD + AD JKB = CD

JKD = 1

JKC = A’D

𝑄𝐶𝑄𝐷

𝑄𝐴𝑄𝐵 00 01 11 10

00 X

01 X 1

11 1 X X

10 X X

𝑄𝐶𝑄𝐷

𝑄𝐴𝑄𝐵 00 01 11 10

00 1

01 1

11 X X X X

10 X X

𝑄𝐶𝑄𝐷

𝑄𝐴𝑄𝐵 00 01 11 10

00 1 1 1 1

01 1 1 1 1

11 X X X X

10 1 1 X X

𝑄𝐶𝑄𝐷

𝑄𝐴𝑄𝐵 00 01 11 10

00 1 1

01 1 1

11 X X X X

10 X X


14

5.THE UP DOWN COUNTER:

Using the above equations (both up and down), the following

circuit has been made and tested successfully. The OR gate in the circuit is

to choose which part of the circuit to activate that is we can choose either

the up counter or the down counter.

U1

JK_FF

J Q

~QK

RESET

CLK

SET

U2

JK_FF

J Q

~QK

RESET

CLK

SET

U3

JK_FF

J Q

~QK

RESET

CLK

SET

U4

JK_FF

J Q

~QK

RESET

CLK

SETV15 V

U5

AND3

U8

AND3

U9

AND3

U10

AND4

U11

OR2

U12

OR3

U6

DCD_HEX_DIG_BLUE

U7

AND4

U13

AND3U14

AND3

U15

AND3

U16

OR2

U17

OR2

U18

OR2

U19

OR2

J1

Ke y = U

J2

Ke y = D

U20A

74LS32N


15

6.TRUTH TABLE FOR THE DECODER:

Digits INPUTS OUTPUT

DISPLAY

7 SEGMENT TERMINALS

A B C D a b c d e f g

0 0 0 0 0 0 1 1 1 1 1 1 0

1 0 0 0 1 1 0 1 1 0 0 0 0

2 0 0 1 0 2 1 1 0 1 1 0 1

3 0 0 1 1 3 1 1 1 1 0 0 1

4 0 1 0 0 4 0 1 1 0 0 1 1

5 0 1 0 1 5 1 0 1 1 0 1 1

6 0 1 1 0 6 1 0 1 1 1 1 1

7 0 1 1 1 7 1 1 1 0 0 0 0

8 1 0 0 0 8 1 1 1 1 1 1 1

9 1 0 0 1 9 1 1 1 1 0 1 1

X X X X X X X X X X X X X






16

KARNAUGH MAP EXPRESSION

a

𝐶𝐷

AB 00 01 11 10

00 1 1 1

01 1 1 1

11 X X X X

10 1 1 X X

a = A +C +BD + BD

𝑏

𝐶𝐷

𝐴𝐵 00 01 11 10

00 1 1 1 1

01 1 1

11 X X X X

10 1 1 X X

𝑏 = 𝐵 + 𝐶𝐷 + CD

𝑐

𝑐 = 𝐵 + 𝐶 + 𝐷

𝐶𝐷

𝐴𝐵 00 01 11 10

00 1 1 1

01 1 1 1 1

11 X X X X

10 1 1 X X

𝑑

𝐶𝐷

𝐴𝐵 00 01 11 10

00 1 1 1

01 1 1

11 X X X X

10 1 1 X X

𝑑 = 𝐴 + BC + BD + CD + BCD


17

𝑒

𝑒 = 𝐵𝐷 + 𝐶𝐷

𝐶𝐷

𝐴𝐵 00 01 11 10

00 1 1

01 1

11 X X X X

10 1 X X

𝑔

𝐶𝐷

𝐴𝐵 00 01 11 10

00 1 1

01 1 1 1

11 X X X X

10 1 1 X X

𝑔 = 𝐴 + 𝐵𝐶 + 𝐵𝐶 + 𝐶𝐷

𝑓

𝐶𝐷

𝐴𝐵 00 01 11 10

00 1

01 1 1 1

11 X X X X

10 1 1 X X

𝑓 = 𝐴 + 𝐵𝐶 + 𝐵𝐷 + 𝐶𝐷

SUMMARY

PIN EQUATION

a A + B + BD +B’D’

b B’ + C’D’ +CD

c B + C’ + D

d A + B’C + B’D’ + CD’ + BC’D

e B’D’ + CD’

f A + BC’ + BD’ + C’D’

g A + BC’ + B’C + CD’

Table 4: Decoder Equations


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7. BCD TO SEVEN SEGMENT DECODER

CIRCUIT:

J1

Key = A

J2

Key = B

J3

Key = C

J4

Key = D

V112 V

U1

NOT

U2

NOT

U3

NOT

U5

A B C D E F G

CK

U6

AND2

U7

AND2

U8

OR2

U9

OR2

U10

OR2

U11

AND2

U12

AND2

U13

OR2

U14

OR2

U15

OR3

U16

AND3

U17

AND2

U18

AND2

U19

AND2

U20

OR5

U21

AND2

U22

AND2

U23

OR2

U24

AND2U25

AND2

U26

AND2

U27

OR4

U28

AND2

U29

AND2

U30

AND2

U31

OR4

R1

50Ω


19

8.THE FINAL DISPLAY OUTPUT:

The final output will be given by the 7 segment display. The final output is

divided into 2 main parts:

1. Free slots display

2. FULL display

The free slots display is the combinational logic equations and the output of

each decoder is connected to each of these displays.

The above shows an example of BCD to 7 segment display. The resistors

are limiting resistors used to protect the common cathode 7 segment

display.

NOTE:THE ABOVE CIRCUIT IS NOT USED IN THE ACTUAL CIRCUIT. I

AM ONLY USING THIS AS AN EXAMPLE.

U2

A B C D E F G

CK

R1

50Ω

12 15R2

50Ω

16 17R3

50Ω

18 19R4

50Ω

20 21R5

50Ω

22

23

R6

50Ω

24 25R7

50Ω

26

27

U1

4511BD_5V

DA7

DB1

DC2

DD6

OA 13

OD 10

OE 9

OF 15

OC 11OB 12

OG 14~EL5

~BI4

~LT3

GND

R8

50ΩGND

5


20

FULL DISPLAY:

The condition for the FULL display is that the both counters’ outputs should

be 0. All the flip flops’ outputs (0000 for both counters) should be taken and

ANDED altogether, and then sent to the display.

The above circuit is just an example on how to display the word FULL on

the 7 segment. Let us analyze this more closely; For the F, U, L, L to

display; we need to activate part of the LEDs in the 7 segment as shown

below:

F: a, e, f, g

U: b, c, d, e, f

L: d, e, f

L: d, e, f

NOTE: THIS ABOVE CIRCUIT IS AN EXAMPLE I USED TO EXPLAIN

ABOUT HOW TO DISPLAY “FULL”. THIS CIRCUIT IS ACTUALLY NOT

BEING USED IN OUR CIRCUIT.

U9

A B C D E F G

CK

U1

A B C D E F G

CK

U2

A B C D E F G

CK

U3

A B C D E F G

CK

VCC

20V R4

50Ω

R1

50Ω

R2

50Ω

R3

50ΩJ1

Key = C


21

9.GROUPING ALL THE PARTS TO MAKE THE

FINAL CIRCUIT:

U1

JK

_F

F

JQ

~Q

K

RESET

CLK

SET

U2

JK

_F

F

JQ

~Q

K

RESET

CLK

SET

U3

JK

_F

F

JQ

~Q

K

RESET

CLK

SET

U4

JK

_F

F

JQ

~Q

K

RESET

CLK

SET

V1

5 V

U5

AN

D3

U8

AN

D3

U9

AN

D3

U1

0

AN

D4

U1

1

OR

2

U1

2

OR

3

U7

AN

D4

U1

3

AN

D3

U1

4

AN

D3

U1

5

AN

D3

U1

6

OR

2

U1

7

OR

2

U1

8

OR

2

U1

9

OR

2

J1

Ke

y =

U

J2

Ke

y =

D U2

0A

74

LS

32

N

U2

1

JK

_F

F

JQ

~Q

K

RESET

CLK

SET

U2

2

JK

_F

F

JQ

~Q

K

RESET

CLK

SET

U2

3

JK

_F

F

JQ

~Q

K

RESET

CLK

SET

U2

4

JK

_F

F

JQ

~Q

K

RESET

CLK

SET

U2

5

AN

D3

U2

6

AN

D3

U2

7

AN

D3

U2

8

AN

D4

U2

9

OR

2

U3

0

OR

3

U3

2

AN

D4

U3

3

AN

D3

U3

4

AN

D3

U3

5

AN

D3

U3

6

OR

2

U3

7

OR

2

U3

8

OR

2

U3

9

OR

2

U4

4

AN

D2

U45

AB

CD

EF

G

CK

U46

AB

CD

EF

G

CK

U47

AB

CD

EF

G

CK

U48

AB

CD

EF

G

CK

R1

10Ω

R2

50Ω

R3

50Ω

R4

50Ω

U4

3

AN

D4

U4

2

AN

D4

U4

0

AN

D5

U4

9

AN

D5

U4

1

NO

R2

U5

0

SR

_F

F

SQ

~Q

R

U5

1

DC

D_

7S

EG

_P

ABCD

0345 2 16

U52

AB

CD

EF

G

CK

U5

3

DC

D_

7S

EG

_P

ABCD

0345 2 16

U54

AB

CD

EF

G

CK

R5

50Ω


22

10.EXPLANATION OF THE OTHER ELEMENTS

USED IN THE CIRCUIT:

As we can see from the circuit, a NOR gate and a latch have been included

in the circuit. Here below, we are going to look at their uses:

SR LATCH:

Both the entry and exit of the car park are connected to sensors which

detects the incoming or outgoing of vehicles in and out of the park.

According to our requirements, when a car comes in, the counter is

supposed to count down and vice versa. An S-R latch is also called a set-

reset latch. An input on S sets the latch, making true and false. An

input on R resets the latch; becomes false and becomes true. The

output of the circuit is stable in either state with the inputs removed. We

can remove the input that caused a particular output and the output will be

unchanged. The state, and so the output, will only change when the

complementary input is applied. Such a circuit is said to

be bistable because it has two stable states.

U50

SR_FF

S Q

~QR


23

S R Q

Operation

0 0

Hold (no count)

0 1 0 1 Reset(count up)

1 0 1 0 Set(count down)

1 1 ? ? Unstable(No count)

Table 3-1 S-R Latch Truth Table

CLOCKPULSE:

The output of 10 while counting down or after 9 while counting up

needs to change. This will depend on the clock pulse of the down

circuit as shown in the circuit diagram. This is why we take 1001 (for

the counting up) and 0000(for the counting down) and AND them as

shown in the circuit. Their outputs are then applied to a NOR gate

and then sent to the clock pulse. By doing so, we will be able to

increase or decrease the output of the higher significant number.


24

11.PRACTICAL PART


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Documents

Car park Digital controller