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Principle of Microcomputer 8051 Architecture
1
Principle of Microcomputer (UEE 2301/1071)
Chap 2. MCS-51 Architecture
微算機原理與實驗
宋開泰
Office:EE709 Phone:5731865(校內分機:31865)
Email:[email protected] URL:http://isci.cn.nctu.edu.tw
Principle of Microcomputer 8051 Architecture
2
• MCS-51系列:8-bit 單晶片微電腦
內部記憶體
(Byte)
外部記憶體
(Byte)
Ports
程式 資料 程式 資料 平行 串列
中
斷
計數器
MHz
Pin
No.
8051 4K ROM 128 64K 64K 32 UART 5 2×16bit 2~12 40
8751 4K EPROM 128 64K 64K 32 UART 5 2×16bit 2~12 40
8031 -- 128 64K 64K 32 UART 5 2×16bit 2~12 40
8052AH 8K ROM 256 64K 64K 32 UART 6 3×16bit 2~12 40
8752AH 8K EPROM 256 64K 64K 32 UART 6 3×16bit 2~12 40
8032AH -- 256 64K 64K 32 UART 6 3×16bit 2~12 40
80C51 4K ROM 128 64K 64K 32 UART 5 2×16bit 2~12 40
87C51 4K EPROM 128 64K 64K 32 UART 5 2×16bit 2~12 40
80C31 -- 128 64K 64K 32 UART 5 2×16bit 2~12 40
80C252 8K ROM 256 64K 64K 32 UART 7 3×16bit 2~12 40
87C252 8K EPROM 256 64K 64K 32 UART 7 3×16bit 2~12 40
83C252 -- 256 64K 64K 32 UART 7 3×16bit 2~12 40
8052AH
-BASIC
8K ROM 256 64K 64K 32 UART 6 3×16bit 2~12 40
Principle of Microcomputer 8051 Architecture
3
CC2430 ZigBee Chip
• CC2430
• 體積小 7mm×7mm
• 低耗電量
• 使用電壓範圍大2.0V~3.6V
• 8個ADC input pins
• 內含8051
Principle of Microcomputer 8051 Architecture
4
CC2530
From TI
Principle of Microcomputer 8051 Architecture
6
Aladdin robot in SEMICON TAIWAN 2014
Principle of Microcomputer 8051 Architecture
7
• 依 Program Memory 來分類
1). 不含 Program Memory (ROM, EPROM) 8031, 8032
2). 含 ROM ─ 8051, 8052
3). 含 EPROM ─ 8751, 8752
4). 含 EEPROM ─ 89C51, 89C52
5). 含 Flash memory – 89C51RC, 89C51RD
In System Programmable (ISP)
MCS-51之分類
Principle of Microcomputer 8051 Architecture
8
• 有適合控制用之 8-bit CPU
• 外部記憶體 (Memory) 最大範圍:
1. 程式記憶體 (Program memory) ─ 64K bytes
2. 資料記憶體 (Data memory) ─ 64K bytes
• 內部記憶體:
1. 程式記憶體 ─ 4K(8051), 8K(8052) bytes
2. 資料記憶體 ─ 128(8051), 256(8052) bytes
• 有 32 條可單獨設定之 I/O lines (4 個 ports)
MCS-51的特色
Principle of Microcomputer 8051 Architecture
9
• 有2(8051)/3(8052)個 16-bit Timer/Counters
• 有 5(8051)/6(8052)個 Interrupts,且可規劃 2 個
levels 之 priority
• 有全雙工 (Full-Duplex) 之 Serial I/O Ports
(UART)
• 有 On-chip Clock 及 Oscillator Circuit
• 有 Boolean Processor 之能力 (處理 single-bit 之
logic operation 能力)
MCS-51的特色
Principle of Microcomputer 8051 Architecture
10
• 大多數的指令執行時間:1 s
( 12 MHz Clock )
• 乘除法指令執行時間:4 s
( 12 MHz Clock )
• 有 210 個 Bit-addressable locations
MCS-51的特色
Principle of Microcomputer 8051 Architecture
11
MCS-51接腳圖
40
39
38
37
36
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32
31
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21
1
2
3
4
5
6
7
8
9
10
11
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18
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20
MCS-51
(T2) P1.0
(T2EX) P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RxD / P3.0
TxD / P3.1
INT0 / P3.2
INT1 / P3.3
T0 / P3.4
T1 / P3.5
WR / P3.6
RD / P3.7
XTAL2
XTAL1
Vss
Vcc
P0.0 / AD0
P0.1 / AD1
P0.2 / AD2
P0.3 / AD3
P0.4 / AD4
P0.5 / AD5
P0.6 / AD6
P0.7 / AD7
EA / VDD
ALE / PROG
PSEN
P2.7 / A15
P2.6 / A14
P2.5 / A13
P2.4 / A12
P2.3 / A11
P2.2 / A10
P2.1 / A9
P2.0 / A8
Principle of Microcomputer 8051 Architecture
12
8051 Pin Assignment
Principle of Microcomputer 8051 Architecture
13
MCS-51方塊圖
Interrupt Control
Timer 1
Timer 2
INT0 INT1 P3.2 P3.3
Timer 0
Serial port
Other Registers
128 (8051, 8031)
RAM 256
(8052, 8032)
ROM or
EPROM 8K(8052, 8752) 4K(8051, 8751) 0K(8031, 8032)
Timers
Timer 0, 1 (8051, 8031)
Timer 0,1,2 (8052, 8032)
P1.1 P1.0 P3.5 P3.4
T2EX T2 T1 T0
Serial Port
RxD P3.0
TxD P3.1
I/O Ports
P0 (Address/Data)
P1 P2 (Address)
P3
Bus Control
EA RST ALE PSEN
RD P3.7
WR P3.6
Oscillator
XTAL1 XTAL2
CPU
Principle of Microcomputer 8051 Architecture
14
8051方塊圖
P0: address/data
P2: address(A8~A15)
Principle of Microcomputer 8051 Architecture
15
MCS-51 Architecture
• 8-bit CPU with register A (Accumulator) and B
• Internal Memory:
1. Program memory – 4K (8051), 8K (8052) Bytes
2. Data memory – 128 (8051), 256 (8052) Bytes
• External memory maximum range
– Program memory – 64K Bytes
– Data memory – 64K Bytes
• 32 I/O lines arranged as 4 8-bit ports, P0~P3
• 2 (8051)/3 (8052) 16-bit programmable Timer/Counters
• 5 (8051)/6 (8052) Interrupts, with 2 levels programmable priority
• Full-duplex serial I/O ports (UART)
• On-chip clock and oscillator circuit
• Boolean processor, single-bit logic operations.
Principle of Microcomputer 8051 Architecture
16
MCS-51 Architecture(Continued)
• 16-bit program counter(PC) and data pointer(DPTR)
• 8-bit program status word(PSW)
• 8-bit stack pointer(SP)
• Internal ROM or EPROM (8751) of 0 (8031) to 4K (8051)
• Internal RAM of 128 Bytes:
1. 4 register banks, each containing eight registers
2. 16 Bytes of bit addressable locations, which may be addressed at bit level
3. 80 Bytes of general-purpose data memory
Principle of Microcomputer 8051 Architecture
17
8051 Program Model
Principle of Microcomputer 8051 Architecture
18
8051 Oscillator and Clock
• Instruction time Tinst =
C : number of cycles
For example ADD A, R1 (one-cycle instruction)
16 MHz crystal Tinst = 0.75 µs.
12 MHz crystal Tinst = 1µs.
• 11.0592 MHz crystal
cycle frequency = 921.6 KHz
can be divided by 19200, 9600, 4800, 2400, 1200, 300
(Baud rate of serial communication).
frequency crystal
12C
Principle of Microcomputer 8051 Architecture
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FIGURE 2–5 Relationship between oscillator clock cycles, states, and
the machine cycle
Principle of Microcomputer 8051 Architecture
20
Crystal Oscillator
Principle of Microcomputer 8051 Architecture
21
Internal Memory
• ROM: memory for program codes
• RAM: memory for variable data that can be altered as the program runs.
• The 8051 belongs to a Harvard architecture, which uses the same address, in different memories, for codes and data. Internal circuitry accesses the correct memory based upon the nature of the operation in progress.
• Unlike Van Neumann architecture, which can use a single memory address for either program code or data, but not for both.
Principle of Microcomputer 8051 Architecture
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8031 Memory Space
Principle of Microcomputer 8051 Architecture
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Internal ROM
• The 8051 is organized so that data memory and program memory can be in two entirely different physical memory entities. Each has the same address ranges.
• Internal program codes are contained in an internal ROM, address space 0000H~0FFFH.
Principle of Microcomputer 8051 Architecture
(Continued)
24
• The program counter(PC) is 16-bit wide, which can access program code bytes from 0000H~FFFFH.
• Program addresses higher than 0FFFH will cause the 8051 to automatically fetch code bytes from external program memory.
• Program code can be fetched exclusively from an external memory address 0000H to FFFFH, by connecting the external access pin(EA) to ground.
Principle of Microcomputer 8051 Architecture
25
Internal RAM
128-byte internal RAM is organized into three distinct areas:
1. 32 bytes working registers (00H~1FH)
• Organized as four banks of eight registers each (R0~R7)
• Each register can be addressed by name (when the bank is selected) or by its RAM address.
• Bits RS0 and RS1 in the PSW determine which bank of register is currently in use.
• Bank 0 is selected upon reset.
Principle of Microcomputer 8051 Architecture
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2. A bit-addressable area of 16 bytes (address 20H~2FH)
• 128 addressable bits. An addressable bit can be specified by its bit address of 00H~7FH.
For example: bit address 4FH is also bit 7
of byte address 29H.
3. 80 bytes of general purpose RAM.
Address: 30H~7FH
Principle of Microcomputer 8051 Architecture
27
8051 On-chip Data Memory
Principle of Microcomputer 8051 Architecture
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Special Function Registers (SFRs)
• SFRs have byte addresses in the range
[80H~FFH]. The SFRs are mapped into the
block of 128 bytes next to internal RAM,
which occupy the address[00H~7FH].
• SFRs contain data and control registers. Each
on-chip facility, such as each of the timers, the
serial port, and the interrupt system, has one or
more dedicated SFRs.
Principle of Microcomputer 8051 Architecture
29
Principle of Microcomputer 8051 Architecture
30
8052 Internal RAM
• The 8052 has 256 bytes of internal RAM, the
higher block of 128 bytes is accessible only
through register indirect addressing.
The instruction MOV A, 80H moves the value stored in
the SFR 80H into the accumulator,
The instruction MOV A, @R0, where R0 has been
previously set to 80H, moves the contents of the internal
RAM location 80H into the accumulator.
Principle of Microcomputer 8051 Architecture
31
8052 Memory Space
Principle of Microcomputer 8051 Architecture
32
The Stack and the Stack Pointer
• The 8-bit stack pointer (SP) register is used
by the 8051 to hold an internal RAM
address that is called the “top of the stack.”
• The address held in the SP register is the
location in internal RAM where the last
byte of data was stored by a stack operation.
Principle of Microcomputer 8051 Architecture
(Continued)
• When data are to be placed on the stack, the
SP increments before storing data on the
stack so that the stack grows up as data are
stored.
• As data are retrieved from the stack, the
byte is read from the stack, and the SP
decrements to point to the next available
byte of the stored data.
33
Principle of Microcomputer 8051 Architecture
34
Stack operation
Principle of Microcomputer 8051 Architecture
35
Data Pointer DPTR
• Two registers, total 16-bit, address DPH--83H, DPL--82H
• Used to store a 16-bit address, which is used to access 64K
bytes of external RAM.
Example
MOV A, #04H ;(A)=04H
MOV DPTR, 1993H ;(DPTR)=1993H
MOVX @A+ DPTR, A ;(1993H+04H)=(A)
Principle of Microcomputer 8051 Architecture
36
Processor (Program) Status Word (PSW)
•8-bit register,
address: D0H, also
called Flag register
•Flags are 1-bit
registers provided
to store the result
of certain program
instructions. Other
instructions can
test the condition
of the flags and
make decisions
based upon the
flag states.
Principle of Microcomputer 8051 Architecture
37
CY(PSW. 7)
• Carry flag, C or CY.
• Can be set(=1) or clear(=0) by hardware or software.
• For arithmetic operations: set if there is a carry out of bit 7 during an addition, or set if there is a borrow into bit 7 during subtraction.
– For example
what is the status of the carry bit?
C = 0, clear
• Another example : ANL C, 25H
AND bit 25H with the carry flag and put the result back in carry flag.
MOV R5, # 55H
MOV A, #0AAH
ADD A, R5
0 1 0 1 0 1 0 1
1 0 1 0 1 0 1 0
1 1 1 1 1 1 1 1
Principle of Microcomputer 8051 Architecture
38
Auxiliary Carry Flag(AC)
• When adding binary-coded-decimal(BCD) values, the auxiliary carry
flag (AC) is set if a carry is generated out of bit 3 into bit 4 or if the result
in the lower nibble is in the range 0AH~0FH
• AC is used in Decimal Adjust Accumulator instruction
DA A
to bring results greater than 9 back into range.
For example
AC = 1, ACC = 0AH (This is greater than 910)
if the addition is followed by DA A, the final result in ACC is 10H
(=1010)
MOV R5, # 1
MOV A, #9
ADD A, R5
Principle of Microcomputer 8051 Architecture
39
Register Bank Select Bits (RS0, RS1)
• RS0 and RS1 determine the active register bank.
• They are cleared after a system reset and are changed by
software as needed.
For example
Register bank 3 is enabled, the content of R7(byte address
1FH) is moved to the accumulator.
SETB RS1
SETB RS0
MOV A, R7
Principle of Microcomputer 8051 Architecture
40
Overflow Flag (OV) • OV is set after an addition or subtraction operation if there is an
arithmetic overflow.
• Results greater than +127 or less than –128 will set the OV bit.
For example
CY =1, no overflow OV = 0
MOV R7, # 0FFH
MOV A, # 0FH
ADD A, R7
1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1
1 0 0 0 0 1 1 1 0
- 110
1510
+ 14 =0E
0 F
7 F
8 E
=(-116)
1510
12710
14210 OV is set
Principle of Microcomputer 8051 Architecture
41
Parity Flag(P)
• Even parity is adopted for MCS-51.
• When an instruction is executed, hardware will set(=1) or
clear(=0) parity flag according to the number of “1”s in A
register.
P = 1, when A register contains odd number of “1”s
P = 0, when A register contains even number of “1”s.
Principle of Microcomputer 8051 Architecture
42
PSW Register Summary
Principle of Microcomputer 8051 Architecture
43
Multiplexing Address and Data Bus
Principle of Microcomputer 8051 Architecture
44
Accessing External Code Memory
Principle of Microcomputer 8051 Architecture
45
74LS75 Transparent latch
1. Outputs are controlled by the enable C, as long as the enable is
LOW, output Q holds its last value.
2. When the enable goes HIGH, the output follows the data presented
at input D.
From: Design with
Microprocessors for
Mechanical Engineers,
by A. K. Stiffler
Principle of Microcomputer 8051 Architecture
46
74LS373
Transparent latch
74LS374 Edge-
triggered flip-flop
Data should
be latched on
the trailing
edge of the
enable pulse.
From: Design with
Microprocessors for
Mechanical Engineers,
by A. K. Stiffler
Principle of Microcomputer 8051 Architecture
47
Read Timing for External Code Memory
Principle of Microcomputer 8051 Architecture
48
Interfacing to External RAM
Principle of Microcomputer 8051 Architecture
49
Accessing External Data memory
Principle of Microcomputer 8051 Architecture
50
Accessing Multiple External Memory Chips
Principle of Microcomputer 8051 Architecture
51
74LS138 decoder
From: Microprocessor
Systems Design, A.
Clements
B
Principle of Microcomputer 8051 Architecture
52
FIGURE 2–16 Two circuits for system reset. (a) Manual reset (b) Power-on reset.
Principle of Microcomputer 8051 Architecture
53
I/O ports