CDB42518 Evaluation Board For CS42518/16 · 2016-12-16 · Evaluation Board For CS42518/16 Features Single-Ended Analog Inputs and Outputs Integrated S/PDIF compatible Receiver CS5361

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Cirrus Logic, Inc.http://www.cirrus.com

CDB42518

Evaluation Board For CS42518/16
Features
�Single-Ended Analog Inputs and Outputs� Integrated S/PDIF compatible Receiver�CS5361 converters supply ADCIN1 and

ADCIN2 for CS42518 One Line Modes�CS8406 S/PDIF Digital Audio Transmitter �Header for optional external configuration of

CS42518 and board�Header for external DSP serial audio I/O�3.3 or 5.0 Volt Logic Interface supply�Demonstrates recommended layout and

grounding arrangements�Windows compatible software interface to

configure CS42518 and inter-board connections

DescriptionThe CDB42518 demonstration board is an excellentmeans for evaluating the CS42518/16 family of highly in-tegrated multi-channel CODEC-S/PDIF receivers.Evaluation requires an analog/digital signal source andanalyzer, Windows compatible computer, and powersupplies.

System timing can be provided by an on-board oscillatoror phase-locked to an S/PDIF input. RCA phono jacksare provided for the CS5361 analog inputs and CS42518analog inputs and outputs. Digital data I/O is availablevia RCA phono jacks or optical connectors to/from theCS42518 and CS8406.

The Windows software provides a GUI to make configu-ration of the board easy. The software communicatesthrough the computer’s parallel port, and will configurethe hardware to allow all features of the CS42518 to beevaluated. The evaluation board may also be configuredto accept external timing and data signals for operationin a user application during system development.

ORDERING INFORMATIONCDB42518 Evaluation Board

I

PC Parallel Port

CS42518

S/PDIF Inputs

Analog Inputs

Analog Inputs

S/PDIF Output

S/PDIF Output Analog Outputs

+18V -18V +5V GND

CPLDExt. Control

Mux

AnalogFilter

CS5361(x2)

8-chAnalogOutput

Mute

CS8406

DSP Header

1

s Logic, Inc. 2003 Reserved)

JAN ‘03DS584DB2

CDB42518

TABLE OF CONTENTS1. SYSTEM OVERVIEW ............................................................................................................... 4

1.1 CS42518 ............................................................................................................................ 41.2 CS8406 .............................................................................................................................. 41.3 CS5361 .............................................................................................................................. 41.4 Crystal Oscillator ................................................................................................................ 41.5 Analog Input ....................................................................................................................... 41.6 Analog Outputs .................................................................................................................. 41.7 CPLD ................................................................................................................................. 51.8 DB-25 Computer Parallel Port ........................................................................................... 51.9 External Control Header .................................................................................................... 51.10 DSP Header ..................................................................................................................... 61.11 LED Function Indicator .................................................................................................... 61.12 Power ............................................................................................................................... 61.13 Grounding and Power Supply Decoupling ....................................................................... 61.14 External Control Header Signals ...................................................................................... 71.15 DSP Header Signals ........................................................................................................ 8

2. INITIAL BOARD SETUP ........................................................................................................... 92.1 Power Supplies .................................................................................................................. 92.2 Installing the Software ........................................................................................................ 9

3. CDB425XX.EXE USER'S GUIDE ........................................................................................... 103.1 Main Window ................................................................................................................... 103.2 CS425XX Window ........................................................................................................... 103.3 Preset Scripts ................................................................................................................... 103.4 Quick Start Preset - Analog In to Analog Out .................................................................. 103.5 Quick Start Preset - Analog In to Digital Out .................................................................... 103.6 Quick Start Guide - Digital In to Analog Out .................................................................... 11

4. BLOCK DIAGRAMS ............................................................................................................... 125. SCHEMATICS AND LAYOUT ................................................................................................ 166. BILL OF MATERIALS ............................................................................................................ 327. ADDENDUM ........................................................................................................................... 36

Contacting Cirrus Logic SupportFor all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com/en/contacts/sales

IMPORTANT NOTICE

"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product infor-mation describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the infor-mation contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warrantyof any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information beingrelied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including thosepertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of thisinformation as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrusand by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets orother intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information onlyfor use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copyingfor general distribution, advertising or promotional purposes, or for creating any work for resale.

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Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to usethose components in a standard I2C system.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade-marks or service marks of their respective owners.

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CDB42518

LIST OF FIGURESFigure 1. Instrumentation Amplifier Configuration........................................................................... 5Figure 2. MCLK and SDATA......................................................................................................... 12Figure 3. CX and SAI LRCK/SCLK ............................................................................................... 13Figure 4. Output Channel Mute Select.......................................................................................... 14Figure 5. SPDIF Routing ............................................................................................................... 15Figure 6. CS42518........................................................................................................................ 16Figure 7. Clocks, Data, and DSP Header ..................................................................................... 17Figure 8. SPDIF ............................................................................................................................ 18Figure 9. CS5361 External ADC #1 .............................................................................................. 19Figure 10. CS5361 External ADC #2 ............................................................................................ 20Figure 11. CS42518 Analog Inputs............................................................................................... 21Figure 12. Analog Outputs A1 and B1 .......................................................................................... 22Figure 13. Analog Outputs A2 and B2 .......................................................................................... 23Figure 14. Analog Outputs A3 and B3 .......................................................................................... 24Figure 15. Analog Outputs A4 and B4 .......................................................................................... 25Figure 16. DB-25, Ext Ctrl Header, Reset..................................................................................... 26Figure 17. CPLD ........................................................................................................................... 27Figure 18. Power........................................................................................................................... 28Figure 19. Component Placement and Reference Designators.................................................... 29Figure 20. Top Layer..................................................................................................................... 30Figure 21. Bottom Layer................................................................................................................ 31

LIST OF TABLESTable 1. System Connections ......................................................................................................... 6Table 2. Jumper Settings ................................................................................................................ 7Table 3. CS42518 External Control Header Signals....................................................................... 7Table 4. CS42518 DSP Header Signals ......................................................................................... 8

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CDB42518

1. SYSTEM OVERVIEW The CDB42518 demonstration board is an excellent means for evaluating the CS42518/16 family of highly integrat-ed CODEC-S/PDIF receivers. Analog and digital audio signal interfaces are provided, as well as a DB-25 computerparallel port interface for use with the supplied Windows configuration software.

The CDB42518 schematic set has been partitioned into 13 pages as shown in Figures 6 through 18.

1.1 CS42518A complete description of each member of the CS42518/16 family is included in each respective product data sheet.

1.2 CS8406The CS8406 S/PDIF transmitter on the demonstration board (see Figure 8) allows the performance of the CS42518to be measured digitally. Either the CS42518 CODEC (CX) port or the Serial Audio Interface (SAI) port can be mul-tiplexed to the CS8406. The CS8406 transmitter is configured to operate in slave mode only, and will receive therequired clocks from the CS42518. The data format for the CS8406 is selectable and must match that of its source.The CS8406 must be configured using the supplied software.

1.3 CS5361There are two CS5361 A/D converters on the CS42518 demonstration board (see Figures 9 and 10). These con-verters supply the CS42518 ADCIN signals, and must operate in left-justified, 24-bit mode only. Their serial dataoutputs are used when supporting the CS42518 One Line Mode of operation.

RCA analog connectors supply the inputs to each CS5361 channel through a unity gain, AC-coupled, single-to-differential circuit. Each CS5361 input circuit is biased to 1/2 VA, and a 1VRMS signal will drive the converter to fullscale. The CS5361 converters are set to operate in slave mode and will receive their clocks from the CS42518. TheSCLK and LRCK signals can be provided from either the CS42518 CX or SAI port, and must be selected using theconfiguration software.

1.4 Crystal OscillatorOscillator Y1 (see Figure 7) provides the System Clock (OMCK) for the CS42518. The crystal oscillator on the boardis mounted in pin sockets that allow it to be removed or replaced. The board is shipped with a 24.000 MHz crystaloscillator stuffed at Y1. Please refer to the CS42518/16 data sheet for details on OMCK operation.

The buffer on the output of the oscillator provides for signal level shifting to the proper VLS supply. This buffer canbe removed if the oscillator is powered from the same VLS voltage source as the codec.

1.5 Analog InputRCA phono connectors supply the CS42518 analog inputs through unity gain, AC-coupled single-to-differential cir-cuits (see Figure 11). Each input circuit is biased to match the 2.7VDC VQ, and a 1VRMS differential signal will drivethe CS42518 converter to full scale.

1.6 Analog OutputsEach CS42518 analog output is routed through a differential to single-ended, unity-gain low pass filter, which is AC-coupled to an RCA phono jack (see Figures 12 through 15). The analog output filter on the CDB42518 has beendesigned to add flexibility when evaluating the CS42518 DAC outputs. The output filter was designed in a two stageformat, with the first stage being an optional instrumentation amplifier, and the second stage a 2-pole butterworthlow pass filter.

The 2-pole low pass filter provides an example of an inexpensive circuit with good distortion and dynamic range per-formance. It is designed to have the in-band impedance matched between the positive and negative legs. It alsoprovides a balanced to single-ended conversion for standard un-balanced outputs. Evaluate this circuit by placingthe FILT jumpers (three per output channel) to position 1 (selectable by J9, J10 & J11 for OUTA1, etc.).

4

CDB42518

The instrumentation amplifier is optionally inserted before the LPF by changing the FILT jumpers to position 2. Theinstrumentation amplifier incorporates a 5x gain (+14dB) which effectively lowers the noise contribution of the fol-lowing 2-pole LPF. This improves the overall dynamic range of the system. The gain of this stage is determined fromthe following equation:

The resistor designated by R2 (see Figure 1) can be adjusted to change the gain of the instrumentation amp. Thefeedback resistors on the two sides of the instrumentation amp ‘R’ must be equal.

A resistor divider pad (R66 and R84 for OUTA1) has been placed after the low pass filter to bring the circuit back tounity gain (selectable with jumper J11 for OUTA1).

The attenuation provided by the output mute transistor (Q2 for OUTA1) is determined by the resistor-divider formedbetween the collector-emitter on-resistance and the output resistor of the LPF (R66 for OUTA1). The greater theoutput resistor, the greater the attenuation will be for a given transistor. The trade off is that a high output impedanceis not usually desirable, and may affect the voltage transfer to the next stage based upon its input impedance.

The same resistor that affects the transistor mute level also affects the HPF formed with the output DC-block capac-itor (C63 for OUTA1). For LPF configuration 2, the values for the DC-block capacitor and output resistor pad (R66and R84 for OUTA1) were chosen to give uniform distortion performance across the audio bandwidth, particularlyat low frequency. The HPF formed by this R-C pair must be such that the voltage across the aluminum electrolyticDC-block capacitor must be a minimum at 20Hz. This keeps the distortion due to the electrolytic's dielectric absorp-tion properties to a minimum. For a design utilizing only LPF configuration 1, there is no post-LPF resistor-dividerpad, and a much smaller value capacitor can be used.

1.7 CPLDThe CPLD controls the on-board signal routing and configuration (see Figure 17). The CPLD interfaces with thecomputer software through the DB-25 parallel port header, or can communicate with an external processor via theExternal Control header.

1.8 DB-25 Computer Parallel Port On-board clock and data routing and configuration logic, as well as the CS42518 part are configured using a com-puter with the supplied Windows-based software. The software communicates via the DB-25 parallel port interface(see Figure 16) to a local CPLD that can configure all parts on the board.

1.9 External Control HeaderA 26-pin dual-row header allows access to the control signals needed to configure the CS42518. The external con-troller has access to the CS42518 I2C/SPI signals, master mute and reset, and the CS42518 interrupt signal is avail-able (see Figure 16). All control header signals are buffered, and are referenced to VLC levels. See Table 3 for acomplete description of External Control Header signals.

Gain 1 2 R( )R2

------------+=

IN+

IN-OUT-

OUT+

R

R

R2

Figure 1. Instrumentation Amplifier Configuration

5

CDB42518

1.10 DSP HeaderA 32-pin dual-row header provides access to the serial audio signals required to interface with a DSP (see Figure 7).Either the CS42518 or the DSP header can be the master of the MCLK signal. The CS42518 can supply the DSPheader with its recovered master clock (RMCK), or pass the local oscillator-sourced OMCK. An optional configura-tion supported is for the DSP header to source DSP_MCLK to the OMCK input, and the RMCK of the CS42518 isnot used.

The CS42518 SAI and CX ports are individually selectable to be master or slave, and should source/receive theirclocks to/from the DSP as required. All serial port timings must be synchronous to the to RMCK or the clock sourcesuppling OMCK. See the data sheet for a complete description of serial port modes of operation. All DSP headersignals are buffered, and are referenced to VLS levels. DSP interface power VLS and ground are supplied to theheader. See Table 4 for a complete description of DSP Header signals.

1.11 LED Function IndicatorD1 (see Figure 16) indicates that a master reset condition has occurred on the board. D4 (see Figure 17) is sourcedfrom the CPLD and is currently unsupported.

1.12 PowerPower can easily be supplied to the evaluation board through three binding posts, all referenced to the single blackbinding post ground connector (see Figure 18).

Supply +18.0 VDC to the green binding post to provide the positive analog rail. Supply -18.0 VDC to the yellow bind-ing post to provide the negative analog rail. +18V and -18V supply power to the op-amps and can be +/-12 to +/-18volts (must be +/-18 V when filter 2 is selected).

Supply +5.0VDC to the red binding post. This directly supplies the digital +5V, is regulated down to provide the digital+3.3V, and is filtered to supply VLC, VA and VARX.

VLS and VD must be individually set with jumpers to either +3.3V or +5V.

1.13 Grounding and Power Supply DecouplingThe CS42518 requires careful attention to power supply and grounding arrangements to optimize performance.Figures 15 and 16 detail the routing and component placement for both top and bottom layers of the demonstrationboard. Power supply decoupling capacitors are located as close to the CS42518 as possible. Extensive use ofground plane fill in the demonstration board yields large reductions in radiated noise.

CONNECTOR INPUT/OUTPUT SIGNAL PRESENT

+5V Input + 5VDC power

-18V Input -18 to -12VDC negative supply for the op-amps

+18V Input +12 to +18VDC positive supply for the op-amps

GND Input Ground connection from power supply

SPDIF RX - J1 Input Digital audio interface input via coax

SPDIF RX - OPT1 Input Digital audio interface input via optical

SPDIF TX - J2 Output CS8406 digital audio interface output via coax

SPDIF TX - OPT2 Output CS8406 digital audio interface output via optical

CS42518 TXP - OPT3 Output CS42518 digital audio interface output via optical

PC Port - J22 Input/Output Parallel connection to computer for SPI / I2C control port signals

EXTERNAL CONTROL HEADER - J17

Input/Output I/O for SPI / I2C control port signals - see signal descriptions below

DSP HEADER - J36 Input/Output I/O for DSP serial port signals - see signal descriptions below

ANALOG IN LFT/RT Input RCA phono jacks for analog input signal to CS42518 internal ADCs

EXT A/D #1 LEFT/RIGHT Input RCA phono jacks for analog input signal to CS5361 ADC #1

EXT A/D #2 LEFT/RIGHT Input RCA phono jacks for analog input signal to CS5361 ADC #2

OUT_A1 to OUT_B4 Output RCA phono jacks for channels A1 to B4 analog outputs

Table 1. System Connections

6

CDB42518

1.14 External Control Header Signals

JUMPER / SWITCH PURPOSE POSITION FUNCTION SELECTED

J37 Selects source of voltage for the VLS supplies

+3.3V*+5V

Voltage source is +3.3V regulatorVoltage source is +5V binding post

J38 Selects source of voltage for the VD supply

+3.3V*+5V

Voltage source is +3.3V regulatorVoltage source is +5V binding post

S2 Stand-Alone Mode Select SAM0SAM1

Stand-Alone Modes are for debug use and are presently unsupported

J9,J10,J11J13,J15,J16J18,J19,J20J23,J25,J26J28,J29,J30J32,J34,J35J39,J40,J41J43,J45,J46

DAC Output Filter select - FILT *1

2

Selects standard 2-pole LPF

Selects instrumentation-amp/LPF/pad

*Default Factory Settings

Table 2. Jumper Settings

HeaderPin #

Signal Description Source Schematic Signal Name Buffer BufferVoltage

1 External Control Present Signal CTRL EXT_CONTROL_PRESENT- - -

2 Ground CDB GND - -

3 Address Bit 0 (I2C) / CS- (SPI) CTRL AD0/CS 74VHC125 VLC


5 Address Bit 1 (I2C) / CDIN (SPI) CTRL AD1/CDIN 74VHC125 VLC


7 SDA (I2C) / CDOUT (SPI) CTRL or CS42518 SDA/CDOUT MOSFET VLC


9 Serial Control Port Clock CTRL SCL/CCLK 74VHC125 VLC


11 Master MUTE to all Outputs CTRL EXT_MUTE 74VHC125 VLC


13 Master RESET CTRL EXT_RESET Diode -


15 CS42518 Interrupt (Programmable) CS42518 EXT_HDR_INT 74VHC125 VLC


17 Enable external I2C interface CTRL EXT_EN_SCL 74VHC125 VLS


19 Enable external I2C interface CTRL EXT_EN_SDA 74VHC125 VLS


Table 3. CS42518 External Control Header Signals

7

CDB42518

1.15 DSP Header Signals

HeaderPin #

Signal Description Source SchematicSignal Name

Buffer BufferVoltage

1 Master Clock CS42518 or DSP DSP_MCLK 74VHC125 VLS


3 CODEC port LRCK CS42518 or DSP DSP_CX_LRCK 74VHC125 VLS


5 CODEC port SCLK CS42518 or DSP DSP_CX_SCLK 74VHC125 VLS


7 CODEC port SDATA Input 1 DSP DSP_SDAT1 74VHC125 VLS








15 no connect - - - -


17 SAI port LRCK CS42518 or DSP DSP_SAI_LRCK 74VHC125 VLS


19 SAI port SCLK CS42518 or DSP DSP_SAI_SCLK 74VHC125 VLS


21 no connect - - - -


23 CODEC port SDATA Output CS42518 DSP_CX_SDOUT 74VHC125 VLS


25 SAI Port SDATA Output CS42518 DSP_SAI_SDOUT 74VHC125 VLS


27 MCLK Direction Control DSP MCLK_TO_DSP- - -


29 Serial Port Interface Power CDB VLS - -


31 Serial Port Interface Power CDB VLS - -


Table 4. CS42518 DSP Header Signals

8

CDB42518

2. INITIAL BOARD SETUP

2.1 Power Supplies1) Verify that all power supplies are off before making connections.

2) Connect a +5.0 VDC power supply to the +5V (J47) red binding post. Select VLS and VD operating voltage byplacing a jumper on J37 and J38 to select either +5V or +3.3V.

3) Connect a +12.0 to +18.0 VDC power supply to the +18V (J49) green binding post. If using the FILT positionnumber 2 for the output filter stage, then supply +18.0V only.

4) Connect a -12.0 to -18.0 VDC power supply to the -18V (J50) yellow binding post. If using the FILT positionnumber 2 for the output filter stage, then supply -18.0V only.

5) Connect the common ground of the power supplies to the GND (J48) binding post.

6) Attach parallel port cable between board and computer.

7) Attach all required analog and digital cables to the board jacks and connectors.

8) If using the DSP Header connection, attach the required user supplied flat ribbon cable to the header with thepower supplies turned off.

9) If using the External Control Header connection, attach the required user supplied flat ribbon cable to the headerwith the power supplies turned off. Note that external controller must ground the EXT_CONTROL_PRESENT-signal to gain control of the I2C/SPI signals. This can be done easily by connecting External Control Header pins1 and 2 together.

10) With all cables and connections in place, turn on the power supplies to the board. Turn on supplies in this order:+5 V, +18 V, -18 V.

11) Press and release the RESET switch S1. The LED, D1, will illuminate as long as S1 is depressed indicating areset condition. Once S1 is released, the LED should turn off. If it remains on, an error has occurred. At thispoint, power off the power supplies and re-check all connections. Apply power to the board and press andrelease S1. Once the LED has turned off, the board should now be ready for setup and use.

2.2 Installing the Software1) Create a directory called CDB42518 anywhere on your system.

2) Copy CDB425XX.EXE from the included CD into this directory.

3) Copy the .LVS preset script files from the CD into this directory.

4) Run port95nt.exe from the CD. This will install a utility that will allow the CDB software to access the parallelport. After running the program the system will need to be restarted.

5) If desired, create a shortcut to CDB425XX.EXE on your desktop. You should now be able to runCDB425XX.EXE. Double-click on CDB425XX.EXE or its shortcut.

6) Select the LPT port you are using to connect to the CDB42518.

7) Shut down the application, reset the board, and then restart the application.

9

CDB42518

3. CDB425XX.EXE USER'S GUIDE

3.1 Main WindowThe main window of the CDB42518 control application allows the user to configure the CDB42518 inter-board rout-ing of clocks and data, as well as setup the CS5361 and CS8406 parts. To make changes to the CS5361, CS8406,or inter-board routing, the “Configure Board” radio button must be selected.

The RESET CS425xx button will reset only the part. The MASTER RESET button will reset the CS42518, as wellas reset the board into its default state.

3.2 CS425XX WindowTo configure the CS42518, the “Configure CS425xx” radio button must be selected, then press the “CS425XX” but-ton. This will bring up the complete CS42518 configuration window.

3.3 Preset ScriptsTo make configuring the board and part easier, preset scripts can be saved and recalled. A preset script is a “snap-shot” of all GUI board and component settings. This can done using the File pulldown menu and choosing Load orSave. Scripts are saved with the default .LVS extension, and when loaded, will create a .LOG file. There are severalpreset scripts included with the software. The following sections represent three common setup modes with scriptsfor quick evaluation of the board.

3.4 Quick Start Preset - Analog In to Analog OutTo measure analog in to analog out performance, you will need the following:

• CS42518 Demonstration Board

• +18 VDC, -18 VDC, and +5 VDC power supplies

• Analog signal source and analyzer

• Windows compatible computer with parallel port cable and CDB425xx software

Step 1 - Follow Initial Board Setup procedure as described above

Step 2 - Select Output Filter Jumpers

Set all CDB42518 analog output filter jumpers to the FILT2 settings.

Step 3 - Connect to Windows Software

Connect the computer to the board and launch the CDB425xx software.

Step 4 - Connect Signal Source

Connect the analog output from the analyzer to the Left Analog Input J7. Connect J12 analog OUTA1 RCA to theinput of the analyzer. Set the analyzer output to 1.0 VRMS, 1 kHz. Set the analyzer input to measure signal leveland apply a 22-22 kHz filter.

Step 5 - Configure the Board

Using the Windows software, load the preset script “Single Speed Analog In To Analog Out.LVS”. This preset willconfigure the CS42518 to use OMCK as the master clock, CX and SAI ports will be masters, and the CX_SDOUT(ADC) data will source all CX_SDIN (DAC) inputs. The left/right analog inputs will appear at all odd/even analog out-puts. The single speed sample rate will be 46.875kHz based upon the 24.000MHz OMCK. You may load the similardouble speed or quad speed presets to investigate higher sample rates.

Step 6 - Measure Audio

You should now have audio appearing at the Analog A1 output.

3.5 Quick Start Preset - Analog In to Digital OutTo measure the analog to digital converter performance, you will need the following:



10

CDB42518


• Digital signal source and analyzer






Connect the analog output from the analyzer to the Left Analog Input J7. Connect the CS8406 digital output (coaxJ2 or optical OPT2) to the input of the analyzer. Set the analyzer output to 1.0 VRMS, 1 kHz. Set the analyzer inputto measure digital signal level and apply a 22-22 kHz filter.


Using the Windows software, load the preset script “Single Speed Analog In To Digital Out.LVS”. This preset willconfigure the CS42518 to use OMCK as the master clock, CX and SAI ports will be masters, and the CX (ADC)clocks data will source the CS8406 inputs. The CS8406 will output the ADC digital data to both the optical and RCAjacks. The single speed sample rate will be 46.875kHz based upon the 24.000MHz OMCK. You may load the similardouble speed or quad speed presets to investigate higher sample rates.


You should now have digital audio appearing at the CX_SDOUT port and the CS8406 digital output.

3.6 Quick Start Guide - Digital In to Analog OutTo measure digital to analog performance, you will need the following:




• Digital signal source and analyzer



Step 2 - Select Output Filter Jumpers

Set all CDB42518 analog output filter jumpers to the FILT2 settings.




Connect the S/PDIF digital output from the analyzer to the optical input connector OPT1. Connect the analog OUTA1RCA phono jack J12 to the input of the analyzer. Set the analyzer output to 0 dBFS, 1 kHz, sample rate at 48 kHz.Set the analyzer input to measure signal level and apply a 22-22 kHz filter.


Using the Windows software, load the preset script “Single Speed Optical In to Analog Out.LVS”. This preset willconfigure the CS42518 to use the recovered PLL clock as the master clock, the SAI port will be master, the CX portwill be slaved to the SAI port, the SAI_SDOUT will source all CX_SDIN inputs. The test source left/right data willappear at all odd/even analog outputs. You may load the similar double speed or quad speed presets to investigatehigher sample rates, but you must be sure to supply an appropriate speed SPDIF signal.


You should now have audio appearing at the Analog A1 output.

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CDB42518

4. BLOCK DIAGRAMS

MCLK_TO_DSPDSP_MCLK

OMCK

RMCK

SAI_SDOUT

CX_SDOUT

CX_SDIN1

CX_SDIN2

CX_SDIN3

CX_SDIN4

CX_TO_CXSDIN

SAI_TO_CXSDIN

DSP_TO_CXSDIN

DSP_SDAT4

DSP_SDAT3

DSP_SDAT2

DSP_SDAT1

DSP_CX_SDOUT

8406_SDINCX_DATA_TO_8406

DSP_SAI_SDOUT

8406_SDINSAI_DATA_TO_8406

5361_MCLK

DSP_MCLKMCLK_TO_DSP

8406_MCLKY1

24.000 MHz

Figure 2. MCLK and SDATA

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CDB42518

Figure 3. CX and SAI LRCK/SCLK

DS

P_S

AI_

MA

STE

R

CX

LR

CK

SA

I SC

LK

SA

I LR

CK

CX_TO_SAI

SAI_TO_CX

DS

P_C

X_M

AS

TER

DS

P_L

RC

K

DS

P_S

CLK

DS

P

DS

P

8406

8406

5361

5361

DS

P

DS

P

8406

8406

5361

5361

SLC

T_S

AI_

5361

SA

I_TO

_840

6D

SP

_SA

I_S

LAV

E

SLC

T_C

X_5

361

CX

_TO

_840

6D

SP

_CX

_SLA

VE

CX

SC

LK

13

CDB42518

Figure 4. Output Channel Mute Select

RX

P/G

PO

6

EN

_MU

TE6

MU

TEC

RX

P_G

PO

7

EN

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and

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and

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or

EX

T_M

UTE

and

GP

O6

14

CDB42518

A0

A1A

B0

B1B

C0

C1C

4053C

CE

A0

A1A

B0

B1B

C0

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4053B

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A0

A1A

B0

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Opto-electronicCoupler

RCA Jack

RXP/GPO5

RXO

RXP/GPO1

RXP/GPO2

RXP/GPO3

RXP/GPO4

N/C

RXP/GPO6

RXP/GPO7

ENABLE_4053C

ENABLE_4053B

ENABLE_4053A

Figure 5. SPDIF Routing

15

CDB42518

5. SCHEMATICS AND LAYOUT

Fig

ure

6.

CS

4251

8

16

CDB42518

Fig

ure

7.

Clo

cks,

Dat

a, a

nd

DS

P H

ead

er

17

CDB42518

Fig

ure

8.

SP

DIF

18

CDB42518

Figure 9. CS5361 External ADC #1

19

CDB42518

Figure 10. CS5361 External ADC #2

20

CDB42518

Figure 11. CS42518 Analog Inputs

21

CDB42518

Fig

ure

12.

An

alo

g O

utp

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A1

and

B1

22

CDB42518

Fig

ure

13.

An

alo

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A2

and

B2

23

CDB42518

Fig

ure

14.

An

alo

g O

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A3

and

B3

24

CDB42518

Fig

ure

15.

An

alo

g O

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A4

and

B4

25

CDB42518

Fig

ure

16.

DB

-25,

Ext

Ctr

l Hea

der

, Res

et

26

CDB42518

Fig

ure

17.

CP

LD

27

CDB42518

Fig

ure

18.

Po

wer

28

CDB42518

Fig

ure

19.

Co

mp

on

ent

Pla

cem

ent

and

Ref

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ce D

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nat

ors

29

CDB42518

Fig

ure

20.

To

p L

ayer

30

CDB42518

Fig

ure

21.

Bo

tto

m L

ayer

31

CDB42518

6. BILL OF MATERIALSC

IRR

US

LO

GIC

CD

B42

528B

.sch

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128 C

139 C

146 C

147 C

149 C

168 C

174

C0603C

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133 C

143 C

154 C

158 C

171 C

177 C

178

C0805C

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21 C

22 C

23 C

24 C

25 C

27 C

35 C

36 C

42

C43 C

44 C

45 C

46 C

47 C

48 C

49 C

50 C

58 C

74

C76 C

78 C

80 C

84 C

86 C

100 C

101 C

102 C

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3 C

4 C

20 C

32 C

37 C

40 C

61 C

62 C

69 C

82

C87 C

92 C

93 C

94 C

95 C

96 C

104 C

109 C

110

C113 C

114 C

117 C

120 C

124 C

127 C

134 C

137

C138 C

144 C

145 C

150 C

159 C

160 C

161 C

162

C167 C

173 C

175 C

176 C

181 C

187 C

192 C

195

C196 C

197 C

203 C

207 C

208 C

209 C

210 C

211

C212 C

213 C

214 C

217 C

218 C

219 C

224 C

228

C231 C

233 C

234 C

235 C

236 C

248 C

251 C

252

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119 C

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185 C

198 C

223 C

239

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98 C

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206 C

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246

C0805C

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172 C

179 C

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99 C

118 C

157 C

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222 C

247

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32

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225 C

240

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107 C

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130 C

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165 C

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C193 C

194 C

215 C

216 C

229 C

230 C

249 C

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170 R

192 R

211 R

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93 R

116 R

142 R

168 R

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209 R

226

CR

CW

08051651F

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75 R

87 R

120 R

135 R

167 R

183 R

212 R

220

CR

CW

08051871F

DA

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RE

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1.8

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9 R

10 R

11 R

12 R

13

CR

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08051003F

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179 R

180 R

196 R

198

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08051000F

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16

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42 R

44 R

45 R

50 R

85 R

98 R

104

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160 R

163 R

201 R

231 R

235

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155 R

158

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164 R

191 R

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156 R

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204 R

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89 R

106 R

110 R

124 R

137 R

174 R

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222

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08052941F

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146 R

147 R

239

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CW

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99 R

130 R

149 R

178 R

197 R

218 R

233

CR

CW

08052800F

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5 R

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17 R

34 R

81

CR

CW

08053321F

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16

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71 R

91 R

92 R

114 R

115 R

140 R

141 R

165

R166 R

187 R

188 R

207 R

208 R

224 R

225

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301O

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30 R

31 R

47 R

52 R

54 R

69

CR

CW

06033320F

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159

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86 R

109 R

131 R

154 R

182 R

203 R

219 R

238

CR

CW

08054420F

DA

LE

RE

S,

442 O

HM

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0805,

1/1

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. 100ppm

18

R61 R

97 R

101 R

102 R

112 R

113 R

126 R

127

R148 R

161 R

175 R

176 R

193 R

194 R

195 R

205

R232 R

240

CR

CW

08054752F

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8R

73 R

94 R

117 R

143 R

169 R

190 R

210 R

227

CR

CW

08055491F

DA

LE

RE

S,

5.4

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805,

1/1

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, 1%

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8R

76 R

90 R

122 R

138 R

171 R

186 R

213 R

223

CR

CW

08056191F

DA

LE

RE

S,

6.1

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, 0

805,

1/1

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, 1%

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18

R23 R

24 R

26 R

27 R

28 R

29 R

36 R

37 R

38 R

43

R46 R

48 R

49 R

53 R

64 R

65 R

67 R

68

CR

CW

06036340F

DA

LE

RE

S,

634 O

HM

S,

0603,

1/1

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34

CDB42518

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, 0805,

1/1

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. 100ppm

2R

22 R

25

CR

CW

0805822J

DA

LE

RE

S,

8.2

K,

0805,

1/1

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, 5%

, 200ppm

24

R77 R

82 R

83 R

88 R

103 R

105 R

123 R

128 R

129

R136 R

151 R

152 R

173 R

177 R

181 R

184 R

200

R202 R

214 R

216 R

217 R

221 R

236 R

237

CR

CW

08058870F

DA

LE

RE

S,

887 O

HM

S,

0805,

1/1

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, 1%

. 100ppm

13

R1 R

18 R

19 R

20 R

21 R

55 R

56 R

57 R

58 R

59

R60 R

62 R

63

CR

CW

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DA

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13 J

15 J

16 J

18 J

19 J

20 J

23 J

25 J

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29 J

30 J

32 J

34 J

35 J

37 J

38 J

39 J

40 J

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CX

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X_S

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3 C

X_S

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4

CX

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DO

UT

IN

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OM

CK

RM

CK

RS

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1 T

P2 T

P3

TP

4 T

P5 T

P6 T

P7 T

P8 T

P9 T

P10 T

P11

35

CDB42518

7. ADDENDUMThere are three hardware modifications to the circuit board as follows:

1) U16 pin 10 and U16 pin 13 are unterminated in the schematic set. They should have been connected to ground.A top side modification was performed on the board by adding a wire from U16 pin 10 to U16 pin 13, then to theground pad at C94.

2) U17 pin 11 is grounded in the schematic set. It should have been left unterminated. A top side modification wasperformed by lifting U17 pin 11.

3) The MCLK_TO_DSP- signal trace between U29 pin 1 and U47 pin 1 got merged to the ground fill beneath thecrystal oscillator Y1. A top side modification was performed on the board by cutting the trace to disconnect itfrom the ground fill. A bottom side modification was performed on the board by adding a wire to reconnect thetrace.

36

• Notes •

Documents

CDB42518 Evaluation Board For CS42518/16 · 2016-12-16 · Evaluation Board For CS42518/16 Features Single-Ended Analog Inputs and Outputs Integrated S/PDIF compatible Receiver CS5361