1 800-series PeriPherals

PreliminarY Data 6DP18oC cDP1863c

CMOS 8-Bit ProgrammableFEstrI

CLK 2

CLK I

STR

DIIDL2vss

voD

OUT

DI5DI4Dt3

92CS-31696

TERMINAL ASSIGNMENT

Frequency Generator

Features:] Directty interfaces with CDP1g)j-series

microprocessorst 256 possible programmable frequenctest Two clock input predividers (+ 4 and + 8)

a Gated square-wave outqutr Sing/e 4 to 10.5 V suPPlY

The RCA-CDP1863 and CDP1863C CMOS integrated crr-

cuits are programmable {requency generators designed tooroduce 256 possiUte frequencies from a single{requencyinput clock. ihey witt interface directly with the CDP1800-series microprocessor as shown in the system diagram (see

Fig. 1).

The CDP1863 and CDP1863C consist of a programmable

uo-counter and an 8-bit latch (see Fig 2) An input clock rs

predivided by a fixed internal counter chain in addition toih" ptogr"rnrn"ble counter. The final stage of the device

divides ihe output ot the up-counter by two to provide a

square-wave output. The input clock mqy be applied toeiiher of two inputs; CLKI provides a divide-by{our predi-

vide, and CLK2 a divide-by-eight. The unused i nput m ust be

tied to Voo to avoid interference with the true clock After the

programmable up-counter has reached its maximum count'ihe next predivided clock pulse will cause it to go to zero'nt tnit ti*e, the output {lip{lop toggles and the load flip-flop is turned on. The output of the load flip-flop is fed into

the NOR gates which allow the divide rate stored in the 8-bitlatch to p-reset the up-counter. Before the next predivided

clock puise clocks this up-counter, the load flip-flop is reset

and the NOR gates are turned oJf The counter tnen re-

sumes its up-count The data at the eight data inputs ls

latched into the device by the high-to-low transition of

CLK1. when STR(STROBE) is high, or by the high{o-lowtransition of STR, when CLKl is high'

When using CLK2, CLKl must be tied to Voo to permrt tne

STR input"to generate the inlernal latch clock The 8-bitdata in ihe latch determines the divide rate of the program-

rnable uo-counter in the device This rate may range lromdivide-by-one to divide-bY-256.

A low level on the F-ESE-T input resets the up-counter'predividers, and f lip{lops, and forces an initial state into the

b-uit aut" latch. This initial state provides a f ixed divide rate

ior the device prior to running the system A high level on

the FIKET input enables the up-counter, predividers, and

f lip{lops and allows programming a new divide rate into the

devrce.

The CDP1863 and CDP1863C are functionally identical

They differ in that the CDPl863 has an operating voltage

range ol 4 to 1 0.5 volts and the C DP1 863C h as an operatr ng

uLli"g" ttng" of 4 to 6.5 volts. Both are supplied in .l6-lead

herm-etic dual-in-line ceramic packages (D suff ix) and in16-lead dual-in-line plastic packages (E suffix)'

Fig.1 - Typical CDPl8}O-series microptocessor syslem using the CDP1863 and CDP1863t-

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1 800-Serles Peripherals

OPERATf NG CONDITTONS at Ta: 2So C untess Otherwise SDecifiedFor maximum reliability, nominal operating conditions should be selected so that operation is atways withinrhe lollowing nnges

CHARACTERISTICLIMITS

UNITScDP1863 cDPl863CMIN. MAX. MIN. MAX.

ruPPly-vollage Hange (At lA : Full

Temperature 10.5 6.5

Vss Voo Vss Voo

5 gs

Fig.2 - Block diagram tor the CDp186g and CDplB6gC

SIGNAL DESCRIPTIONS

:1K1, CLK2-9ut clock which is divided-down by the device to provider- output frequency. The divide rate of the device is com_:,:sed of a fixed predivide, the programmable divider, ano a: .'de-by-two outpul flip-flop which provides a seuare_-ave output. CLKl is pre-divided by four and CLK2 is pre_: .'ded by eight. The unused CLOCK input must be tied to, 16 to avoid interference with the true CLOCK signal. CLKl-ay also be used to tatch the eight data inputsl

ouTSquare-wave output which is the resultof thedivided_downinput CLOCK. The OUTpUT toggles after the program-mable up-counter reaches its maximurn vaiue and goes tozero. OUT is held low when OE is low.OEA frigh on thilinput allows OUT to toggte freely. A low onOE holds OUT low.

8- BIT LATCH

NOR GATES

PROG RAM MA8 L €UP- COUNTER

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18O0-Serles PeriPherals

"to"* r7

RESET

STR

I N TERNA L

LATCH CLK

OATAINPUTS

Fig.3 - General CLOCK 1 timing diagram

,ror*,7=T--

aroa* a -

STR

I NTERNALLATCH CLK

O ATAI N PUTS

92CM-31677

Fig. 4 - General CLOCK 2 timing cliagram

cLocK t(rPB) Z f-]t

FESET ieCEIRt

STR {N2)

INTERNALLATCH CLK

DATA INPUTS{ 8US)

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