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CEG3420 L1 Intro.1 Copyright (C) 1998 UCB CEG3420 Computer Design Lecture 1 Philip Leong

CEG3420 Computer Design  Lecture 1

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CEG3420 Computer Design  Lecture 1. Philip Leong. Overview. Course Style, Philosophy and Structure Intro to Computer Architecture. Course Administration. Instructor:Philip Leong(phwl) TA: Hiu Yung Wong(hywong2) Norris Leong(mpleong) Tuts:W5 (MMW703) - PowerPoint PPT Presentation

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Page 1: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.1 Copyright (C) 1998 UCB

CEG3420 Computer Design Lecture 1

Philip Leong

Page 2: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.2 Copyright (C) 1998 UCB

Overview

° Course Style, Philosophy and Structure

° Intro to Computer Architecture

Page 3: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.3 Copyright (C) 1998 UCB

Course Administration

° Instructor: Philip Leong (phwl)

° TA:• Hiu Yung Wong (hywong2)

• Norris Leong (mpleong)

° Tuts: W5 (MMW703)

° WWW: http://www.cse.cuhk.edu.hk/~phwl/ceg3420/ceg3420.html

° Text: Computer Organization and Design: The Hardware/Software Interface, Second Edition, Patterson and Hennessy

• Q: Need 2nd Edition? yes! >> 50% text changed, all exercises changed all examples modernized, new sections, ...

Page 4: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.4 Copyright (C) 1998 UCB

Lecture notes

° Available on CEG3420 Page

° Courtesy of University of California at Berkeley’s CS152 Course (http://oheo.eecs.berkeley.edu:80/cs152/)

Page 5: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.5 Copyright (C) 1998 UCB

Objectives

° This is a course in Computer Design and at the end of the course, students should understand

how modern computer systems work

how to design a computer & how design decisions affect cost and performance.

how to measure performance

Page 6: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.6 Copyright (C) 1998 UCB

Tutorials

° These will be posted on the CEG3420 WWW site each week.° Tutorial solutions must be handed to the tutor in the tutorial

session of the week following the tutorial unless otherwise specified

Page 7: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.7 Copyright (C) 1998 UCB

Grading

° Grade breakdown• Final exam: 50% (combined)

• Midterm : 25%

• Assignments : 20%

• Tutorials: 5%

° Anything late: -20% per day

Page 8: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.8 Copyright (C) 1998 UCB

Cheating

° What is cheating?• Studying together in groups is encouraged

• Work must be your own

• Common examples of cheating: running out of time on a assignment and then pick up output, take homework from box and copy, person asks to borrow solution “just to take a look”, copying an exam question, …

° Any cases, (however small or large) will be forwarded to CS&E disciplinary committee

Page 9: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.9 Copyright (C) 1998 UCB

Project

° Two projects will be completed in this course• Software simulator for a subset of the MIPS instruction set

- after completing this project you should really understand how the instruction set works logically

• Design of a RISC microprocessor

- after completing this project you should understand how to implement it in hardware

- you can be creative and develop as simple/complex processor as you like

° Done in groups of two

Page 10: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.10 Copyright (C) 1998 UCB

Things We Hope You Will Learn from CEG3420

° Keep it simple and make it work• Fully test everything individually and then together

• Retest everything whenever you make any changes

• Last minute changes are big “no-nos”

° Planning is very important:• Promise what you can deliver; deliver more than you promise

• Murphy’s Law: things DO break at the last minute

- Don’t make your plan based on the best case scenarios

- Freeze you design and don’t make last minute changes

° Never give up! It is not over until you give up.

Page 11: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.11 Copyright (C) 1998 UCB

Assumed knowledge

° Basic machine structure• processor, memory, I/O

° Read and write basic C programs

° Read and write in an assembly language• not necessarily MIPs which will be covered in the course

° Logic design• logical equations, schematic diagrams, FSMs, components

Page 12: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.12 Copyright (C) 1998 UCB

Levels of Representation (Review)

High Level Language Program

Assembly Language Program

Machine Language Program

Control Signal Specification

Compiler

Assembler

Machine Interpretation

temp = v[k];

v[k] = v[k+1];

v[k+1] = temp;

lw $15, 0($2)lw $16, 4($2)sw $16, 0($2)sw $15, 4($2)

0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111

°°

ALUOP[0:3] <= InstReg[9:11] & MASK

Page 13: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.13 Copyright (C) 1998 UCB

What is “Computer Architecture”

Computer Architecture =

Instruction Set Architecture +

Machine Organization

Page 14: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.14 Copyright (C) 1998 UCB

Instruction Set Architecture (subset of Computer Arch.)

... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation. – Amdahl, Blaaw, and Brooks, 1964

SOFTWARESOFTWARE-- Organization of Programmable Storage

-- Data Types & Data Structures: Encodings & Representations

-- Instruction Set

-- Instruction Formats

-- Modes of Addressing and Accessing Data Items and Instructions

-- Exceptional Conditions

Page 15: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.15 Copyright (C) 1998 UCB

The Instruction Set: a Critical Interface

instruction set

software

hardware

Page 16: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.16 Copyright (C) 1998 UCB

Example ISAs (Instruction Set Architectures)

° Digital Alpha (v1, v3) 1992-97

° HP PA-RISC (v1.1, v2.0) 1986-96

° Sun Sparc (v8, v9) 1987-95

° SGI MIPS (MIPS I, II, III, IV, V) 1986-96

° Intel (8086,80286,80386, 1978-96 80486,Pentium, MMX, ...)

Page 17: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.17 Copyright (C) 1998 UCB

MIPS R3000 Instruction Set Architecture (Summary)

° Instruction Categories• Load/Store

• Computational

• Jump and Branch

• Floating Point

- coprocessor

• Memory Management

• Special

R0 - R31

PCHI

LO

OP

OP

OP

rs rt rd sa funct

rs rt immediate

jump target

3 Instruction Formats: all 32 bits wide

Registers

Page 18: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.18 Copyright (C) 1998 UCB

Organization

Logic Designer's View

ISA Level

FUs & Interconnect

° Capabilities & Performance Characteristics of Principal Functional Units

• (e.g., Registers, ALU, Shifters, Logic Units, ...)

° Ways in which these components are interconnected

° Information flows between components

° Logic and means by which such information flow is controlled.

° Choreography of FUs to realize the ISA

° Register Transfer Level (RTL) Description

Page 19: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.19 Copyright (C) 1998 UCB

Example Organization

° TI SuperSPARCtm TMS390Z50 in Sun SPARCstation20

Floating-point Unit

Integer Unit

InstCache

RefMMU

DataCache

StoreBuffer

Bus Interface

SuperSPARC

L2$

CC

MBus Module

MBus

L64852 MBus controlM-S Adapter

SBus

DRAM Controller

SBusDMA

SCSIEthernet

STDIO

serialkbdmouseaudioRTCBoot PROMFloppy

SBusCards

Page 20: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.20 Copyright (C) 1998 UCB

What is “Computer Architecture”?

I/O systemInstr. Set Proc.

Compiler

OperatingSystem

Application

Digital DesignCircuit Design

Instruction Set Architecture

Firmware

° Coordination of many levels of abstraction

° Under a rapidly changing set of forces

° Design, Measurement, and Evaluation

Datapath & Control

Layout

Page 21: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.21 Copyright (C) 1998 UCB

Forces on Computer Architecture

ComputerArchitecture

Technology ProgrammingLanguages

OperatingSystems

History

Applications

(A = F / M)

Constraintse.g. cost, energy

Page 22: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.22 Copyright (C) 1998 UCB

Technology => dramatic change

° Processor• logic capacity: about 30% per year

• clock rate: about 20% per year

° Memory• DRAM capacity: about 60% per year (4x every 3 years)

• Memory speed: about 10% per year

• Cost per bit: improves about 25% per year

° Disk• capacity: about 60% per year

Page 23: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.23 Copyright (C) 1998 UCB

VLSI commercial IC technology extrapolations

Page 24: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.24 Copyright (C) 1998 UCB

Technology

° In ~1985 the single-chip processor (32-bit) and the single-board computer emerged

• => workstations, personal computers, multiprocessors have been riding this wave since

° In the 2002+ timeframe, these may well look like mainframes compared single-chip computer (maybe 2 chips)

DRAM

Year Size

1980 64 Kb

1983 256 Kb

1986 1 Mb

1989 4 Mb

1992 16 Mb

1996 64 Mb

1999 256 Mb

2002 1 Gb

i80286

i80486

Pentium

i80386

i8086

i4004

R10000

R4400

R3010

SU MIPS

1000

10000

100000

1000000

10000000

100000000

1970 1975 1980 1985 1990 1995 2000 2005Transistors

i80x86M68KMIPSAlpha

Microprocessor Logic DensityDRAM chip capacity

Page 25: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.25 Copyright (C) 1998 UCB

Performance Trends

Microprocessors

Minicomputers

MainframesSupercomputers

1995

Year

19901970 1975 1980 1985

Lo

g o

f P

erfo

rma

nce

Page 26: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.26 Copyright (C) 1998 UCB

Processor Performance (SPEC)

Year

Perf

orm

an

ce

0

50

100

150

200

250

300

19

82

19

83

19

84

19

85

19

86

19

87

19

88

19

89

19

90

19

91

19

92

19

93

19

94

19

95

RISC

Intel x86

35%/yr

RISCintroduction

Did RISC win the technology battle and lose the market war?

performance now improves 50% per year (2x every 1.5 years)

Page 27: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.27 Copyright (C) 1998 UCB

Measurement and Evaluation

Architecture is an iterative process -- searching the space of possible designs -- at all levels of computer systems -- constraints of energy, cost (=area) and performance

Good IdeasGood Ideas

Mediocre IdeasBad Ideas

Cost /PerformanceAnalysis

Design

Analysis

Creativity

Page 28: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.28 Copyright (C) 1998 UCB

CEG3420: Course Content

Computer Architecture and Engineering

Instruction Set Design Computer Organization

Interfaces Hardware Components

Compiler/System View Logic Designer’s View

“Building Architect” “Construction Engineer”

Page 29: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.29 Copyright (C) 1998 UCB

CEG3420: So what's in it for me?

° In-depth understanding of the inner-workings of modern computers, their evolution, and trade-offs present at the hardware/software boundary.

• Insight into fast/slow operations that are easy/hard to implementation hardware

° Experience with the design process in the context of a large complex (hardware) design.

• Functional Spec --> Control & Datapath --> Physical implementation

• Modern CAD tools

° Designer's "Conceptual" toolbox.

Page 30: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.30 Copyright (C) 1998 UCB

Conceptual tool box?

° Evaluation Techniques

° Levels of translation (e.g., Compilation)

° Levels of Interpretation (e.g., Microprogramming)

° Hierarchy (e.g, registers, cache, mem,disk,tape)

° Pipelining and Parallelism

° Static / Dynamic Scheduling

° Indirection and Address Translation

° Synchronous and Asynchronous Control Transfer

° Timing, Clocking, and Latching

° CAD Programs, Hardware Description Languages, Simulation

° Physical Building Blocks (e.g., CLA)

° Understanding Technology Trends

Page 31: CEG3420 Computer Design  Lecture 1

Summary

° All computers consist of five components• Processor: (1) datapath and (2) control

• (3) Memory

• (4) Input devices and (5) Output devices

° Not all “memory” are created equally• Cache: fast (expensive) memory are placed closer to the processor

• Main memory: less expensive memory--we can have more

° Interfaces are where the problems are - between functional units and between the computer and the outside world

° Need to design against constraints of performance, power, area and cost

Page 32: CEG3420 Computer Design  Lecture 1

CEG3420 L1 Intro.32 Copyright (C) 1998 UCB

Summary: Computer System Components

Proc

CachesBusses

Memory

I/O Devices:

Controllers

adapters

DisksDisplaysKeyboards

Networks

° All have interfaces & organizations