Cell-Aware Testing

Binod KumarM.Tech(EE)

Outline

Introduction

Introduction

Physical defects like shorts, opens, and transistor defects may occur during the fabrication process of semiconductor devices.

Conventional gate level fault models do not cover many of these defects which can be modeled at the transistor level.

These defects may affect functional operation if left undetected.

Cell-aware testing considers defects at transistor level making them cell aware.

50% of todays standard library

cells are guaranteed to be tested sufficiently with SA patterns

All the present day fault models share the assumption, that a fault only occurs between library cell instances, at the ports of library cells, or outside of library cells between the interconnect lines of the library cells.

ATPG tools apply these standard fault models and do either assume no faults within the library cells, or consider faults inside the library cell based on the gate model used by the ATPG. These gate models are well suitable for propagating fault effects through the library cells and they are useful for injecting faults at the cell ports.

However these gate models are not suitable for modeling real layout based defects inside library cells.

Gate-Exhaustive

N-Detect-the well-known n-detect tests, suffer from significant

test size increases., or

Embedded-Multi-Detect-embedding multi-

detection of faults within regular ATPG patterns results in

a higher quality without a significant increase in test set

size,

which either are too complex

for real-world designs or merely improve the

probability of detecting intra-cell defects, the new

approach targets the actual root causes of intra-cell

defects.

In N-Detect testing, the chance of detection is improved

by targeting the same fault multiple times under

different conditions. However, this typically also

increases the pattern set by a factor N and therefore

makes the test costly. The concept of the EMD ATPG

technique addresses this increase in pattern count

The major contribution of the EMD-based approach

was to increase the defect coverage by exploiting

unused bits in existing patterns, instead of adding

further test patterns as proposed by methods based on

N-Detect. The major disadvantage of methods like N-

Detect or EMD is that there exists only a probabilistic

relation to actual defects.

Layout Extraction

The first part of the flow in Fig. 1 is the layout extraction

step, which reads the layout data (file F1) of the individual

library cell and creates a SPICE transistor netlist in detailed

standard parasitic format (DSPF) including parasitic elements

like resistors and capacitors which is stored in file F2. As

an example, lets consider a 3-to-1 multiplexer cell from a

65 nm library. The corresponding layout with some defects

highlighted is shown in Fig. 3.

Defect extraction from cell layout

Analog Simulation

The second part of the CAT view generation flow as

shown in Fig. 1 is analog fault simulation, which starts with

the extraction of considered defects from the DSPF SPICE

netlist. The resulting considered defects are stored in the cell-dependent defects file (file F3 in Fig. 1). The defects con-

sidered are single hard defects, not parametric variations from

IC processing, and they occur at sites where there are SPICE

netlist components, both intentional and parasitic.

Open: Any cell-internal open defect, such as an open in poly, metal, diffusion, or vias. In the extracted SPICE netlist, these defects are matched to existing resistor elements by increasing their resistance values. Different open resistor values are considered as necessary.

2) Bridge: Any cell-internal bridge defect such as bridges between adjacent objects in the same layer or different layers. In the extracted SPICE netlist, these defects

are matched to existing capacitor elements by inserting resistors in parallel with them. Different bridge resistor values are considered as necessary.

3) Tleak: Any cell-internal transistor defect that will switch a transistor partially on with a certain resistive value.

Different leakage resistor values are considered as necessary.

Tdrive: Any cell-internal defect that will switch a tran-

sistor partially off with a certain resistive value. Different

drive strength resistor values are considered as neces-

sary.

5) PortBridge: A bridge between a port (e.g., D1) and VSS,

VDD, or any other port of the cell. Different bridge

resistor values are considered as necessary.

6) PortOpen: A disconnected port (e.g., D1), to analyze the

effect of cell-external disconnects to cell ports. Different

open resistor values are considered as necessary.

Extracted transistor netlist and inserted defects.

Analog simulation environment