Cell Cell

microprocessormicroprocessorinside PlayStation 3

Present by Jinyun Bian, Xin Huang, Jian Li

AbstractAbstract

� Developed by Sony, Toshiba, and IBM

� The first major commercial application of Cell was in Sony's PlayStation 3 game console

� Used in some SuperComputer

A Cell ProcessorA Cell Processor

ArchitectureArchitecture� external input and output structures

� the main processor called the Power Processing Element (PPE)

� eight fully functional co-processors called the Synergistic Processing Elements, or SPEs

� a specialized high-bandwidth circular data bus connecting the PPE, input/output elements and the SPEs, called the Element Interconnect Bus or EIB

ArchitectureArchitecture

Memory flow controllerLocal StorageSynergistic Processing Unit

Die photoDie photo

Power Processor Element (PPE)� The controller for the eight SPEs

� Similarity to other 64-bit PowerPC processors

� L1, L2 cache

� AltiVec unit: fully pipelined for single precision floating point

� Each PPE can complete two double precision operations per clock cycle

� 3.2 GHz

� Double precision: 6.4G FLOPS

� Single precision: 25.6G FLOPS

FLOPSFLOPS

� floating point operations per second

� a measure of a computer's performance, especially in fields of scientific calculations that make heavy use of floating point calculations

� Linpack benchmark

ComparisonComparison

� a simple calculator needs 10 FLOPS

� ENIAC: 300 FLOPS

� Intel Core i7-980 XE: 107.6G FLOPS

� SONY PS3: 218G FLOPS

� nVIDIA Geforce GTX 280: 720G FLOPS

� Tianhe-1: 2.566P FLOPS

� Folding@Home network average: 4.1P FLOPS

� K Computer: 8.162P FLOPS

Synergistic Processing Elements (SPE)� An SPE is a RISC processor for single and double precision instructions

� contain a 128-bit register

� operate on sixteen 8-bit integers, eight 16-bit integers, four 32-bit integers, or four single-precision floating-point numbers in a single clock cycle

� handle most of the computational workload

� At 3.2 GHz, each SPE gives a theoretical 25.6 GFLOPS of single precision performance

Element Interconnect Bus (EIB)

� The EIB is a communication bus internal to the Cell processor which connects the various on-chip system elements: the PPE processor, the memory controller (MIC), the eight SPE coprocessors, and two off-chip I/O interfaces

� Bandwidth: 204.8 GB/s

ArchitectureArchitecture

Memory flow controllerLocal StorageSynergistic Processing Unit

AdvantageAdvantage

�Operation on floating point number

� Multi-core, Multi-thread

� Decoding/Encoding MPEG streams

� Generating or transforming three-dimensional data

� Matrix Multiplication

� Accelerate 3D

� Multi-OS support

� Physics Simulation

ApplicationsApplications

� Video processing card

� Server

� Console video games(PlayStaion 3)

� Supercomputing(IBM Roadrunner)

� Distributed computing(PlayStation 3 consoles)

� Password cracking

Thank youThank you