CellularAutomata-BasedParallelRandomNumber ...2 International Journal of Reconﬁgurable Computing produces an unrepeatable sequence of random numbers [17]. Both types of random number

Hindawi Publishing CorporationInternational Journal of Reconfigurable ComputingVolume 2012, Article ID 219028, 13 pagesdoi:10.1155/2012/219028

Research Article

Cellular Automata-Based Parallel Random NumberGenerators Using FPGAs

David H. K. Hoe, Jonathan M. Comer, Juan C. Cerda,Chris D. Martinez, and Mukul V. Shirvaikar

Department of Electrical Engineering, The University of Texas at Tyler, TX 75799, USA

Correspondence should be addressed to David H. K. Hoe, [email protected]

Received 13 February 2012; Revised 4 June 2012; Accepted 20 June 2012

Academic Editor: Dionisis Pnevmatikatos

Copyright © 2012 David H. K. Hoe et al. This is an open access article distributed under the Creative Commons AttributionLicense, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properlycited.

Cellular computing represents a new paradigm for implementing high-speed massively parallel machines. Cellular automata (CA),which consist of an array of locally connected processing elements, are a basic form of a cellular-based architecture. The use of fieldprogrammable gate arrays (FPGAs) for implementing CA accelerators has shown promising results. This paper investigates thedesign of CA-based pseudo-random number generators (PRNGs) using an FPGA platform. To improve the quality of the randomnumbers that are generated, the basic CA structure is enhanced in two ways. First, the addition of a superrule to each CA cell isconsidered. The resulting self-programmable CA (SPCA) uses the superrule to determine when to make a dynamic rule change ineach CA cell. The superrule takes its inputs from neighboring cells and can be considered itself a second CA working in parallelwith the main CA. When implemented on an FPGA, the use of lookup tables in each logic cell removes any restrictions on how thesuper-rules should be defined. Second, a hybrid configuration is formed by combining a CA with a linear feedback shift register(LFSR). This is advantageous for FPGA designs due to the compactness of the LFSR implementations. A standard software packagefor statistically evaluating the quality of random number sequences known as Diehard is used to validate the results. Both theSPCA and the hybrid CA/LFSR were found to pass all the Diehard tests.

1. Introduction

Cellular computing is touted as one of the new paradigmsfor future computational systems due to three key properties:simplicity, massive parallelism, and local interconnect [1].Such systems have advantages over the traditional general-purpose processor in terms of high-speed parallel compu-tation and fault tolerant capabilities. A variety of uniqueapplications have been proposed and implemented using thecellular computational model including fault-tolerant self-healing architectures [2], cellular neural networks [3, 4], andpseudo-random number generators [5]. Cellular automata(CA), which consist of an array of locally interconnected, ele-mentary processing elements, can be viewed as one form of ahigh-speed massively parallel machine. As CA are dynamicalsystems which evolve in discrete time and space, they are

used to model a variety of physical and biological processes,including fluid dynamics, the immune system, the evolutionof genetic regulatory networks, and urban traffic flow [6–10]. A CA-based architecture will likely form the basis forthe development of ultra-high speed and compact quantum-based computers [11, 12]. However, the programming ofa CA-based machine to compute complex problems is achallenging and unresolved issue [13–15]. Also noteworthyis the development of a cellular automata hardware emulatorknown as the Wolfram machine [16].

This paper investigates a specific application for CA-based computation: the implementation of a high-qualitypseudo random number generator (PRNG) [5]. A goodPRNG will produce a sequence of repeatable, but high-quality, random numbers based on an initial seed. This is incontrast to a true random number generator (TRNG) which

2 International Journal of Reconfigurable Computing

produces an unrepeatable sequence of random numbers[17]. Both types of random number generators are needed,for example, for computer security applications, where aTRNG is used to seed a PRNG with a completely randomnumber. In addition, PRNGs are required in a varietyof areas including Monte Carlo simulations, on-chip self-test circuitry, and optimization methods such as simulatedannealing and genetic algorithms.

Reconfigurable platforms such as field programmablegate arrays (FPGAs) have been investigated for implementingcellular computing machines [18–20]. As an FPGA consistsof an array of reconfigurable logic cells, it provides an attrac-tive platform for implementing CA-based computationalstructures. In this paper, the potential for using FPGAs toimplement high-quality random number generators usingcellular automata is explored.

In many hardware implementations, it is desirable tooptimize performance of the PRNGs in terms of speed,area, and power dissipation, while producing high-qualityrandom numbers. For example, due to advances in very largescale integration (VLSI) processing technology, the complex-ity of integrated circuit designs now make it feasible, andeven necessary, to place self-test circuits on the chip itself.The hardware overhead introduced by a built-in self-test(BIST) module should be a small portion of the overall cir-cuit. A common method for implementing a PRNG for self-testing circuits is a linear feedback shift register (LFSR), sinceit can be compactly constructed from a series of cascadedflip-flops and a few XOR gates. However, for certain testsinvolving stuck-open faults that can convert a combinationalcircuit to a sequential one, the correlation between adjacentnumbers in a test vector sequence should be minimized.Due to the shifting properties of the LFSR, it is known tohave problems with detecting sequential faults [21]. Wolframsuggested in 1986 that cellular automata (CA) could be usedfor efficiently generating random numbers due to the useof nearest neighbor interconnectivity and regularity in theirphysical layout [5]. Subsequent research has demonstratedthat heterogeneous CA, which are composed of two linearfunctions, are more suited for test vector generation for BISTthan LFSRs and the homogeneous CAs originally proposedby Wolfram [22].

Advances in VLSI technology have also made it possibleto implement complex digital systems on FPGAs. BecauseFPGA designs can be optimized for a given application,they often have superior performance in terms of speed andpower dissipation over generic integrated circuit designs andmicroprocessor-based implementations. As an example, foran application involving signal processing for radio astron-omy, an FPGA-based system built using a 130 nm processtechnology was compared with a DSP fabricated with a com-parable technology and a microprocessor fabricated froma 90 nm technology. The FPGA system had 10 times thethroughput compared with the DSP design and 4 timesthe throughput of the microprocessor-based system [23].Similar improvements are reported by others [24, 25]. Forthis reason, FPGAs are increasingly being used in areas for-merly dominated by application specific integrated circuits(ASICs), such as embedded system design and digital signal

D

Q QQ

DD

Bit 1 Bit 2 Bit 3

Figure 1: Schematic of a maximal length 3-bit linear feedback shiftregister.

State

Rule

State

Rule

State

Rule

Figure 2: A one-dimensional nearest neighbor cellular automata.

processing applications. Hence, there is a need to explore theimplementation of PRNGs on FPGAs.

An FPGA typically consists of an array of logic cells thatcan be arbitrarily connected through programmable inter-connect. Each logic cell usually consists of a programmablelookup table (LUT), a flip-flop, and several multiplexers. Thestructure of the FPGA has an impact on the optimal designof PRNGs that will differ from a VLSI implementation. Forexample, a Xilinx FPGA has the ability to convert selectedLUTs into shift registers. As such, a 52-bit LFSR can beefficiently implemented using only four logic cells [26]. Bycontrast, it takes at least one logic cell to implement eachCA cell. For this reason, it is interesting to explore theconstruction of a PRNG that combines a CA with an LFSR.Another configuration of interest is a CA that updates itsown internal rules based upon the states of cells in itsneighborhood as proposed in [27]. While an efficient VLSIdesign restricts the possible rules that can be implementedin order to minimize the number of logic gates used, theuse of LUTs removes this constraint in an FPGA design. Theobject of this paper is to investigate the quality of the randomnumbers that can be produced using the aforementioneddesigns while considering the amount of resources requiredwhen implemented on an FPGA. The widely used statisticaltests implemented in the Diehard program are used toevaluate the quality of the random numbers [28]. The XilinxSpartan-3E FPGA is the reconfigurable platform used in thisstudy.

This paper is organized as follows. Section 2 providessome background on the design of LFSRs and CAs as well asdescribing the relevant previous work in this area. Section 3on research method describes the PRNG configurations thatare evaluated and the simulation strategy used. Section 4contains the results and a discussion of their implementation.Conclusions and future work are given in Section 5.

International Journal of Reconfigurable Computing 3

Rule 90

(a)

Rule 150

(b)

Figure 3: Graphical representations of CA rules “90” and “150” [6].

State

Rule

State

Rule Rule

State

Rule

State

Rule Rule

State

Rule

State

Rule Rule

State

Rule Rule

State

Rule Rule

State

Rule Rule

State

Rule

State

Rule

State

Rule

Figure 4: Schematic of the self-programmed cellular automata(SPCA).

2. Background and Previous Work

This section overviews the design of linear feedback shiftregisters (LFSRs) and cellular automata (CA), followed by areview of related works that have utilized LFSRs and CA forgenerating random numbers.

An LFSR consists of a shift register where selected out-puts, known as taps, are fed into an XOR gate. In an LFSRusing external feedback, the output of the XOR gate isthen fed into the input of the shift register, as illustratedin Figure 1. Internal feedback LFSRs will place XOR gatesbetween selected flip-flops that form the shift register. Thelocation of the taps determines the pattern generated by theLFSR. An LFSR is said to have maximal length if it cangenerate a pattern which is 2n − 1 before repeating, wheren is the length of the shift register. While the LFSR can becompactly implemented in both VLSI and FPGA designs,the shifting operation produces a high degree of correlationbetween adjacent bits.

A cellular automata can be viewed as a state machineconsisting of an array of cells which hold their current states.The CA will evolve in discrete timesteps, where the nextstate of each cell is determined by the states of the cellsin its “neighborhood” according to some specified rule. Acommon configuration is a one dimensional CA with binarystate values, and a neighborhood consisting of the cell’s ownstate and those of its immediate neighbors, as depicted inFigure 2.

Such a one-dimensional CA can be represented as anarray of n cells, {s1(t), s2(t), . . . , sn(t)}, where si(t) represents

the binary state of the ith cell at time t. As an example of anupdate rule for the one dimensional CA, consider

si(t + 1) = si+1(t)⊕ si−1(t). (1)In this case, the current state of the ith cell is determined

by taking the exclusive-OR of its two immediate neighbors.A pictorial representation of how this rule is encoded isillustrated in Figure 3, where the top row represents the eightpossible configurations for a three-cell neighborhood and thebottom row represents the next state for the cell of interest.Since the eight bits in the bottom row represent a value of 90in decimal, this update rule is dubbed rule “90” [6].

The current state of the ith cell can be included in theupdate rule that uses the exclusive-OR operations, as repre-sented by (2):

si(t + 1) = si+1(t)⊕ si(t)⊕ si−1(t). (2)In this case, the binary representation of the rule results

in a value of 150 in decimal, and hence, (2) represents the CArule “150.” While higher dimensions and state values can beused, this paper will focus on one-dimensional CA with eachstate represented by a single bit.

As noted by Hortensius et al., if different rules are usedin each cell (heterogeneous CA), higher quality randomnumbers can be generated from a CA than if a uniform(homogeneous) rule is applied to all cells [22]. Combinationsof rules 90 and 150 were found to produce good randomnumbers with maximal length suitable for BIST. These rulesare popular since they can be generated using XOR gates,where analysis in GF(2) can be used to determine maximallength CA. The use of time and site spacing was shown tofurther decorrelate adjacent bits. Further work on hybrid90/150 CA for generating self-test circuitry was carried outby Nandi et al. [29].

Guan and Tan proposed a one-dimensional CA where therule in each cell changes dynamically based upon the statesof the cells within a new neighborhood of three cells [27].Dubbed “self-programmable cellular automata” (SPCA), therules are switched between 90 and 165 or 150 and 105. Theserules were selected because they can be easily implementedwith XOR gates. The SPCA is diagramed in Figure 4. A“super-rule” is used to determine how the rules within theCA are switched, based on neighboring cells which can be upto a distance of three cells away. The use of the super-rule canhelp avoid the patterns that occur when cells have static rules.These patterns are indicative of low-quality random numbersequences because they give rise to recurring structures (e.g.,the “triangle pattern” seen in Figure 5(a)).

Each cell in the SPCA can be thought of as having a hier-archical structure (i.e., a “super rule” and a “rule state”),


22 cells

50

0

Rule 90

Tim

este

ps

(a)

90/150

(b)

90/165 SPCA

(c)

Figure 5: Space-time evolution patterns for: (a) a simple rule-90 CA, (b) a hybrid 90/150 CA, and (c) the SPCA using rules 90/165 andsuper-rule 90. All are initialized with a single bit in the center.

CACA CA CA CA CA CA CA CACACACACA

FFFFFFFFFF

CACACA

SR16 SR16

Figure 6: Schematic of a hybrid CA/LFSR FPGA implementation.SR16 represent the LUT-based 16-bit shift registers. Combined withthe flip-flops (FFs), it forms a 37-bit LFSR.

which together control the lower parts: two rules and astate. This type of CA may also be thought of as twointerlinked parallel CA (Figure 4), one of which (the “lower”CA) depends on the other (the “upper” CA) to decide whichof its two internal rules is to be used in the next timestep.But the upper CA also depends on the states of the lower CAto determine its own states. The neighborhoods of the upperand lower CA need not be the same.

During each timestep, two things happen simultaneouslyin each cell: the “upper” cell checks its neighborhood andapplies its rule to determine and update its next state, whilethe “lower” cell checks its neighborhood and the state ofthe upper cell and then applies the appropriate rule to itsinputs and updates its new state. Because these events happensimultaneously, the lower cell always uses the rule indicatedby the upper cell during the previous timestep, not thecurrently updating state of the upper cell. The use of theupper CA to switch the rules of the lower CA provides anadditional randomizing effect. An inspection of the space-time diagram for a hybrid 90/150 CA and the SPCA, shown

in Figure 5, reveals the improved quality of the randomnumbers generated from the latter.

In [27], SPCA of lengths from 16 to 24 bits were foundthat could pass all the statistical tests using the Diehardprogram. This paper investigates the implementation of theSPCA on FPGAs where it should be noted that the use ofLUTs allows more flexibility in the choice of rule selection.

Tkacik proposed a random number generator whichcombines the outputs of a CA with an LFSR [30]. A 37bit CA was combined with a 43-bit LFSR. This maximallength configuration combined 32 bits from the CA andLFSR to produce a maximal length RNG. It was found thatthe LFSR and CA must be clocked at different frequencies tocreate a sequence of numbers that can pass all the Diehardtests. Figure 6 depicts the version implemented on FPGAsin our work. The last bit of the LFSR and CA can becombined in an XOR gate to produce a single random bitin order to generate maximal site spacing. In the designdepicted in Figure 6, three additional internal nodes fromthe LFSR and CA are combined with XOR gates to generatefour bits each clock cycle. The advantage of this sitespacing [22], as we shall see, is that a sequence of randomnumbers can be produced that passes all of the Diehardtests without clocking the LFSR and CA at different rates.This technique makes use of site spacing in order to avoidany correlation between neighboring bits. It does, however,lead to decreased throughput (only up to 4 bits per timestep)which is undesirable because it may take several cycles togenerate a multibit random number. In [30], Tkacik statesthe maximal length of a combined CA and LFSR is 2m+n −2m − 2n + 1 for an m-sized CA and an n-sized shift register.This is true if the cycle lengths of the individual CA andLFSR are relatively prime. A 37 bit shift register and 16bit cellular automata represent one example of a maximallength CA/LFSR configuration that was studied in this work(Figure 6).


FXINAFXINB

1

COUT

10

YB

FX

Y

YQ

BY

FXINA

FXINB

1

10

YB

X

XQ

BX

CIN

CE

1G

BY

PROD

10

10

FXGXORG

10

SRHIGHSRLOW

SR REV

1F

D

BX

PROD

10

FG

F

10

BX

BX CIN

CE

CLK

SR

Lower cellD QCE FFCK

INIT1INIT0

LATCH

Upper cell

Reset type

SYNCASYNC

SEHIGHSELOW

FF

INIT1INIT0

LATCH

SR REV

D QCECK

CLK

SR

F4 ca

F3 caF2F1

A4A3A2A1

F5FXOR

S00 1

BYBY B

DA4A3A2A1

G2

G1

S00 1

F5

G4 caG3 caG2 caG1

⟨20⟩⟨18⟩⟨19⟩

⟨21⟩⟨18⟩

clkout 0BU

reset 1BUF

BX B

CE B

CLK B

SR B

F1

F2

ca ⟨19⟩

ca ⟨19⟩

Figure 7: FPGA editor view of the hard macro used to form an SPCA cell showing the lower and upper cells.

3. PRNGs Implemented on FPGAs

This section describes the various CA configurations thatwere considered for implementation on FPGAs and the sim-ulation method used to determine the quality of randomnumbers that were produced by each design.

Two programs were written in C to simulate the twoPRNGs: SPCA and the hybrid LFSR/CA. These simulationsoutput the states of the various components of the PRNGs,allowing analysis and confirmation of the hardware output.The Linux command diff was used to compare the outputfiles from the simulations to the test data obtained from logicanalyzer measurements.

Logisim was used as a secondary simulator to confirm theresults of the C program. The usefulness of Logisim lies in its

graphical representation of the simulation, which makessome flaws more obvious and easier to fix than in C code.C code, however, is itself sometimes easier to debug andis much faster. With the diff command, the outputs fromLogisim, C, and the FPGA hardware were all able to beautomatically compared. A combination of VHDL code andhard macros were used to implement these PRNGs on anFPGA. The hard macro used to form the SPCA cell is shownin Figure 7. One whole cell is contained in this hard macro,which uses one slice on the Spartan 3E FPGA. Both ofthe theoretical upper and lower cells are included in thismacro. The dashed circle and arrow constitute the “lower”cell, and the solid circle and arrow constitute the “upper”cell. The circles are lookup tables (LUTs). These process theinputs from neighboring cells, applying the desired rule and


(a) (b)

Figure 8: (a) The FPGA editor snapshot showing the layout of the 22-cell SPCA, using 30 slices (small, colored boxes). (b) The FPGA editorview of a portion of the CA + LFSR implementation. The inset shows a pair of hard macros used to realize the CAs.

outputting the new cell state. The flip-flops (FFs) that holdthe cell’s state and super-rule state are indicated with dashedand solid arrows, respectively.

Our SPCA uses rules 90 and 165 for the lower cells andrule 90 for the super-rule. The upper cells have a neighbor-hood of −2, +1. We have simulated this CA using a Cprogram and confirmed with a Logisim simulation.

One of the limitations of the design in [27] is that thePRNG was designed for a VLSI implementation. Therefore,pairs of rules that can be implemented with minimal over-head were chosen. However, since our PRNGs will be imple-mented on FPGAs, we are not subject to the same types ofoverhead. As the basic logic unit in the Spartan 3E FPGAis a 4-input LUT, it takes up the same area whether it isimplementing a logical AND, an XOR, or a more complicatedrule or pair of rules. Therefore, all 256 rules or any pair ofthese rules are available at the same cost in overhead.

A pair of rules can be implemented in a 4-input LUTbecause three inputs can be used for the neighborhood (leftneighbor, cell’s own state, right neighbor) and the fourthinput can be used to consider the state of the super rule—thatis, to select which rule to use. If the rule selector is 0, rule 90is applied to the other three inputs; but if the rule selector is1, rule 165 is applied. As with the case of the SPCA, an LFSRis easily implemented using a 4-input LUT. In this case, thelook-up table is configured as a 16-bit shift register. The LUTis configured as an addressable shift register rather than withfixed values and is referred to as a Shift Register LUT 16-bit(SRL16). The SRL16 allows for very efficient and compactFPGA implementations of LFSRs.

As previously noted, a hybrid LFSR + CA PRNG con-sisting of two state machines which are relatively prime intheir cycle lengths will generate a sequence equal to 2n+m −2n − 2m + 1 [30]. The advantage of this hybrid approach forFPGA implementation is the possible design tradeoffs. AnLFSR by itself does not produce a good random sequence butcan be compactly implemented on an FPGA. By comparison,a CA consumes more FPGA resources but provides goodpseudorandom sequences due to the absence of adjacent bitcorrelations. The objective here is to create a new PRNG thatpossesses the CA’s randomness and the LFSR’s compactness.

A 16 cell heterogeneous CA consisting of a mixture ofrules 90 and 150 was utilized as the baseline design. The ruleswere arranged to yield a maximal length pattern as describedin [22]. This PRNG was implemented on an FPGA and wasverified to run properly. Usage of hard macros allowed eachcell to fit in one slice. This baseline PRNG failed many of theDiehard tests as shown in Table 4. A similar 22-cell hybridCA was also simulated for comparison with the 22-cell SPCA.This CA too failed most of the Diehard tests as expected(Table 4).

4. Performance Evaluation

This section evaluates the FPGA PRNG implementationsin terms of the quality of the random numbers, hardwareresources utilized, throughput, and test results. The tapsrequired to implement the various LFSRs in this study wereobtained from [26] and are summarized in Table 1.

4.1. Overhead. The different CA combinations for the SPCAand CA/LFSR hybrid that were synthesized on an FPGA andassociated resource usage are summarized in Table 2. Whensynthesized on a Xilinx Spartan 3E FPGA, a 52-bit LFSRrequires 4 slices (3 flip-flops and 5 LUTs) while a 16 cellCA requires 16 slices (16 flip-flops and 16 LUTs). The 22-bit SPCA requires 30 slices (44 flip-flops and 60 LUTs). TheSPCA is larger because it uses one slice per cell (1 bit) whilethe LFSR takes advantage of the compact 16 bit shift-registerimplementation in a single LUT (i.e., half a slice).

Figure 8(a) shows the FPGA editor view of the SPCA.Each colored box is a cell or some auxiliary circuit such asa multiplexer for initializing the SPCA.

Figure 8(b) shows the view of the LFSR + CA combina-tion. The inset highlights the bulls-eye marking that indicatesa slice containing the hard macro for implementing one cellof the cellular automaton.

4.2. Quality of the Generated Random Numbers. TheDiehard suite of statistical tests was run on all the config-urations listed in Tables 3 and 4. The tables also summarize


0

50

100

150

200Fr

equ

ency

0.0-

0.1

>0.

1-0.

2

>0.

2-0.

3

>0.

3-0.

4

>0.

4-0.

5

>0.

5-0.

6

>0.

6-0.

7

>0.

7-0.

8

>0.

8-0.

9

>0.

9-0.

1

P-values

16 hybrid CA

(a)

0

10

20

30

40

50

60

70

80

90

Freq

uen

cy

22 hybrid CA

0.0-

0.1

>0.

1-0.

2

>0.

2-0.

3

>0.

3-0.

4

>0.

4-0.

5

>0.

5-0.

6

>0.

6-0.

7

>0.

7-0.

8

>0.

8-0.

9

>0.

9-0.

1

P-values

(b)

0

5

10

15

20

25

30

35

40

45

Freq

uen

cy

22 SPCA

0.0-

0.1

>0.

1-0.

2

>0.

2-0.

3

>0.

3-0.

4

>0.

4-0.

5

>0.

5-0.

6

>0.

6-0.

7

>0.

7-0.

8

>0.

8-0.

9

>0.

9-0.

1

P-values

(c)

0

5

10

15

20

25

30

35

40

45

Freq

uen

cy

30 LFSR + 16 CA

0.0-

0.1

>0.

1-0.

2

>0.

2-0.

3

>0.

3-0.

4

>0.

4-0.

5

>0.

5-0.

6

>0.

6-0.

7

>0.

7-0.

8

>0.

8-0.

9

>0.

9-0.

1

P-values

(d)

0

5

10

15

20

25

30

35

40

45

Freq

uen

cy

31 LFSR + 8 CA

0.0-

0.1

>0.

1-0.

2

>0.

2-0.

3

>0.

3-0.

4

>0.

4-0.

5

>0.

5-0.

6

>0.

6-0.

7

>0.

7-0.

8

>0.

8-0.

9

>0.

9-0.

1

P-values

(e)

0

5

10

15

20

25

30

35

40

45

Freq

uen

cy

31 LFSR + 16 CA

0.0-

0.1

>0.

1-0.

2

>0.

2-0.

3

>0.

3-0.

4

>0.

4-0.

5

>0.

5-0.

6

>0.

6-0.

7

>0.

7-0.

8

>0.

8-0.

9

>0.

9-0.

1

P-values

(f)

Figure 9: Continued.


0

10

15

20

25

30

35

40

45Fr

equ

ency

35 LFSR + 8 CA

0.0-

0.1

>0.

1-0.

2

>0.

2-0.

3

>0.

3-0.

4

>0.

4-0.

5

>0.

5-0.

6

>0.

6-0.

7

>0.

7-0.

8

>0.

8-0.

9

>0.

9-0.

1

P-values

(g)

0

5

10

15

20

25

30

35

40

45

Freq

uen

cy

35 LFSR + 16 CA

0.0-

0.1

>0.

1-0.

2

>0.

2-0.

3

>0.

3-0.

4

>0.

4-0.

5

>0.

5-0.

6

>0.

6-0.

7

>0.

7-0.

8

>0.

8-0.

9

>0.

9-0.

1

P-values

(h)

0

5

10

15

20

25

30

35

40

45

Freq

uen

cy

37 LFSR + 16 CA

0.0-

0.1

>0.

1-0.

2

>0.

2-0.

3

>0.

3-0.

4

>0.

4-0.

5

>0.

5-0.

6

>0.

6-0.

7

>0.

7-0.

8

>0.

8-0.

9

>0.

9-0.

1

P-values

(i)

5

0

10

15

20

25

30

35

40

45

Freq

uen

cy52 LFSR + 8 CA

0.0-

0.1

>0.

1-0.

2

>0.

2-0.

3

>0.

3-0.

4

>0.

4-0.

5

>0.

5-0.

6

>0.

6-0.

7

>0.

7-0.

8

>0.

8-0.

9

>0.

9-0.

1

P-values

(j)

5

0

10

15

20

25

30

35

40

45

Freq

uen

cy

52 LFSR + 16 CA

0.0-

0.1

>0.

1-0.

2

>0.

2-0.

3

>0.

3-0.

4

>0.

4-0.

5

>0.

5-0.

6

>0.

6-0.

7

>0.

7-0.

8

>0.

8-0.

9

>0.

9-0.

1

P-values

(k)

Figure 9: The P-value distributions obtained from the Diehard test results.


0

5

10

15

20

25

30

35

40

45

Freq

uen

cy

37 LFSR + 16 CA

0.0-

0.1

>0.

1-0.

2

>0.

2-0.

3

>0.

3-0.

4

>0.

4-0.

5

>0.

5-0.

6

>0.

6-0.

7

>0.

7-0.

8

>0.

8-0.

9

>0.

9-0.

1

P-values

0

5

10

15

20

25

30

35

40

45

Freq

uen

cy

0.0-

0.1

>0.

1-0.

2

>0.

2-0.

3

>0.

3-0.

4

>0.

4-0.

5

>0.

5-0.

6

>0.

6-0.

7

>0.

7-0.

8

>0.

8-0.

9

>0.

9-0.

1

P-values

37 LFSR + 16 CA(2 bit word)

0

5

10

15

20

25

30

35

40

45

Freq

uen

cy

0.0-

0.1

>0.

1-0.

2

>0.

2-0.

3

>0.

3-0.

4

>0.

4-0.

5

>0.

5-0.

6

>0.

6-0.

7

>0.

7-0.

8

>0.

8-0.

9

>0.

9-0.

1

P-values

37 LFSR + 16 CA(4 bit word)

Figure 10: P-value distributions for the hybrid 37LFSR + 16CA with 2 and 4 bit outputs per time step. The previous result for the single bitversion is listed again on the left for comparison.

the test results. The names of the tests are listed in Table 5 (formore details on each test, see [28]). Any test that returns a P-value equal to “1.000” or “0.000” is considered to have failedand is represented with an “F” on the table. A test with up totwo P-values equal to “0.999” or “0.001” is said to barely passand is represented with a “BP.” Any test with at least three P-values equal to “0.999” or “0.001” is said to barely fail andis represented with a “BF.” Otherwise, the test is said to pass(represented with a “P”).

The results for maximum site spacing techniques arediscussed first, followed by the maximum throughput results.

As for the various LFSR + CA configurations where only 1 bitis generated per clock cycle (i.e., the maximum site spacingcase), the 37 bit LFSR + 16 bit CA and the 52 bit LFSR +8 bit CA produced the best results, passing all 18 tests. Anintriguing result is that the 52 bit LFSR + 8 bit CA performedslightly better than the 52 bit LFSR + 16 CA.

As can be seen from Table 4, a hybrid CA by itself isinsufficient to pass all the Diehard tests. As for techniqueswith maximum throughput, the SPCA was simulated withtwenty different initial seed patterns for the on-off states ofthe CA. Ten seeds were nonrandom, orderly patterns such as


Table 1: LFSR taps.

LFSR Taps

30 30, 6, 4, 1

31 31, 28

35 35, 33

37 37, 5, 4, 3, 2, 1

52 52, 39

Table 2: FPGA resource utilized by the CAs.

Configuration LUTs Flip-Flops Slices

8 CA 8 8 8

16 CA 16 16 16

31 LFSR 4 3 3

35 LFSR 4 4 4

52 LFSR 5 3 4

30 LFSR + 16 CA 21 19 19

31 LFSR + 8 CA 13 11 11

31 LFSR + 16 CA 21 19 19

35 LFSR + 8 CA 13 12 12

35 LFSR + 16 CA 21 20 20

37 LFSR + 16 CA 21 22 23

52 LFSR + 8 CA 13 11 12

52 LFSR + 16 CA 22 19 20

22 SPCA 60 44 30

all-on, alternating on/off, a single cell on in the middle, andso forth. Six of ten of these simulations failed Diehard usingour standards and two barely passed.

Ten random initial seed patterns were also utilized. Theserandom seeds have an unpatterned set of on/off states withapproximately equal numbers of on and off states. Five ofthese simulations failed Diehard by our standards, onebarely passed, and the remaining four passed all the Diehardtests.

In sum, the SPCA has much greater throughput than theLFSR + CA, while the LFSR + CA is not sensitive to the initialseed values for passing all the Diehard tests.

According to Diehard, an “ideal” PRNG should havea uniform distribution of P-values. Figure 9 compares theP-value distributions for different PRNGs tested usingthe Diehard test suite. PRNG configurations that failedDiehard tests tend to contain a high frequency of P-values inthe 0.9 to 1.0 range as seen for the 35LFSR + 8CA and for thetwo baseline hybrid CA. PRNG configurations that passed alltests such as the 37LFSR + 16CA contain P-values that aremore equally distributed across the range [0,1).

4.3. Tradeoffs between Throughput and Quality of the RandomNumbers Generated. After these results were obtained, it wasconsidered whether a better balance between throughput andquality of randomness could be found. In order to achieve a

Figure 11: Test setup showing the Spartan 3E FPGA developmentboard connected to a Tektronix TLA 7012 logic analyzer.

greater throughput for the LFSR + CA, more than just thelast bits were XORed to generate the output. The number ofbits that could be XORed was limited however, because theshift register bits inside the compact LUT cannot be accessed.Therefore, only bits that were tapped out or that could not beplaced in a LUT were used to XOR with bits from the CA. Intwo different variations of the 37 LFSR + 16 CA, throughputwas increased to 2 and 4 bits per timestep. These PRNGs stillpass all Diehard tests (Table 6). As seen in Figure 10, all theP-value distributions remained relatively level.

4.4. Test Results and Comparisons with Related Works. Thedesigns were implemented on a Xilinx Spartan-3E FPGA andwere tested using a Tektronix TLA 7012 logic analyzer, asshown in Figure 11.

In the SPCA design, each cell was programmed to assumean initial state when an onboard switch was in the “on”position. This initial condition allowed the SPCA to be setand held at an initial state, allowing for consistent readings.After setting up the initial cell states in the FPGA, fourmillion timesteps were read, with the FPGA running at50 MHz. Because the logic analyzer connection to the FPGAboard only had 16 pins, the FPGA was programmed to usean onboard switch to multiplex the output pins between thefirst 16 cells of the 22 SPCA and the last 16 cells. In order toget all 22 states, the FPGA was run twice, starting from thesame initial states each time. On the first run, the states ofthe first 16 cells were read out: on the second run, the statesof the latter 16 cells were read. The 10-cell overlap betweenthese two sets of data helped confirm that they did indeedcoincide. This method was used three times to generate threesets of data from the FPGA. All three sets of data matchedthe simulation. The LFSR + CA has also been successfullyimplemented, matching the simulation.

The hybrid LFSR + CA design could operate at a speed of110 MHz with a power dissipation of 89 mW while the SPCAdesign had a maximum operating frequency of 115 MHz anda power dissipation of 103 mW. In terms of throughput, the


Table 3: Diehard results for LFSR + CA maximum site spacing.

Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

30 LFSR + 16 CA P P P P P P P P P P BP P P BP P P P P

31 LFSR + 8 CA P P P P P P F P P P BP P P P P P P P

31 LFSR + 16 CA P P P P P P P P P P P P P BP P P P P

35 LFSR + 8 CA P P P P BP P F P P P BP P F P P P P P

35 LFSR + 16 CA P P P P P P P P P P BP P P P P P P P

37 LFSR + 16 CA P P P P P P P P P P P P P P P P P P

52 LFSR + 8 CA P P P P P P P P P P P P P P P P P P

52 LFSR + 16 CA P P P P P P P P BP P BP P P P P P P P

Table 4: Diehard results for hybrid CA and SPCA optimized for throughput.

16 CA (90/150) — F F F F F F F F F F F F F F F F F

22 CA (90/150) F F F F F P F F F F F P F P P P P P

22 SPCA P P P P P P P P P P P P P P P P P P

Table 5: Diehard tests.

1 Birthday spacings

2 Overlapping 5-Permuatation

3 Binary rank 31 ∗ 314 Binary rank 32 ∗ 325 Binary rank 6 ∗ 86 Bitstream

7 OPSO

8 OQSO

9 DNA

10 Count-the-1′s

11 Count-the-1′s 2

12 Parking lot

13 Minimum distance

14 3D Spheres

15 Squeeze

16 Overlapping sums

17 Runs

18 Craps

LFSR + CA design can output 440 Mb/sec while the SPCAcan deliver 2530 Mb/sec. The SPCA has a significantly higherthroughput since it outputs all 22 bits in one clock cycle,while the hybrid LFSR + CA design outputs a maximumof 4 bits per clock cycle. The previous designs by Guanand Tan [27] and Tkacik [30] were implemented on customintegrated circuit processes instead of FPGAs, so a directcomparison is not feasible. It can be observed that the SPCAdesign by Guan reported an estimated throughput of 3510Mb/sec for his 20 bit SPCA design [27]. Given that thesedesign simulations targeted a 0.35 µm CMOS process and

that the Spartan-3E FPGA used in our design is built from a90 nm CMOS process, the comparable throughput numbersare consistent with the differences in performances typicallyexperienced between ASIC and FPGA implementations[31].

5. Conclusions

Cellular automata represent a basic form of a high-speedmassively parallel computation engine. Such forms of cellularcomputing can be implemented on current reconfigurableplatforms, such as FPGAs, and will form the basis for quan-tum computers developed for emerging nanotechnologies.This paper has evaluated the performance of CA-basedPRNGs suitable for implementation on FPGAs. Synthesisresults for the Xilinx Spartan 3E FPGA give a good idea ofthe relative resources required for each configuration. TheLFSR + CA combination uses less overhead than the SPCA,due to use of the compact LUT implementation of the LFSR.The Diehard suite of statistical tests was used to evaluatethe quality of the random numbers produced from eachconfiguration. It was found that the 37 bit LFSR + 16 bitCA and the 52 bit LFSR + 8 bit CA and the SPCA withrandom initial seeds passed all the tests. There is a largegap in throughput between the LFSR + CA and the SPCA.This is due to the inaccessibility of bits that are inside thecompact LUT used for the LFSR. In order for more bitsto be accessible, the LFSR must be split up, increasing theoverhead. The SPCA, however, has a high throughput sincethe state of every cell can be used. Although the states of thetheoretical upper CA in the SPCA could be used to doublethroughput, this technique was avoided because it couldcompromise usefulness in an encryption setting [27].

In the future, we will attempt to add more throughputto the LFSR + CA and also explore the aspect of maximumcycle length. The LFSR + CA combination can pack a largenumber of states in a small space using the current design


Table 6: Diehard results for modified throughput LFSR + CA and SPCA.

37 LFSR + 16 CA (2 bit word) P P P P P P P P P P P P P P P P P P

37 LFSR + 16 CA (4 bit word) P P P P P P P P P P P P P P P P P P

of FPGAs. This large quantity of states could give the LFSR+ CA a very long cycle length. In the work reported here,the SPCA has the best throughput, the LFSR + CA has thesmallest overhead, and both can produce quality randomnumbers.

References

[1] M. Sipper, “Emergence of cellular computing,” Computer, vol.32, no. 7, pp. 18–26, 1999.

[2] Z. Zhang, Y. Wang, S. Yang, R. Yao, and J. Cui, “The researchof self-repairing digital circuit based on embryonic cellulararray,” Neural Computing and Applications, vol. 17, no. 2, pp.145–151, 2008.

[3] L. O. Chua and L. Yang, “Cellular neural networks: theory,”IEEE Transactions on Circuits and Systems, vol. 35, no. 10, pp.1257–1272, 1988.

[4] C. Schwarzlmüeller and K. Kyamakya, “Implementing aCNN Universal Machine on FPGA: state-of-the-art and keychallenges,” in Proceedings of the International Symposium onTheoretical Engineering (ISTET ’09), pp. 1–5, June 2009.

[5] S. Wolfram, “Random sequence generation by cellularautomata,” Advances in Applied Mathematics, vol. 7, no. 2, pp.123–169, 1986.

[6] S. Wolfram, A New Kind of Science, Wolfram Media, 2002.[7] B. Chopard and M. Droz, Cellular Automata Modeling of

Physical Systems, Cambridge University Press, 1998.[8] J. Mata and M. Cohn, “Cellular automata-based modeling

program: synthetic immune system,” Immunological Reviews,vol. 216, no. 1, pp. 198–212, 2007.

[9] L. Schramm, Y. Jin, and B. Sendhoff, “Redundancy createsopportunity in developmental representations,” in Proceedingsof the IEEE Symposium on Artificial Life (ALIFE ’11), pp. 203–210, April 2011.

[10] O. K. Tonguz, W. Viriyasitavat, and F. Bai, “Modeling urbantraffic: a cellular automata approach,” IEEE CommunicationsMagazine, vol. 47, no. 5, pp. 142–150, 2009.

[11] L. R. Hook IV and S. C. Lee, “Design and simulation of 2-D 2-dot quantum-dot cellular automata logic,” IEEE Transactionson Nanotechnology, vol. 10, no. 5, pp. 996–1003, 2011.

[12] H. Cho and E. E. Swartzlander, “Adder designs and analysesfor quantum-dot cellular automata,” IEEE Transactions onNanotechnology, vol. 6, no. 3, pp. 374–383, 2007.

[13] M. Mamei, A. Roli, and F. Zambonelli, “Emergence andcontrol of macro-spatial structures in perturbed cellularautomata, and implications for pervasive computing systems,”IEEE Transactions on Systems, Man, and Cybernetics Part A, vol.35, no. 3, pp. 337–348, 2005.

[14] S. Nichele and G. Tufte, “Trajectories and attractors as specifi-cation for the evolution of behaviour in cellular automata,” inProceedings of the 6th IEEE World Congress on ComputationalIntelligence (WCCI ’10), pp. 1–8, July 2010.

[15] H. Kanoh and S. Sato, “Improved evolutionary design forrule-changing cellular automata based on the difficulty of

problems,” in Proceedings of the IEEE International Conferenceon Systems, Man, and Cybernetics (SMC ’07), pp. 1243–1248,October 2007.

[16] L. Fortuna, M. Frasca, A. S. Fiore, and L. O. Chua, “Thewolfram machine,” International Journal of Bifurcation andChaos, vol. 20, no. 12, pp. 3863–3917, 2010.

[17] S. Srinivasan, S. Mathew, R. Ramanarayanan et al., “2.4GHz7mW all-digital PVT-variation tolerant True Random Num-ber Generator in 45nm CMOS,” in Proceedings of the 24thSymposium on VLSI Circuits (VLSIC ’10), pp. 203–204, June2010.

[18] T. Kobori, T. Maruyama, and T. Hoshino, “A cellular automatasystem with FPGA,” in Proceedings of the 9th Annual IEEE Sym-posium on Field-Programmable Custom Computing Machines,pp. 120–129, 2001.

[19] P. A. Mudry, F. Vannel, G. Tempesti, and D. Mange, “CON-FETTI: a reconfigurable hardware platform for prototypingcellular architectures,” in Proceedings of the 21st InternationalParallel and Distributed Processing Symposium (IPDPS ’07), pp.1–8, March 2007.

[20] S. Murtaza, A. G. Hoekstra, and P. M. A. Shot, “Performancemodeling of 2D cellular automata on FPGA,” in Proceedings ofthe International Conference on Field Programmable Logic andApplications (FPL ’07), pp. 74–78, August 2007.

[21] K. Furuya and E. J. McCluskey, “Two-pattern test capabilitiesof autonomous TPG circuits,” in Proceedings of the Interna-tional Test Conference, pp. 704–711, October 1991.

[22] P. D. Hortensius, R. D. McLeod, W. Pries, D. M. Miller, andH. C. Card, “Cellular automata-based pseudorandom num-ber generators for built-in self-test,” IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems, vol.8, no. 8, pp. 842–859, 1989.

[23] P. H. W. Leong, “Recent trends in FPGA architectures andapplications,” in Proceedings of the 4th IEEE InternationalSymposium on Electronic Design, Test and Applications (DELTA’08), pp. 137–141, January 2008.

[24] A. DeHon, “Density advantage of configurable computing,”Computer, vol. 33, no. 4, pp. 41–49, 2000.

[25] J. Sun, G. Peterson, and O. Storaasli, “Sparse matrix-vectormultiplication design on FPGAs,” in Proceedings of the 15thAnnual IEEE Symposium on Field-Programmable Custom Com-puting Machines (FCCM ’07), pp. 349–351, April 2007.

[26] M. George and P. Alfke, “Linear Feedback Shift Registersin Virtex Devices,” Xilinx Application Note XAPP210 (v1.3),2007.

[27] S. U. Guan and S. K. Tan, “Pseudorandom number generationwith self-programmable cellular automata,” IEEE Transactionson Computer-Aided Design of Integrated Circuits and Systems,vol. 23, no. 7, pp. 1095–1101, 2004.

[28] G. Marsaglia, Diehard, 1996, http://stat.fsu.edu/∼geo/diehard.html.

[29] S. Nandi, B. Vamsi, S. Chakraborty, and P. P. Chaudhuri,“Cellular automata as a BIST structure for testing CMOScircuits,” IEE Proceedings, vol. 141, no. 1, pp. 41–47, 1994.


[30] T. E. Tkacik, “A hardware random number generator,” in Pro-ceedings of the Cryptographic Hardware and Embedded Systems(CHES ’02), vol. 2523 of Lecture Notes in Computer Science, pp.450–453, 2003.

[31] I. Kuon and J. Rose, “Measuring the gap between FPGAsand ASICs,” IEEE Transactions on Computer-Aided Design ofIntegrated Circuits and Systems, vol. 26, no. 2, pp. 203–215,2007.

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttp://www.hindawi.com Volume 2010

RoboticsJournal of

Hindawi Publishing Corporationhttp://www.hindawi.com Volume 2014


Active and Passive Electronic Components

Control Scienceand Engineering

Journal of



RotatingMachinery


Hindawi Publishing Corporation http://www.hindawi.com

Journal ofEngineeringVolume 2014

Submit your manuscripts athttp://www.hindawi.com

VLSI Design



Shock and Vibration


Civil EngineeringAdvances in

Acoustics and VibrationAdvances in



Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation http://www.hindawi.com

Volume 2014

The Scientific World JournalHindawi Publishing Corporation http://www.hindawi.com Volume 2014

SensorsJournal of


Modelling & Simulation in EngineeringHindawi Publishing Corporation http://www.hindawi.com Volume 2014


Chemical EngineeringInternational Journal of Antennas and

Propagation




Navigation and Observation



DistributedSensor Networks


Documents

CellularAutomata-BasedParallelRandomNumber ...2 International Journal of Reconﬁgurable Computing produces an unrepeatable sequence of random numbers [17]. Both types of random number