Embed Size (px)
Citation preview
External Use
CENTURA® INTEGRATED
GATE STACK SYSTEM
Control. Down to the Last Atom.
Steve Ghanayem
Vice President and General Manager
Silicon Systems Group
2011 Semicon West Briefing
July 12, 2011
External Use
R 140
G 140
B 140
R 220
G 220
B 220
R 69
G 153
B 195
R 254
G 203
B 0
R 255
G 121
B 1
R 234
G 40
B 57
R 155
G 238
B 255
R 146
G 212
B 0
R 75
G 75
B 75
R 6
G 30
B 60
These presentations contain forward-looking statements, including those regarding
market outlooks; technology roadmaps; the proposed Varian merger; and Applied’s
market positions, products, growth opportunities, strategies and business outlooks.
These statements are subject to known and unknown risks and uncertainties that could
cause actual results to differ materially from those expressed or implied by such
statements, including but not limited to: the level of demand for Applied’s products, which
is subject to many factors, such as uncertain global economic and industry conditions,
demand for electronic products and semiconductors, government renewable energy
policies and incentives, and customers’ new technology and capacity requirements; the
satisfaction of conditions precedent to the proposed merger with Varian, including the
ability to secure regulatory approvals in a timely manner or at all; Applied’s ability to (i)
develop, deliver and support a broad range of products and expand its markets, (ii) align
its cost structure with business conditions, (iii) successfully execute its acquisition
strategy and realize synergies, (iv) obtain and protect intellectual property rights, and (v)
attract, motivate and retain key employees; and other risks described in Applied’s SEC
filings. All forward-looking statements are based on management’s estimates, projections
and assumptions as of July 12, 2011, and Applied undertakes no obligation to update any
forward-looking statements.
Safe Harbor
External Use
R 140
G 140
B 140
R 220
G 220
B 220
R 69
G 153
B 195
R 254
G 203
B 0
R 255
G 121
B 1
R 234
G 40
B 57
R 155
G 238
B 255
R 146
G 212
B 0
R 75
G 75
B 75
R 6
G 30
B 60
INTERCONNECT-ENABLING PRODUCTS
New Products Released at 2011 Semicon West
3
TRANSISTOR-ENABLING PRODUCTS
Producer® Black Diamond® 3
Producer ® Nanocure™ 3
Centura® DPN HD
Centura® Integrated Gate Stack
Endura® Versa™ XLR W PVD
Reflexion GT™ for Tungsten
Endura® HAR Cobalt PVD
Vantage® Vulcan™ RTP
External Use
R 140
G 140
B 140
R 220
G 220
B 220
R 69
G 153
B 195
R 254
G 203
B 0
R 255
G 121
B 1
R 234
G 40
B 57
R 155
G 238
B 255
R 146
G 212
B 0
R 75
G 75
B 75
R 6
G 30
B 60
Strained Silicon
High-k Metal Gate
FinFET
The Transistor Is Undergoing a Revolution
4
90nm 65nm 45nm 32nm 22nm
Unrelenting innovation in materials
and structure to continue scaling
External Use
R 140
G 140
B 140
R 220
G 220
B 220
R 69
G 153
B 195
R 254
G 203
B 0
R 255
G 121
B 1
R 234
G 40
B 57
R 155
G 238
B 255
R 146
G 212
B 0
R 75
G 75
B 75
R 6
G 30
B 60
Engineering the High-k Stack Layers
5
Source: Applied Materials Maydan Technology Center
Atomic-scale engineering
Material stability
Interface layer precision
Source Drain
2 nm
Si
Interface Layer
High-k
External Use
R 140
G 140
B 140
R 220
G 220
B 220
R 69
G 153
B 195
R 254
G 203
B 0
R 255
G 121
B 1
R 234
G 40
B 57
R 155
G 238
B 255
R 146
G 212
B 0
R 75
G 75
B 75
R 6
G 30
B 60
Increasing Complexity of Dielectric Gate Stack
6
Today 10 Years Ago
4X NUMBER
OF STEPS Nitridation
Interface
Layer
High-k
Dielectric
Post-Nitridation
Anneal
SiO2
TOTAL STACK STEPS
External Use
R 140
G 140
B 140
R 220
G 220
B 220
R 69
G 153
B 195
R 254
G 203
B 0
R 255
G 121
B 1
R 234
G 40
B 57
R 155
G 238
B 255
R 146
G 212
B 0
R 75
G 75
B 75
R 6
G 30
B 60
Applied Leads in Gate Stack Production Experience
7
Nitridation #1
Interface Layer Formation #1
Post-Nitridation Anneal #1 Applied’s
Market
Position
Centura DPN
Gate Stack System
PREVIOUS PROCESS SEQUENCE
External Use
R 140
G 140
B 140
R 220
G 220
B 220
R 69
G 153
B 195
R 254
G 203
B 0
R 255
G 121
B 1
R 234
G 40
B 57
R 155
G 238
B 255
R 146
G 212
B 0
R 75
G 75
B 75
R 6
G 30
B 60
'02 '03 '04 '05 '06 '07 '08 '09 '10 '11E
Applied Leads in the Gate Stack Market
8
Fiscal Year
~$1B cumulative
revenue
GATE STACK SYSTEM SHIPMENTS
External Use
R 140
G 140
B 140
R 220
G 220
B 220
R 69
G 153
B 195
R 254
G 203
B 0
R 255
G 121
B 1
R 234
G 40
B 57
R 155
G 238
B 255
R 146
G 212
B 0
R 75
G 75
B 75
R 6
G 30
B 60
Applied Leads in Gate Stack Production Experience
9
Nitridation #1
Interface Layer Formation #1
Post-Nitridation Anneal #1 Applied’s
Market
Position
Centura Integrated
Gate Stack System
NEW PROCESS SEQUENCE
Under Continuous Vacuum
Integrated ALD High-k new
External Use
R 140
G 140
B 140
R 220
G 220
B 220
R 69
G 153
B 195
R 254
G 203
B 0
R 255
G 121
B 1
R 234
G 40
B 57
R 155
G 238
B 255
R 146
G 212
B 0
R 75
G 75
B 75
R 6
G 30
B 60
10
Critical surface
preparation for ALD
Scales down to 3Å for
cutting-edge scaling
Interlayer Formation With Industry-Leading
Thermal Oxidation
External Use
R 140
G 140
B 140
R 220
G 220
B 220
R 69
G 153
B 195
R 254
G 203
B 0
R 255
G 121
B 1
R 234
G 40
B 57
R 155
G 238
B 255
R 146
G 212
B 0
R 75
G 75
B 75
R 6
G 30
B 60
11
Atomic Layer Deposition Process
First precursor adsorbed
as monolayer on surface
Second precursor
adsorbed as monolayer,
reacts with first layer
Reaction by-products
purged and steps repeated
to form each atomic layer
External Use
R 140
G 140
B 140
R 220
G 220
B 220
R 69
G 153
B 195
R 254
G 203
B 0
R 255
G 121
B 1
R 234
G 40
B 57
R 155
G 238
B 255
R 146
G 212
B 0
R 75
G 75
B 75
R 6
G 30
B 60
12
Nitridation “fixes” the
dose and stabilizes the
film
Anneal completes
dielectric stack
processing
Nitridation and Anneal Complete the Stack
External Use
R 140
G 140
B 140
R 220
G 220
B 220
R 69
G 153
B 195
R 254
G 203
B 0
R 255
G 121
B 1
R 234
G 40
B 57
R 155
G 238
B 255
R 146
G 212
B 0
R 75
G 75
B 75
R 6
G 30
B 60
Why Does Integration Under Vacuum Matter? …Because Interfaces Matter at 22nm
<15% ~50%
45nm
22nm
Interface to
Bulk Ratio
Si or SiGe
Interface Layer
High-k
Si or SiGe
High-k Interface Layer
13
External Use
R 140
G 140
B 140
R 220
G 220
B 220
R 69
G 153
B 195
R 254
G 203
B 0
R 255
G 121
B 1
R 234
G 40
B 57
R 155
G 238
B 255
R 146
G 212
B 0
R 75
G 75
B 75
R 6
G 30
B 60
Interfaces Matter Physically… …Air Exposure Causes Interfacial Contamination
Applied’s
Integrated Flow
Non-Integrated
Flow
Si or SiGe
High-k Interface Layer
No Air
Exposure
Air
Exposure Si or SiGe
High-k
Interface Layer
Uncontrolled
oxidation and
contamination
14
External Use
R 140
G 140
B 140
R 220
G 220
B 220
R 69
G 153
B 195
R 254
G 203
B 0
R 255
G 121
B 1
R 234
G 40
B 57
R 155
G 238
B 255
R 146
G 212
B 0
R 75
G 75
B 75
R 6
G 30
B 60
Interfaces Matter Even More Electrically… …Yielding Chip Performance Benefits
Threshold Voltage
Fully
Integrated
Gate Stack
Air Exposure
After
Interface Layer
Fully
Integrated
Gate Stack
Air Exposure
After Interface
Layer
Half-of-a-Generation
Performance Boost
Peak
Mobility
For Lower Power Devices
5 to 10% HIGHER PEAK
MOBILITY
20 to 40% TIGHTER
THRESHOLD
VOLTAGE
DISTRIBUTION
(1s)
15
External Use
R 140
G 140
B 140
R 220
G 220
B 220
R 69
G 153
B 195
R 254
G 203
B 0
R 255
G 121
B 1
R 234
G 40
B 57
R 155
G 238
B 255
R 146
G 212
B 0
R 75
G 75
B 75
R 6
G 30
B 60
The Gate Stack System for Atomic-Scale
Engineering
Centura platform is industry’s
benchmark for complex gate
dielectrics
Atomic-level control of interface
layer, high-k and nitridation
Integrated system enables
“nearly perfect” gate dielectrics
16
