CERDEC-06/27/2006 21.1

Digital Array Radar Technology Development

March 20, 2007

Dr. Barry S. PerlmanAssociate Director for TechnologyUS Army CERDECFt. Monmouth, NJ 07703

CERDEC-06/27/2006 21.2

Introduction

Development of Digital Array Radar

High-Power GaN MMICsIntegrated Low-Cost ModulesSiRF Integrated CircuitsAntenna Subpanel

Development

Summary/Conclusions

CERDEC-06/27/2006 21.3

DAR Program OverviewDAR Program Overview

Objective:Objective:Develop technology for a low-cost, air-cooled

active electronically scanned radar

Application:Application:Air defense, surveillance, counter mortar,

surveillance

Contributors:Contributors:Lockheed-Martin MS2CREE SemiconductorPurdue UniversitySierra Monolithics

CERDEC-06/27/2006 21.4

Development of DAR TechnologyDevelopment of DAR Technology

analog

digital to the element

digital

Proc

Analog ArchitectureAnalog Architecture•• Proven Approach Proven Approach •• High PerformanceHigh Performance•• Large Large DoDDoD InvestInvest•• New Devices in DevNew Devices in Dev

DACDAC

ADCADC

Up/Up/DnDnConvtrConvtr

DACDAC

ADCADC

Up/Up/DnDnConvtrConvtr

DACDAC

ADCADC

Up/Up/DnDnConvtrConvtr

DACDAC

ADCADC

Up/Up/DnDnConvtrConvtr Proc

Digital ArchitectureDigital Architecture•• Reduces RF DevicesReduces RF Devices•• Increases Op FlexibilityIncreases Op Flexibility•• May Reduce SystemMay Reduce System

•• CostCost•• WeightWeight•• ObsolescenceObsolescence

Proc

Analog ArchitectureAnalog Architecture•• Proven Approach Proven Approach •• High PerformanceHigh Performance•• Large Large DoDDoD InvestInvest•• New Devices in DevNew Devices in Dev

DACDAC

ADCADC

Up/Up/DnDnConvtrConvtr

DACDAC

ADCADC

Up/Up/DnDnConvtrConvtr

DACDAC

ADCADC

Up/Up/DnDnConvtrConvtr

DACDAC

ADCADC

Up/Up/DnDnConvtrConvtr

DACDAC

ADCADC

Up/Up/DnDnConvtrConvtr

DACDAC

ADCADC

Up/Up/DnDnConvtrConvtr

DACDAC

ADCADC

Up/Up/DnDnConvtrConvtr

DACDAC

ADCADC

Up/Up/DnDnConvtrConvtr

DACDAC

ADCADC

Up/Up/DnDnConvtrConvtr

DACDAC

ADCADC

Up/Up/DnDnConvtrConvtr

DACDAC

ADCADC

Up/Up/DnDnConvtrConvtr Proc

Digital ArchitectureDigital Architecture•• Reduces RF DevicesReduces RF Devices•• Increases Op FlexibilityIncreases Op Flexibility•• May Reduce SystemMay Reduce System

•• CostCost•• WeightWeight•• ObsolescenceObsolescence

Objective: Low Cost Air Cooled Phased Array Technology

Key is Leap to Digital Architecture and Maximal use of Commercial Technology

CERDEC-06/27/2006 21.5

WBG Front EndsVery High Power

High Temperature OperationVery High PAE

Minimization of Cooling SystemElimination of Circulator & Limiter

High Voltage Operation

WBG Technology is a Key enabler to achieve

an Affordable Radar

Panel TechnologyLow Cost SMT ManufacturingMulti-layer Board technology

Air CooledLow Cost Radiating ElementLight Weight Building Block

GaN MMICsMOCVD-grown GaN/AlGaN HEMT on SI 4H-SiC

Standard HEMT process

Thin film resistors, ~20 /sq.MIM capacitors, >200 V

100-µm-diameter via holes through SiC and GaN

Semi-insulating 4H-SiC

i-GaN

ResistorAu T-gate MIM Capacitor Au Airbridge

Substrate Via

4 mil

FoamStacked patch radiator

Buried RFGround

FR4 DC interconnect layers DC power & control traces

RadiationFront of Panel

Back of Panel

CrossSection

Stripline

Beamformer layer

Cooling Fins

Panel heat sink structure

SMT Packaged HPA/LNA/SW MMIC

Phaser MMIC

Ground Plane

*Another Layer Required for Logic Dist

Panel Cross Section

CERDEC-06/27/2006 21.6

GaNDig

Incorporation of SwitchLimiter/LNA on MMICPossible

Dig

GaAs - Based T/R Module

Enabling T/R Module TechnologyEnabling T/R Module Technology

SOI or SiGe Back End - GaN Front End

Low Cost/PowerSi Based Technology

•High Efficiency GaN HPA enables lower complexity, cost, and weight air cooled systems.•Higher Power GaN HPAs and robust GaN LNAs eliminate MMIC chip count & Cost.• Higher voltage operation of GaN enables a more efficient power system• High Temperature Operation

•High Efficiency GaN HPA enables lower complexity, cost, and weight air cooled systems.•Higher Power GaN HPAs and robust GaN LNAs eliminate MMIC chip count & Cost.• Higher voltage operation of GaN enables a more efficient power system• High Temperature Operation

Phase IIPhase I

CERDEC-06/27/2006 21.7

T/R MMIC Block DiagramT/R MMIC Block Diagram

6 Bit Phase Shifter

6 Bit Attenuator

T/R Switch

2 Stage HPA

Gain Block

2 Stage LNA

Antenna Port

Beamformer Port

Gain Block

CERDEC-06/27/2006 21.8

Mask Layout of GaN T/R MMICMask Layout of GaN T/R MMIC

CERDEC-06/27/2006 21.9

Low Cost Array Undergoing System Testing at LM

Four Transceiver Module Test Configuration during Bench Testing Four Transceiver Module Test Configuration during Bench Testing - Beamforming test capability for both Tx & Rx modes- Beamforming test capability for both Tx & Rx modes - Three independent - Three independent transceivertransceiver modules modules - One Module as common RF & computer interface- One Module as common RF & computer interface

Test Configuration Block DiagramTest Configuration Block Diagram

Xcvr#1

Xcvr#2

Xcvr#3

Xcvr#4 Test

Computer

RF Power Splitter/Combiner

Phase ReferenceDC Power

Test Equipment

Optical Data

Rx & Tx Combined RF

Tx & Rx Element RF

Data

& Ctrl

Reference & Power

RF Attenuator

Receive sensitivity & linearity goals achieved Transmitter power & linearity goals achieved Radar frequency control, transceive mode & BW verified EMI Immunity verified Phase locking works across multiple modules Optical data links operate @ 2.5 GB/sec Phase calibration works Distributed beamforming works Adequate radar phase noise floors achieved

Successful Successful PrototypePrototype

CERDEC-06/27/2006 21.10

Antenna SubPanel Antenna SubPanel DevelopmentDevelopment

April 2007 December 2007

Integration of IC’s into Subarray Panel

Picture of plastic

integrated IC.

Jan. 2007

New Array

Creation of fully integrated receive subpanel array

Characterization and Package of Full GaN

MMICMitigation of Active Impedance Versus Scan Angles

First T/R Array

June 2007

Creation of fully integrated Array (T/R)

CERDEC-06/27/2006 21.11

Silicon Digital Beam Former Back End

Multiple Receivers on a Single IC Possibly Utilizing Advanced A/D and Multicore

Processor Technologies

GaN MMIC Front Ends

Pushing the logical limits of integration on silicon with multiple receive channels on a single chip.

Demonstration of necessary Linearity in Standard Silicon Processes

Processor

Processor

Processor

Processor

A/D

A/D

A/D

A/D

Currently Antenna Array Only – RF out

Digital Array Integration

RF Out

CERDEC-06/27/2006 21.12

ConclusionConclusion:: Leverage/Share R&DLeverage/Share R&D ConclusionConclusion:: Leverage/Share R&DLeverage/Share R&D

Army advantages:

MPAR Offers ………

- Lowest cost S-band TRMs

- Economic production Qty’s

- Dual-use Cooperation

- Thru-the-sensor Weather :

Own the NIGHT ………

Own the WEATHER…..

MPAR advantages:

Army Offers …….

- GaN investment head start

- PAR experience @ S-band

- Large-scale sensor integration

- Multi-mission radars

Business cases

Synergy for the Future ……………………