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Worker Ownership• Chin-Hua Tsai CEO & Tester Programmer
B95902064 蔡青樺
• Ming-Hen Tsai COO& Interface ProgrammerB95902028 蔡明亨
• Chia-Hua Ho CTO & Interface ProgrammerB95902082 何家華
• Sang-Chang Hong CIO & Tester Programmer & SpeakpersonB95902004 洪三權
Outline
• Introduction
• Why SRAM Tester?Market? Promising Future?
• Technical Difficulty?
• Technique
• What is cf interface?
• How to detect errors?
Outline
• Introduction
• Why SRAM Tester?Why SRAM Tester?Market? Promising Future? Market? Promising Future?
• Technical Difficulty?
• Technique
• What is cf interface?
• How to detect errors?
SRAM
• Static Random Access Memory
• Doesn’t have to periodically refresh
• Used in Cache, SD card... .
i-Ntelligent
• S: Useful, Safer. For Business!
• W: Undeveloped User Pattern
• O: A new World! Blue Ocean!
• T: Need more capital.
DRAM Tester
• S: 力晶、茂德、南科、華邦 -> 20% Market Share RateDRAM need newest Tech !
• W: DRAM Winter...
• O: 12/16 經濟部紓困方案 Windows 7
• T: Big Monster: SamSung
Outline
• Introduction
• Why SRAM Tester?Market? Promising Future?
• Technical Difficulty?Technical Difficulty?
• Technique
• What is cf interface?
• How to detect errors?
• 1981 年,微軟創辦人比爾.蓋茲( Bill Gates ):「個人電腦記憶體需求將不會超過 640KB 」( Nobody would ever need more than 640KB of memory on theirpersonal computer )
Diffculty of Testing
• Ram become bigger and bigger
EXPONENTIALLYEXPONENTIALLY!
• Ram Fault become more complexcomplex
• However, required testing time is same.....
Outline
• Introduction
• Why SRAM Tester?Market? Promising Future?
• Technical Difficulty?
• Technique
• What is cf interface?What is cf interface?
• How to detect errors?
Introduction (by SPEC):
• CF/CF+ cards
• Vendor-independent specification
• CF Storage Cards provided the capability to easily transfer all types of digital information and software between a large variety of digital systems.
SPEC focus
• Card Physical
• Electrical Interface
• Metaformat(Information structure)
• Software Interface
• CompactFlash Adapters
Software Interface• The standard PC-AT disk I/O address
spaces 1F0h-1F7h, 3F6h-3F7h (primary) or 170h-177h, 376h-377h (secondary) with IRQ 14 (or other available IRQ).
• Any system decoded 16 byte I/O block using any available IRQ.
• Memory space.
Software Interface• Upon receipt of a Class 1 command, the
CompactFlash Storage Card sets BSY within 400 nsec.
• Upon receipt of a Class 2 command, the CompactFlash Storage Card sets BSY within 400 nsec, sets up the sector buffer for a write operation, sets DRQ within 700 μsec, and clears BSY within 400 nsec of setting DRQ.
• Upon receipt of a Class 3 command, the CompactFlash Storage Card sets BSY within 400 nsec, sets up the sector buffer for a write operation, sets DRQ within 20 msec (assuming no re-assignments), and clears BSY within 400 nsec of setting DRQ.
How to use it?• STB_I -STSCHG (PC Card I/O Mode)
Status Pin 46
• WE_I -Write Enable Pin 36
• ACK_O -Acknowledgment Pin 43
• DAT_O -Data Pin 31,30,29,28,27,49,48,47,6,5,4,3,2,23,22,21
Read
• --set modeSTB_I <= '1';WE_I <= '0';-- wait till the ackwait until rising_edge(ACK_O);read_from_the_controller <= DAT_O;
-- read dataportwait until rising_edge(CLK_I);
Write
• STB_I <= '1';WE_I <= '1';--set modeDAT_O <= data_to_controller;--set datawait until rising_edge(ACK_O);-- operate synchronouslywait until rising_edge(CLK_I);
Outline
• Introduction
• Why SRAM Tester?Market? Promising Future?
• Technical Difficulty?
• Technique
• What is cf interface?
• How to detect errors?How to detect errors?
How to detect Errors?
• Detection :All subtypes and All positions of subtype
• Category of Faults
• Detection Algorithm
What kinds of Errors?
• AF ( Address Fault )
• SAF ( Stuck-at Fault )
• TF ( Transition Fault )
• SOpF( Stuck-Open Fault )
• CF ( Coupling Faults )
• DRF( Data Retention Fault )
Address Fault• Case 1: No cell can be access with certain
address
• Case 2:An address can access multiple cells
• Case 3:A cell can be accessed with multiple addresses
• Case 4:Certain cell can be accessed with their own and other address
Coupling Fault
• 當 a-cell 改變, V-cell 就很衰的跟著變
• CFid e.g. <↑;1>
• CFst e.g. <0;1>
• CFin e.g. <0;x> (DRAM)
Data Retention Fault• A cell cannot retain it’s
logic value
• After a time delay Del(100ms < Del < 500ms)the cell will flip
• <1T/ 0> or <0T/1>
Detection Algorithm
• Scan ( Zero-One )
• CheckerBoard
• GALPAT
• Walking 1/0
• March
• Pseudo-Random Test
Scan( Zero-One )
Algorithm:
Step1:write 0 in all cellsStep2:read all cellsStep3:write 1 in all cells Step4:read all cells
Time Complexity:O(n)
Scan( Zero-One )
• Not all AFs will be detected
• SAFs will be detected when it can be guaranteed that the address decoder is correct
• Not all TFs are detected
• Not all CFs will be detected
Check-Board
Step 1: w1 in all cells-W w0 in all cells-BStep 2: read all cells Step 3: w0 in all cells-W w1 in all cells-BStep 4: read all cells
Check-Board
• Not all AFs will be detected
• SAFs will be detected when it can be guaranteed that the address decoder is correct
• Not all TFs are detected
• Not all CFs will be detected
GALPATAlgorithm
Step1: 將所有的 cells 填 0 (or 1), 並定一個base-cell 1(or 0 相對於其它 cells)
Step2: 將所有資料 read 出來, read 完其它的cell 一次就須馬上 read base-cell
Step3: 重覆 Step1,Step2, 將 base-cell 依序移到下一個位置 , 直到 base-cell 都出現過每個 cell
Step4: 將 base-cell 和其它的 cell 資料互換( 即 0->1,1->0), 重覆 Step1,Step2,Step3
Time Complexity:O( n^2)
GALPAT
• All AFs are detected and located
• All SAFs will be located
• All TFs are located
• All CFs are located
Walking 1/0Algorithm
Step1: 將所有的 cells 填 0 (or 1), 並定一個base-cell 1(or 0 相對於其它 cells)
Step2: 將所有資料 read 出來, base-cell 最後 才 read
Step3: 重覆 Step1,Step2, 將 base-cell 依序移到下一個位置 , 直到 base-cell 都出現過每個 cell
Step4: 將 base-cell 和其它的 cell 資料互換( 即 0->1,1->0), 重覆 Step1,Step2,Step3
Time Complexity:O( n^2)
Walking 1/0
• All AFs are detected and located
• All SAFs will be located
• All TFs are located
• All CFs are located
Sliding Diagonal
Algorithm
Step1: 把對角線當作 base-cells, 將 base-cells 填 1, 其餘 cells 填 0Step2: Read all cellsStep3: 把所有 base-cells 右移一格 , 回到Step2, 直到所有 base-cells 重回對角線Step4: 將 Step1 的 base-cells 改為填 0, 其餘 cells 填 1, 重覆 Step2~Step3
Sliding Diagonal
• Time complexity = O(n1.5)
• Not all AFs will be detected
• All SAFs are detected and located
• All TFs are detected and located
• Not all CFs will be detected
Butterfly
Algorithm
Step1: 自訂一個 base-cell, 將 base-cells 填 1, 其餘 cells 填0Step2: Read 在 base-cell 上下左右 第 1,2,4,8,...(2n) 位置的 cellsStep3: Base-cell 依序在 memory 中移動, 並執行 Step2, 直到 memory 中 每一個 cell 都當過 base-cellStep4: 將 Step1 的 base-cells 改為填 0, 其餘 cells 填 1, 重覆Step2~Step3 B: base-cell
N: 北方S: 南方E: 東方W: 西方X: 被重覆標記的 cell
March TestMAT+ Algorithm
↕(w0); ↑(r0,w1); ↓(r1, w0)
Step1: write 0 to all cellsStep2: for( begin to end) read 0 ; write 1;Step3: for( end to begin)
read 1; write 0;
Time Complexity:O( n)
March TestMATS : ↕(w0); ↕(r0,w1);↕(r1) MATS+: ↕(w0); ↑(r0,w1);↓(r1,w0) Marching 1/0 :↕(w0);↑(r0,w1,r1);↓(r1,w0,r0);↕(w1); ↑(r1,w0,r0);↓(r0, w1, r1); MATS++ : ↕ (w0);↑(r0,w1); ↓(r1,w0,r0); MARCH X : ↕(w0);↑(r0,w1); ↓(r1,w0); ↕(r0) MARCH C :↕(w0);↑(r0,w1);↑(r1,w0);↕(r0);↓(r0,w1);↓(r1,w0);↕(r0);
March Test
MARCH A : ↕(w0); ↑(r0,w1,w0,w1);↑(r1,w0,w1);↓(r1,w0,w1,w0);↓ (r0,w1,w0); MARCH Y : ↕(w0);↑(r0,w1,r1); ↓(r1,w0,r0); ↕(r0) MARCH B : ↕(w0);↑(r0,w1,r1,w0,r0,w1);↑(r1,w0,w1); ↓(r1,w0,w1,w0);↓(r0,w1,w0 )
March TestMarch Algorithm Test Lenth Fault
MATS 4n Some AFs, SAFs
MATS+ 5n AFs, SAFs
Marching 1/0 14n AFs, SAFs, TFs
MATS++ 6n AFs, SAFs, TFs
March X 6n AFs, SAFs, TFs, Some CFs
March C- 10n AFs, SAFs, TFs, Some CFs
March A 15n AFs, SAFs, TFs, Some CFs
March Y 8n AFs, SAFs, TFs, Some CFs
March B 17n AFs, SAFs, TFs, Some CFs
Pseudo-Random Test
• complexity: O(kn)
• k: # of iteration
• it can be designed to detect different types of fault.
Pseudo-Random Test (cont.)
e: escape probability
PD: probability of detecting fault
PD = 1 – e
we want to decrease the value of e
Pseudo-Random Test (cont.)
S0: state in which a 0 is stored
S1: state in which a 1 is stored
SD0: state in which SA0 fault is detected
(terminate state)
pSx(t): probability of being in state Sx at iteration t
pI1: probability of being in state 1 at first
Pseudo-Random Test (cont.)
A: a false bit
p0: prob of writing 0 to address A
p1: prob of writing 1 to address A
pr: prob of reading address A
Recusive relation:
pS0(t) = (1 – p1) * pS0(t-1) + p0 * pS1(t – 1)
pS1(t) = p1 * pS0(t-1) + (1- p0 – pr)* pS1(t-1)
pSD0(t) = pr*pS1(t-1) + pSD0(t-1)
Pseudo-Random Test (cont.)
We want to maximize pSD0(t)
pSD0(t) increase with iteration t
given a escape probability, can we find t?
(e ≥ 1 - pSD0(t))
Pseudo-Random Test (cont.)
What's the value of PSD0(t) for any t?
(so we can find t for every given e)
Pseudo-Random Test (cont.)
We can use generating function and solve the recursive relation. And blah blah...