CGS 3763 Operating Systems Concepts Spring 2013

Dan C. Marinescu

Office: HEC 304

Office hours: M-Wd 11:30 - 12:30 AM

Last time: Answers to student questions Page replacement algorithms

Today Page replacement algorithms Implementation of paging Hit and miss ratios Performance penalties

Next time Virtual memory

Reading assignments Chapters 8 and 9 of the textbook

Lecture 37 – Monday, April 15, 2013

Lecture 37 2

Lecture 37

Time intervals 1 2 3 4 5 6 7 8 9 10 11 12 Total number of page faults

Reference string 0 1 2 3 0 1 4 0 1 2 3 4Block 1 in PS - 0 0 0 3 3 3 4 4 4 4 4Block 2 in PS - - 1 1 1 0 0 0 0 0 2 2Block 3 in PS - - - 2 2 2 1 1 1 1 1 3Page OUT - - - 0 1 2 3 - - 0 1 -Page IN 0 1 2 3 0 1 4 - - 2 3 - 9

Block 1 in PS - 0 0 0 0 0 0 4 4 4 4 3Block 2 in PS - - 1 1 1 1 1 1 0 0 0 0Bloch 3 in PS - - - 2 2 2 2 2 2 1 1 1Block 4 in PS - - - - 3 3 3 3 3 3 2 2Page OUT - - - - - - 0 1 2 3 4 0Page IN 0 1 2 3 - - 4 0 1 2 3 4 10

FIFO Page replacement algorithm PS: Primary storage

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Lecture 37

Time intervals 1 2 3 4 5 6 7 8 9 10 11 12 Total number of page faults

Reference string 0 1 2 3 0 1 4 0 1 2 3 4Block 1 in PS - 0 0 0 0 0 0 0 0 0 2 3Block 2 in PS - - 1 1 1 1 1 1 1 1 1 1Block 3 in PS - - - 2 3 3 3 4 4 4 4 4Page OUT - - - 2 - - 3 - - 0 2 -Page IN 0 1 2 3 - - 4 - - 2 3 - 7

Block 1 in PS - 0 0 0 0 0 0 0 0 0 0 3Block 2 in PS - - 1 1 1 1 1 1 1 1 1 1Bloch 3 in PS - - - 2 2 2 2 2 2 2 2 2Block 4 in PS - - - - 3 3 3 4 4 4 4 4Page OUT - - - - - - 3 - - - 0 -Page IN 0 1 2 3 - - 4 - - - 3 - 6

OPTIMAL page replacement algorithm

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Lecture 37

Time intervals 1 2 3 4 5 6 7 8 9 10 11 12 Total number of page faults

Reference string 0 1 2 3 0 1 4 0 1 2 3 4Block 1 in PS - 0 0 0 0 0 0 0 0 0 0 3Block 2 in PS - - 1 1 2 1 1 1 1 1 1 1Block 3 in PS - - - 2 3 3 3 4 4 4 2 2Page OUT - - - 1 - 2 3 - - 4 0 1Page IN 0 1 2 3 - 1 4 - - 2 3 4 9

Block 1 in PS - 0 0 0 0 0 0 0 0 0 0 0Block 2 in PS - - 1 1 1 1 1 1 1 1 1 1Bloch 3 in PS - - - 2 2 2 2 4 2 2 2 2Block 4 in PS - - - - 3 3 3 3 4 4 4 3Page OUT - - - - - - 2 - - - 4 0Page IN 0 1 2 3 - - 4 - - - 3 4 7

LRU page replacement algorithm

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Lecture 37

LRU, OPTIMAL, MRU LRU looks only at history OPTIMAL “knows” not only the history but also the future. In some particular cases Most Recently Used Algorithm performs better than LRU. Example: primary device with 4 cells.

Reference string 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4

LRU F F F F F F F F F F F F F F F

MRU F F F F - - - - F - - - F - -

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Lecture 37

Time intervals 1 2 3 4 5 6 7 8 9 10 11 12 Total number of page faults

Reference string 0 1 2 3 0 1 4 0 1 2 3 4Block 1 in PS - 0 0 0 0 0 0 0 0 0 2 3Block 2 in PS - - 1 1 1 1 1 1 1 1 1 1Block 3 in PS - - - 2 3 3 3 4 4 4 4 4Page OUT - - - 2 - - 3 - - 0 2 -Page IN 0 1 2 3 - - 4 - - 2 3 - 7

Block 1 in PS - 0 0 0 0 0 0 0 0 0 0 3Block 2 in PS - - 1 1 1 1 1 1 1 1 1 1Bloch 3 in PS - - - 2 2 2 2 2 2 2 2 2Block 4 in PS - - - - 3 3 3 4 4 4 4 4Page OUT - - - - - - 3 - - - 0 -Page IN 0 1 2 3 - - 4 - - - 3 - 6

The OPTIMAL replacement policy keeps in the 3-blocks primary memory the same pages as it does in case of the 4-block primary memory.

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Lecture 37

Time intervals 1 2 3 4 5 6 7 8 9 10 11 12 Total number of page faults

Reference string 0 1 2 3 0 1 4 0 1 2 3 4Block 1 in PS - 0 0 0 3 3 3 4 4 4 4 4Block 2 in PS - - 1 1 1 0 0 0 0 0 2 2Block 3 in PS - - - 2 2 2 1 1 1 1 1 3Page OUT - - - 0 1 2 3 - - 0 1 -Page IN 0 1 2 3 0 1 4 - - 2 3 - 9

Block 1 in PS - 0 0 0 0 0 0 4 4 4 4 3Block 2 in PS - - 1 1 1 1 1 1 0 0 0 0Bloch 3 in PS - - - 2 2 2 2 2 2 1 1 1Block 4 in PS - - - - 3 3 3 3 3 3 2 2Page OUT - - - - - - 0 1 2 3 4 0Page IN 0 1 2 3 - - 4 0 1 2 3 4 10

The FIFO replacement policy does not keep in the 3-blocks primary memory the same pages as it does in case of the 4-block primary memory.

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Lecture 37

Time intervals 1 2 3 4 5 6 7 8 9 10 11 12 Total number of page faults

Reference string 0 1 2 3 0 1 4 0 1 2 3 4Block 1 in PS - 0 0 0 3 3 3 4 4 4 2 2Block 2 in PS - - 1 1 1 0 0 0 0 0 0 3Block 3 in PS - - - 2 2 2 1 1 1 1 1 1Page OUT - - - 0 1 2 3 - - 4 0 1Page IN 0 1 2 3 0 1 4 - - 2 3 4 10

Block 1 in PS - 0 0 0 0 0 0 0 0 0 0 0Block 2 in PS - - 1 1 1 1 1 1 1 1 1 1Bloch 3 in PS - - - 2 2 2 2 4 2 2 2 2Block 4 in PS - - - - 3 3 3 3 4 4 4 3Page OUT - - - - - - 2 - - - 4 0Page IN 0 1 2 3 - - 4 - - - 3 4 7

The LRU replacement policy keeps in the 3-blocks primary memory the same pages as it does in case of the 4-block primary memory.

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Lecture 37

Time intervals 1 2 3 4 5 6 7 8 9 10 11 12 Total number of page faults

Reference string 0 1 2 3 0 1 4 0 1 2 3 4Block 1 in PS - 0 0 0 3 3 3 4 4 4 2 2Block 2 in PS - - 1 1 1 0 0 0 0 0 0 3Block 3 in PS - - - 2 2 2 1 1 1 1 1 1Page OUT - - - 0 1 2 3 - - 4 0 1Page IN 0 1 2 3 0 1 4 - - 2 3 4 11

Block 1 in PS - 0 0 0 0 0 0 0 4 4 4 3Block 2 in PS - - 1 1 1 1 1 1 1 1 1 1Bloch 3 in PS - - - 2 2 2 2 4 0 0 0 0Block 4 in PS - - - - 3 3 3 3 3 3 2 2Page OUT - - - - - - 2 - - 3 4 0Page IN 0 1 2 3 - - 4 - - 2 3 4 8

The FIFO replacement policy does not keep in the 3-blocks primary memory the same pages as it does in case of the 4-block primary memory

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Implementation of Page Table

Page table is kept in main memory Page-table base register (PTBR) points to the page table Page-table length register (PRLR) indicates size of the page table In this scheme every data/instruction access requires two

memory accesses. One for the page table and one for the data/instruction.

To reduce the access time cache the most recently used frame addresses for pages. Use of a special fast-lookup hardware cache the translation look-aside buffers (TLBs) implemented as an associative memory.

Before a process A gets control of the CPU the PTBR register is loaded with the address of the page table of

process A the PRLR is loaded with the size of the page table of process A.

Lecture 37 11

Paging hardware

Lecture 37 12

Content addressable or associative memory

Allows parallel search.

Instead an address you search in parallel for a cell with a given contents.

Address translation (p, d) If p is in associative register, get frame # out Otherwise get frame # from page table in memory

Page # Frame #

Lecture 37 13

TLB hits and misses

Lecture 37 14

Lecture 37

Dynamic address translation

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Hit ratio and miss ratios

The primary memory is several orders of magnitude faster than the secondary memory.

If a virtual address is within a page P previously brought in the primary memory we have a “hit,” otherwise we have a “miss” and before we access the data we have to bring page P from the secondary storage in, a time consuming operation.

Hit ratio the fraction of the total number of memory references when we had a hit.

Miss ratio the fraction of the total number of memory references when we had a miss.

Lecture 37 16

Two-level memory system

To understand the effect of the hit/miss ratios we consider only a two level memory system P a faster and smaller primary memory S A slower and larger secondary memory.

The two levels could be:

P L1 cache and S main memory

P main memory and S disk

Lecture 37 17

Lecture 37

The performance of a two level memory

The latency Lp << LS

LP latency of the primary device e.g., 10 nsec for RAM

LS latency of the secondary device, e.g., 10 msec for disk

Hit ratio h the probability that a reference will be satisfied by the primary device. Average Latency (AS) AS = h x LP + (1-h) LS. Example:

LP = 10 nsec (primary device is main memory)

LS = 10 msec (secondary device is the disk) Hit ratio h= 0.90 AS= 0.9 x 10 + 0.1 x 10,000,000 = 1,000,000.009 nsec~ 1000

microseconds = 1 msec Hit ratio h= 0.99 AS= 0.99 x 10 + 0.01 x 10,000,000 = 100,000.0099 nsec~ 100

microseconds = 0.1 msec Hit ratio h= 0.999 AS= 0.999 x 10 + 0.001 x 10,000,000 = 10,000.0099 nsec~ 10

microseconds = 0.01 msec Hit ratio h= 0.9999 AS= 0.999 0x 10 + 0.001 x 10,000,000 = 1,009.99 nsec~ 1

microsecond

This considerable slowdown is due to the very large discrepancy (six orders of magnitude) between the primary and the secondary device.

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