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CH10 Input/OutputCH10 Input/Output
Data TransferData Transfer External DevicesExternal Devices I/O ModulesI/O Modules Programmed I/OProgrammed I/O Interrupt-Driven I/OInterrupt-Driven I/O Direct Memory Direct Memory
Access (DMA)Access (DMA) I/O Channels and I/O Channels and
ProcessorProcessor HI-TECH With Ankush Gera!
Data TransfersData Transfers
Synchronous ----- Usually occur when peripherals are located within the same computer as the CPU. Close proximity allows all state bits change at same time on a common clock.
Asynchronous ----- Do not require that the source and destination use the same system clock.
External DevicesExternal Devices
Human readableHuman readable Screen, printer, Screen, printer,
keyboardkeyboard
Machine readableMachine readable Monitoring and controlMonitoring and control
CommunicationCommunication ModemModem Network Interface Network Interface
Card (NIC)Card (NIC)
Input/Output ProblemsInput/Output Problems
Wide variety of peripheralsWide variety of peripherals Delivering different amounts of dataDelivering different amounts of data At different speedsAt different speeds In different formatsIn different formats
All slower than CPU and RAMAll slower than CPU and RAM Need I/O modulesNeed I/O modules
Peripherals Peripherals (Picture from Dr. Lee’s web site)(Picture from Dr. Lee’s web site)
Input/Output ModuleInput/Output Module
Interface to CPU and MemoryInterface to CPU and Memory Interface to one or more peripheralsInterface to one or more peripherals GENERIC MODEL OF I/O DIAGRAM GENERIC MODEL OF I/O DIAGRAM
Generic Model of an I/O ModuleGeneric Model of an I/O Module
I/O Module FunctionI/O Module Function
Control & TimingControl & Timing CPU CommunicationCPU Communication Device CommunicationDevice Communication Data BufferingData Buffering Error DetectionError Detection
I/O StepsI/O Steps
CPU checks I/O module device statusCPU checks I/O module device status I/O module returns statusI/O module returns status If ready, CPU requests data transferIf ready, CPU requests data transfer I/O module gets data from deviceI/O module gets data from device I/O module transfers data to CPUI/O module transfers data to CPU Variations for output, DMA, etc.Variations for output, DMA, etc.
I/O Module DiagramI/O Module Diagram
Data Register
Status/Control Register
ExternalDeviceInterfaceLogic
ExternalDeviceInterfaceLogic
InputOutputLogic
DataLines
AddressLines
DataLines
Data
Status
Control
Data
Status
Control
Systems Bus Interface External Device Interface
I/O Module DecisionsI/O Module Decisions
Hide or reveal device properties to CPUHide or reveal device properties to CPU Support multiple or single deviceSupport multiple or single device Control device functions or leave for CPUControl device functions or leave for CPU Also O/S decisionsAlso O/S decisions
Input Output TechniquesInput Output Techniques
ProgrammedProgrammed Interrupt drivenInterrupt driven Direct Memory Access (DMA)Direct Memory Access (DMA)
Three I/O TechniquesThree I/O Techniques
Programmed I/OProgrammed I/O
CPU has direct control over I/OCPU has direct control over I/O Sensing statusSensing status Read/write commandsRead/write commands Transferring dataTransferring data
CPU waits for I/O module to complete CPU waits for I/O module to complete operationoperation
Wastes CPU timeWastes CPU time
Programmed I/O - detailProgrammed I/O - detail
CPU requests I/O operationCPU requests I/O operation I/O module performs operationI/O module performs operation I/O module sets status bitsI/O module sets status bits CPU checks status bits periodicallyCPU checks status bits periodically I/O module does not inform CPU directlyI/O module does not inform CPU directly I/O module does not interrupt CPUI/O module does not interrupt CPU CPU may wait or come back laterCPU may wait or come back later
Addressing I/O DevicesAddressing I/O Devices
Under programmed I/O data transfer is very Under programmed I/O data transfer is very like memory access (CPU viewpoint)like memory access (CPU viewpoint)
Each device given unique identifierEach device given unique identifier CPU commands contain identifier (address)CPU commands contain identifier (address)
I/O MappingI/O Mapping
Memory mapped I/OMemory mapped I/O Devices and memory share an address spaceDevices and memory share an address space I/O looks just like memory read/writeI/O looks just like memory read/write No special commands for I/ONo special commands for I/O
Large selection of memory access commands Large selection of memory access commands availableavailable
Isolated I/OIsolated I/O Separate address spacesSeparate address spaces Need I/O or memory select linesNeed I/O or memory select lines
Interrupt Driven I/OInterrupt Driven I/O
Overcomes CPU waitingOvercomes CPU waiting No repeated CPU checking of deviceNo repeated CPU checking of device I/O module interrupts when readyI/O module interrupts when ready
Simple Interrupt Simple Interrupt ProcessingProcessing
Interrupt Driven I/OInterrupt Driven I/OBasic OperationBasic Operation
CPU issues read commandCPU issues read command I/O module gets data from peripheral I/O module gets data from peripheral
whilst CPU does other workwhilst CPU does other work I/O module interrupts CPUI/O module interrupts CPU CPU requests dataCPU requests data I/O module transfers dataI/O module transfers data
CPU ViewpointCPU Viewpoint
Issue read commandIssue read command Do other workDo other work Check for interrupt at end of each instruction Check for interrupt at end of each instruction
cyclecycle If interrupted:-If interrupted:-
Save context (registers)Save context (registers) Process interruptProcess interrupt
Fetch data & storeFetch data & store
See Operating Systems notesSee Operating Systems notes
Design Issues??Design Issues??
How do you identify the module issuing How do you identify the module issuing the interrupt?the interrupt?
How do you deal with multiple interrupts?How do you deal with multiple interrupts? i.e. an interrupt handler being interruptedi.e. an interrupt handler being interrupted
Identifying Interrupting Identifying Interrupting ModuleModule
Different line for each moduleDifferent line for each module PCPC Limits number of devicesLimits number of devices
Software pollSoftware poll CPU asks each module in turnCPU asks each module in turn SlowSlow
Multiple InterruptsMultiple Interrupts
Each interrupt line has a priorityEach interrupt line has a priority Higher priority lines can interrupt lower Higher priority lines can interrupt lower
priority linespriority lines If bus mastering only current master can If bus mastering only current master can
interruptinterrupt
Direct Memory AccessDirect Memory Access
Interrupt driven and Interrupt driven and programmed I/O programmed I/O require active CPU require active CPU interventionintervention Transfer rate is Transfer rate is
limitedlimited CPU is tied upCPU is tied up
DMA is the answerDMA is the answer
DMA FunctionDMA Function
Additional Module (hardware) on busAdditional Module (hardware) on bus DMA controller takes over from CPU for DMA controller takes over from CPU for
I/OI/O
DMA OperationDMA Operation
CPU tells DMA controller:-CPU tells DMA controller:- Read/WriteRead/Write Device addressDevice address Starting address of memory block for dataStarting address of memory block for data Amount of data to be transferredAmount of data to be transferred
CPU carries on with other workCPU carries on with other work DMA controller deals with transferDMA controller deals with transfer DMA controller sends interrupt when finishedDMA controller sends interrupt when finished
DMA Configurations (1)DMA Configurations (1)
Single Bus, Detached DMA controllerSingle Bus, Detached DMA controller Each transfer uses bus twiceEach transfer uses bus twice
I/O to DMA then DMA to memoryI/O to DMA then DMA to memory
CPU is suspended twiceCPU is suspended twice
CPUDMAController
I/ODevice
I/ODevice
Main Memory
DMA Configurations (2)DMA Configurations (2)
Single Bus, Integrated DMA controllerSingle Bus, Integrated DMA controller Controller may support >1 deviceController may support >1 device Each transfer uses bus onceEach transfer uses bus once
DMA to memoryDMA to memory
CPU is suspended onceCPU is suspended once
CPUDMAController
I/ODevice
I/ODevice
Main Memory
DMAController
I/ODevice
DMA Configurations (3)DMA Configurations (3)
Separate I/O BusSeparate I/O Bus Bus supports all DMA enabled devicesBus supports all DMA enabled devices Each transfer uses bus onceEach transfer uses bus once
DMA to memoryDMA to memory
CPU is suspended onceCPU is suspended once
CPU DMAController
I/ODevice
I/ODevice
Main Memory
I/ODevice
I/ODevice
I/O ChannelsI/O Channels
I/O devices getting more I/O devices getting more sophisticatedsophisticated e.g. 3D graphics cardse.g. 3D graphics cards
CPU instructs I/O CPU instructs I/O controller to do transfercontroller to do transfer
I/O controller does entire I/O controller does entire transfertransfer
Improves speedImproves speed Takes load off CPUTakes load off CPU Dedicated processor is Dedicated processor is
fasterfaster
It’s over…PhewwwIt’s over…Phewww But what did we learn?? But what did we learn??
Data TransferData Transfer External DevicesExternal Devices I/O ModulesI/O Modules Programmed I/OProgrammed I/O Interrupt-Driven I/OInterrupt-Driven I/O Direct Memory Direct Memory
Access (DMA)Access (DMA) I/O Channels and I/O Channels and
ProcessorProcessor
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