1

Memory Organization

• Memory Hierarchy

• Main Memory

MEMORY ORGANIZATION

2

Memory Organization

MEMORY HIERARCHY

Memory Hierarchy is to obtain the highest possibleaccess speed while minimizing the total cost of the memory system

Memory Hierarchy

Tape

Disk

I/Oprocessor

CPU

Mainmemory

Cache

Auxiliary memory

Registers

Register

Cache

Main Memory

Disk

Tape

CostSpeed

3

Memory Organization

MAIN MEMORY

RAM and ROM Chips

Typical RAM chip

Chip select 1Chip select 2

ReadWrite

7-bit address

CS1CS2RDWRAD 7

128 x 8RAM 8-bit data bus

CS1 CS2 RD WR0 0 x x0 1 x x1 0 0 01 0 0 11 0 1 x1 1 x x

Memory functionInhibitInhibitInhibitWriteReadInhibit

State of data busHigh-impedanceHigh-impedanceHigh-impedanceInput data to RAMOutput data from RAMHigh-impedance

Typical ROM chip

Chip select 1Chip select 2

9-bit address

CS1CS2

AD 9

512 x 8ROM 8-bit data bus

Main Memory

4

Memory Organization

MEMORY ADDRESS MAP

Memory Connection to CPU- RAM and ROM chips are connected to a CPU

through the data and address buses

- The low-order lines in the address bus select the byte within the chips and other lines in the address bus select a particular chip through its chip select inputs

Memory Address Map: Address space assignment to each memory chip

Main Memory

Example: Build a 1024x8 memory system of 512 bytes of RAM and 512 bytes of ROM using 128x8 RAM chips and 512x8 ROM chips

RAM 1RAM 2RAM 3RAM 4ROM

0000 - 007F0080 - 00FF0100 - 017F0180 - 01FF0200 - 03FF

ComponentHexa

Address

0 0 0 x x x x x x x0 0 1 x x x x x x x0 1 0 x x x x x x x0 1 1 x x x x x x x1 x x x x x x x x x

10 9 8 7 6 5 4 3 2 1

Address bus

0 - 127128 - 255256 - 383384 - 511512 - 1023

DecimalAddress

RAM 1

RAM 2

RAM 3

RAM 4

ROM

1024 x 8 memory

0:

127128

:255256

:383384

:511512

:1023

Address

5

Memory Organization

CONNECTION OF MEMORY TO CPUMain Memory

Decoder3 2 1 0

CS1CS2RDWRAD7

128 x 8RAM 1

CS1CS2RDWRAD7

128 x 8RAM 2

CS1CS2RDWRAD7

128 x 8RAM 3

CS1CS2RDWRAD7

128 x 8RAM 4

CS1CS2

512 x 8ROMAD9

Dat

aD

ata

Dat

aD

ata

Dat

a

WRRD9 8 7-11016-11

Address bus

Data busCPU

x x x x x x xx x x x x x xx x x x x x xx x x x x x x

7 6 5 4 3 2 1

Address bus

RAM 1RAM 2RAM 3RAM 4ROM

Component

1- 7

98 }

00001

100 00 11 01 1

9 8

x x x x x x x x x

6

Memory Organization

EXERCISESProblem 12-4: Extend the memory system of Fig. 12-4 to 4096 bytes of RAM and 4096 bytes of ROM. List the memory-address map and indicate what size decoders are needed.

RAM and ROM chips: 128 x 8 RAM, 512 x 8 ROMMemory system: 4096 bytes of RAM + 4096 bytes of ROM = 8192 bytesNumber of address lines:Number of needed RAM chips:Number of needed ROM chips:

⇒ decoder⇒ decoder

13 (8192 = 213)4096/128 = 324096/512 = 8

5 x 32 3 x 8

Address lines

Component Address range 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

RAM 1 0000 – 007F 0 0 0 0 0 0 0 0 0 x x x x x x x

: : : : : : : : : : : : : : : : : :

RAM 32 0F80 – 0FFF 0 0 0 0 1 1 1 1 1 x x x x x x x

ROM 1 1000 – 11FF 0 0 0 1 0 0 0 x x x x x x x x x

: : : : : : : : : : : : : : : : : :

ROM 8 1E00 – 1FFF 0 0 0 1 1 1 1 x x x x x x x x x