Challenges in the Design of Frequency Synthesizers Wireless Applications

8/3/2019 Challenges in the Design of Frequency Synthesizers Wireless Applications

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Challenges in the Design of Frequency Synthesizersfor Wireless Applications

Behzad RazaviIntegrated Circuits and Systems Laboratory

University of California,Los Angeles

AbstractThis paper describes the challenges in the design of fre-quency synthesizers used in wireless transceivers. Follow-ing a review of design issues and the effect of nonidealities,we present a number of synthesizer architectures alongwith their merits and drawbacks. We also describe thedifficulties in the design of some of the building blocks andconsider the role of synthesizers in emerging applications.

I. INTRODUCTIONThe limited bandwidth available to each user in wireless sys-tems mandates the precise definition of the carrier frequencyin both the transmit and receive paths. Frequency synthesizersgenerate periodic signals with accurately-defined frequencies,thus serving as an integral part of RF transceivers.Frequency synthesis continues to be a challenge, fundamen-tally because performing algebraic operations on frequenciesis more difficult than on other electrical quantities such as volt-ages or currents. The challenge has taken different directionsthroughout the years, motivating the invention of various ar-chitectures and circuit techniques [ l , 2, 31. As RF systemsincorporate higher levels of integration, frequency synthesiz-ers must deal with additional trade-offs resulting from require-ments such as monolithic implementation, low cost, minimalnumber of external components, and low power dissipation.This paper describes the challenges in the design of fre-quency synthesizers at both architecture and circuit level. InSection 11, we consider a typical synthesizer environment, re-view important performance parameters, and analyze the effectof nonidealities. In Section 111, we describe a number of syn-thesizer architectures along with their merits and drawbacks,especially with respect to monolithic integration. The designof building blocks is presented in Section IV and the role ofsynthesizers in some of the emerging applications is discussedin Section V.

11. GENERAL ONSIDERATIONSIn RF transceivers, a frequency synthesizer generates theperiodic signals required for both upconversion and down-conversion. As shown in the generic transceiver of Fig. 1,each mixer is driven by a local oscillator (LO) that is embed-ded in the synthesizer because the frequency must be definedwith very high accuracy -ranging from 0.1 ppm for GSM to

25 ppm for DECT. Moreover, the frequency must be varied in

0-7803-3669-0$5.000 997IEEE

Low-NoiseAmpllflerBand-PassFilter

PowerAmplifier

Fig. 1. Generic RF Transceiver.small precise steps, as depicted inTable 1for the mobile units

IS-54 824-849 MHz 869-894 MHz 30 kHzIS-95 824-849 MHz 869-894 MHz .25 MHzGSM 890-915 MHz 935-960 MHz 200 kHZ

Table 1. Frequency bands of cellular and cordless phone standards.of some cellular and cordless phone standards. Some of theconsiderations in such an environment are as follows.A. Frequency Accuracy

While the reference frequency of synthesizers is usually de-rived from a crystal oscillator to achieve a high accuracy, somefrequency error is inevitable, especially if temperature varia-tion and aging of crystals are taken into account. The effect ofthis error in translating the spectrum of a quadrature-modulatedsignal is to periodically rotate the signal constellation.The problem of frequency error further complicates the de-sign of RF transceivers. In high-precision applications such asGSM, some means of automatic frequency control (AFC) isnecessary. A possible approach is conceptually illustrated inFig. 2. Here, during the training sequence transmitted at thebeginning of the communication, the rotation frequency of theconstellation is measured in the digital domain and the resultis used to adjust the frequency of the crystal oscillator.B. Phase Noise

The local oscillator used in a synthesizer exhibits finitephase noise, corrupting both the upconverted and downcon-verted signals [4]. As shown in Fig. 3(a), the phase noiseof an interferer transmitted by a powerful, nearby station de-grades the detection of a weak signal even with a noiseless20.1 I

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Interferer

bwt e(I C..d

Fig. 5. Effect of synthesizer sideband in receiver.Fig. 2. AFC by feedback from DS P to oscillator

Interferer ii Lo

Signals-ig. 3. Effect of phase noise in (a) a transmitter, (b) a receiver.receiver. Moreover, if the receiver LO contains phase noise,then downconversion creates two overlapping noisy spectra,thus corrupting the wanted signal by the tail of the interferer[Fig. 3(b)]. This effect is called reciprocal mixing.Wireless standards impose stringent constraints on the close-in and far-out phase noise of synthesizers. For example, DECTsystems require that the output phase noise remain below themask shown in Fig. 4.

us, hile the received signal is accompanied by an interfererat wint. It can be seen that two important components appearafter downconversion: the desired channel convolved with theLO signal, and the interferer convolved with the sideband. Ifu i n t - w s = W I F , the downconverted interferer falls in thedesired channel.Typical systems require that all sidebands be approximately60 to 70 dB below the carrier, introducing a trade-off betweensideband suppression and switching speed in phase-lockedtopologies (Section 1II.A).D. witching Time

When the digital input of a synthesizer commands a changein the channel, the circuit requires a finite time to establish thenew output frequency. As the instantaneous value of the fre-quency changes, the upconverted signal in the transmitter leaksinto adjacent channels, often requiring that the power amplifierbe turned off until the synthesizer settles. For this reason, ap-plications such as frequency-hoppedspread-spectrum systemsdemand relatively fast switching.The trade-off between the switching speed and the sidebandmagnitude in phase-locked topologies calls for architecturalinnovationsso as to achieve faster channel selection.

-1 17dBcMZi : -131 dBCRlZ

Frequency Offset1.2 3.0 4.7(MW

Fig. 4.DECT phase noise mask.The issue of phase noise is perhaps the principal obstacle infully integrating synthesizers, especially in mainstream VLSItechnologies hat lack high-quality inductors. We return to thispoint in Section 1V.A.

C. SidebandsIn addition to phase noise, the output of a synthesizer maycontain unwanted sidebands (spurs), for example those gen-erated by the reference frequency of a phase-locked architec-ture (Section 1II.A). Shown in Fig. 5, the effect of sidebandsis particularly troublesome in the receive path. Suppose thesynthesizer output consists of a carrier at WLO and a spur at

E. Sensitivity to NoiseIn a transceiver environment, a frequency synthesizer issubjected to various sources of noise, from digital basebandcircuits to the transmitter power amplifier. The latter is partic-ularly troublesome because of the enormous transient currentsit draws from the supply and ground of the system. As de-picted in Fig. 6, despite various shielding techniques, the

-ol

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Fig. 6. VCO pulling due to PA noise.randomly-modulated output of the PA still corrupts the syn-thesized signal (e.g., through injection pulling). Thus, thesynthesizer, especially the voltage-controlled oscillator (VCO)must reject this type of disturbance. However, in practice it isdifficult to achieve adequate oscillator purity in the presenceI 3


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of the PA noise, unless the frequency planning ensures thatthe PA output spectrum is sufficiently far from the LO outputfrequency [ 5 ] .Another issue arises in portable systems in which the PA isperiodically turned on and off to save power. With the finiteoutput impedance of the battery, the large supply current of thePA may introduce several hundred millivolts of change in thesupply voltage [6],affecting the oscillator frequency and hencegiving rise to a transient in the synthesizer. A locally-generatedsupply devoted to the synthesizer alleviates this problem, butat the cost of complicating he design and increasing the powerdissipation.

111. SYNTHESIZERRCHITECTURESThe high accuracy required in the definition of the output

frequency has made phase-locked loops (PLLs) the dominantarchitecture for frequency synthesis. In this section, we de-scribe a number of synthesizer architectures.A. Integer-N Architecture

A PLL incorporating a programmable divider in the feed-back path can operate as a synthesizer. Shown in Fig. 7, theinteger-N architecture follows the voltage-controlled oscilla-

Fig. 7. Integer-N architecture.tor (VCO) with a pulse swallow divider so as to provide anoutput frequency step equal to the input reference, RE F [7].The divider consists of a dual-modulus prescaler, a swallowcounter, and a program counter. When the divider begins fromthe reset state, the prescaler divides by N + 1until the swallowcounter overflows, changing the modulus control signal. Theprescaler then divides by N until the program counter is full.Thus, for every (N + 1)s+ ( P- S)N = N P + S pulsesgenerated by the VCO, one pulse appears at the divider output.The simplicity of the integer-N architecture has made ita popular choice. In RF systems, the synthesizer has beentraditionally partitioned into three separate chips: the VCO; thedual-modulus prescaler; and the combination of the programcounter, the swallow counter, the phaselfrequency detector(PFD), and the loop low-pass filter (LPF). The VCO and theprescaler have typically been designed in silicon bipolar or

GaAs processes and the rest in CMOS technology. Note that abuffer must be interposed between the VCO and the prescalerto isolate the former from the kickback switching noise of thelatter [81.The integer-N architecture nevertheless suffers from a num-ber of drawbacks. First, since the reference frequency is equalto the channel spacing, and since stability considerations limitthe loop bandwidth to approximately f R E F /10,the switchingtime is quite long. Second, the loop cannot suppress the phasenoise of the VC O for frequency offsets greater than roughlyf R E F / 0,an especially serious issue in MOS implementationsbecause the upconverted l / f noise of the oscillator is quitesignificant for offsets as large as several hundred kilohertz.Third, the periodic disturbance of the VCO control line by thecharge pump creates sidebands at an offset equal to REF,requiring further limitation of the LPF bandwidth so that themagnitude of these sidebands is sufficiently small. Fourth, thedual-modulusprescaler may appear as the speed bottleneck ofthe system because its maximum operation frequency is abouthalf that of a simple divide-by-two circuit (Section 1V.B).B. Fractional-N Architecture

In integer-N synthesizers, the loop bandwidth is limitedbecause the input reference frequency must be equal to thechannel spacing, a property resulting from the fact that theoutput frequency changes by only integer multiples of REF.In fractional-N loops, on the other hand, the output frequencycan vary by afruction of REF, allowing the latter to be muchgreater than the channel spacing.Illustrated in Fig. 8, a fractional-N topology incorporates a"pulse remover," a circuit that blocks one of the input pulses

REF

tRemovevx5Y8

Fig. 8. Fractional-N architecture.upon assertion of theremove command [11. Since under lockedcondition the two frequencies presented to the phase detectormust be equal, the average output frequency of the pulse re-mover equals fREF and hence fout = M ~ R E F1/Tp,whereTp is the period with which the remove command is applied.In practice, the pulse remover is merged with the divider. Forexample, if the VCO output is divided by M for some timeand by M + 1 for some other time, the average divide ratiocan be set between M and M + 1 (Fig. 9) . With f R E F inthe range of tens of megahertz, the loop bandwidth can be aslarge as a few megahertz, yielding a fast lock transient as well

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fout

fModulus ControlFig. 9 . Use of a dual-modulus prescaler as pulse remover

as suppressing the VCO close-in phase noise.The principal drawback of fractional-N loops is the exis-tence of fractional spurs at the output [ I ] . Since each periodof f,,,,/M must be slightly shorter than the reference period,the phase difference between the reference and the feedbacksignal grows in every period until it falls to zero when onepulse is removed. Thus, the charge pump produces increas-ingly wider current pulses, periodically varying the oscillatorcontrol voltage and creating spurs at 1/Tp with respect to thecarrier.Fractional-N spurs can be suppressed by predicting thecharge packet generated by the charge pump and injectingan equal and opposite packet so as to minimize the disturbanceon the oscillator control line [13 . However, device mismatcheslimit the accuracy of this cancellation, often requiring externaladjustment [9].Another approach is to randomize the choice of the modu-lus in Fig. 8 such that the average divide ratio is still equalto the desired value but individual division factors occur onlyfor short periods of time. This technique in effect convertsthe systematic fractional sidebands to random noise. The ideacan be taken one step further by shaping the resulting noisespectrum such that most of its energy appears at large offsetfrequencies [IO]. Thus, noise in the vicinity of the divided car-rier frequency is small and noise at higher offsets is suppressedby the low-pass filter following the PFD.The noise shaping function can be realized by means ofa XA modulator [IO]. Depicted in Fig. 10, the modulatorgenerates a binary stream representing a well-defined average

rout

I A Modulator IFig. 10.Use of a ZA modulator to shape the noise due to modulus randomiza-tion.value accompanied by quantization noise. The spectrum ofthe phase noise in the feedback signal can then be expressedas

where &(f) s the (voltage) noise-shaping function providedby the modulator.

While relatively complex, noise-shaping fractional-N loopsare an interesting alternative whose properties merit furtherstudy. In particular, the stability and lock behavior and theexistence of tones in the output of the modulator need to beinvestigated.C. Dual-Lo op Architectures

The relationship between the channel spacing and the ref-erence frequency of integer-N synthesizers can be altered byemploying two or more loops. A simple approach to generat-ing fine frequency steps is to ad d a variable, low frequency toa fixed, high frequency. Depicted in Fig. 11, this techniqueutilizes PLLl to generate the carrier frequency, and PLL2 to

REF1

: t I : i \

t i

Channel~ P L L ~ SelectFig.11. Dual-loop architecture.produce increments equal to REF^. Varying the divide ratioof PLL2 therefore yields the fine steps required in the outputfrequency. The addition of the two frequencies is performedby a single-sideband (SSB) mixer.The principal advantageof this architecture over single-loop

integer-N topologies is that the loop bandwidth of PLLl canbe chosen to be large so as to reduce the close-in phase noise ofVCO1. The phase noise of VC02 is much lower because of thetrade-off with the center frequency [11, 41. The major draw-back is that accurate single-sideband mixing requires precisegeneration of quadrature phases in both PLLs, low harmonicdistortion in either VCOl or VCO2, and sufficiently small mis-matches in the two mixers [12]. Thus, it is difficult to ensurethat sidebands resulting from mismatches and nonlinearitiesare 60 to 70 dB below the carrier.The above issues can be alleviated as shown in Fig. 12 .Here, the SS B mixer is designed to subtract the two frequenciesand it is placed inside the feedback loop. Furthermore, f2 hasa large offset: f2 = fo + kfREF2, where fo is a fixed value,e.g., 25 MHz. Thus , fout = N ~ R E F IS O + ~ ~ R E F Z .he keypoint here is that the sidebands resulting from mismatches andharmonics are at relatively large frequency offsets and henceare suppressed by the loop low-pass filter. In addition, if thesidebands at the output of the synthesizer fall outside of theband of interest, their magnitude is allowed to be higher thanin-band spurs because the transceiver front-end duplexer (orband-pass filter) attenuates out-of-band interferers, making theeffect illustrated in Fig. 5less significant.

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f REFZ vco,

ChannelSelectFig. 12 . Dual-loop architecture with SS B mixer in on e loop.

Another dual-loop architecture is depicted in Fig. 13. TwoPLLs generate outputs at f i = fo + C ~ R E F I and f2 = f~ -REF1 REF2P P

fo....iAkL i e f 2....Fig. 13 . Dual-loop architecture using vernier effec t.

k f ~ ~ ~ 2 ,espectively. These outputs are mixed and the resultis high-pass filtered to yield: foul = 2 f o + k ( f ~ ~ ~ 1R REF^).Thus, f o u t can increment in steps equal to ~ R E F I R E F 2while f i and f 2 increment in much greater steps, allowing arelatively large loop bandwidth in both PLLs. For example, iff~ = 450 MHz, REF^ = 1 MHz, and REF^ = 1.2 MHz, wehave fou t = 900MHz - C x 200 kHz. Another advantage ofthis architecture is that the dual-modulus divider required ineach loop operates at approximately half the output frequency.The primary difficulty in the architecture of Fig. 13 is thatthe mixer generates cross products of the harmonics of f1 andf2, restricting the choice of fo, REF^, and REF^ if the spursare to fall outside the desired band. In some cases, a solutionmay not even exist.In the dual-loop configurations considered above, the twooscillators may pull each other through the parasitic pathsin the mixer. For this reason, each oscillator must be followedby a buffer with high reverse isolation.D. Direct Digital Synthesis

Direct sigital synthesis (DDS) produces the signal in thedigital domain and utilizes digital-to-analog conversion and

filtering to reconstruct the waveform in the analog domain.Illustrated in Fig. 14, DDS employs an accumulator, a look-...........................

P : 1 1.......... ..............,0

Fig. 14. Direct digital synthe sis.up read-only memory (ROM), a digital-to-analog converter(DAC), and a low-pass filter [2]. The accumulator generates adigital ramp that is mapped to a sinusoid by the ROM. As theincrement value, P , increases, so does the rate at which theaccumulator overflows, thus yielding a shorter period for theoutput sinusoid.

DDS offers a number of advantages over phase-locked ar-chitectures: much less phase noise, fine frequency steps, muchfaster channel switching, and provision for direct modulation.However, speed issues have limited the use of DDS in the RFrange. Since the clock frequency is typically about three tofour times the maximum output frequency so as to relax theLPF rejection requirements, for a 900-MHz signal, the circuitof Fig. 14 would need to be clocked at a rate between 2.7GHz and 3.6 GHz. In todays VLSI technologies, it is difficultto perform the operations shown in Fig. 14at such speeds,especially if power dissipation is critical. Even if the digitalsection can be realized with acceptable complexity and powerdrain, the DAC remains the speed bottleneck. The trade-offsamong settling time, harmonic distortion, spurious response,and power dissipation of the DA C prevent its use in the RFrange.The low phase noise and fast switching of DDS make itattractive for use as the low-frequency generator in the dual-loop architectures of Figs. 11 and 12, replacing the slowerPLL (Fig. 15).In such an approach, however, two issues must

Fig. 15 . Combination of phase-lockingand DDS.be considered. First, if the high-frequency VCO is on the samechip as the DDS circuit, then the substrate and supply noiseproduced by the accumulator and the ROM may significantlycorrupt the VCOoutput. Second, if the dual-loop architecturesrequire a wide tuning range in the low-frequency generator,e.g., a factor of two to one, then the DDS output LPF must have

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a tunable cut-off frequency to suppress the aliased componentswhile maintaining a constant fundamental amplitude.IV. BUILDING LOCKS

A. VCOsVCOs are perhaps the most critical building block of RFsynthesizers. Difficult issues such asphase noise, tuning range,power dissipation, and sensitivity to supply and substrate noisehave motivated a great deal of research on VCO design.The stringent phase noise requirements in wireless systemsusually lead to three general rules originating from Leesonsequation [11,4]:

(2 )1 AW 2 Pnoise4Q2 W O PcarrierRelative Phase Noise = -( -) -where Q is the open-loop quality factor, Aw is the frequencyoffset, W O s the center frequency, and Pnoise is the spectraldensity of each source of noise. The three rules are: (1)use high-Q passive resonators; (2) minimize the number ofactive (and lossy passive) devices in the oscillation path; (3 )maximize the oscillation swing (PCarcier).hrough these rules,we can understand the challenges in VCO design.Rules number 1 and 2 have made topologies such as ringoscillators and relaxation oscillators less attractive for RF ap-plications. Despite their wide tuning range, these circuitsexhibit an open-loop Q in the vicinity of unity [4] while con-taining many noisy devices in the oscillation path. Thus, RFoscillators have predominantly incorporated surface acousticwave (SAW) devices, transmission lines, or LC tanks, alongwith one or two transistors.

In monolithic implementations,on the other hand, inductorsand varactors suffer from a low Q. As shown in Fig. 16, theQ of inductors is limited by three mechanisms: metal line

substrate substrate &

substrate V/Fig. 16. Loss mechanisms in monolithic inductors.

resistivity, capacitive coupling to the substrate, and magneticcoupling to the substrate. Manifesting themselves at highfrequencies, the last two effects are much more pronounced insilicon technologies with heavily-doped substrates, yielding ageneral variation of Q as plotted in Fig. 17.The effect of metal line resistance can be lowered by re-moving the first few internal turns of a spiral inductor becausethe small area and large (negative) mutual coupling of these

Fig. 17

A

Degradationof Q due to substrate loss.turns make their contribution to the total inductance ncgligi-blc. Also, thc substrate loss due to capacitive coupling can bereduced by placing under the spiral a conductive plate (e.g., n-well) that is periodically broken in the direction perpendicularto the current flow (Fig. 18). Unfortunately, the magnetically-

ConductivPlate

Fig. 18 . Suppressionof capacitively-coupledcurrents in the substrate,induced current would still flow through the substrate. The Qof inductors in todays mainstream bulk CMOS technologiesrarely exceeds five.The series resistance of varactors is also of concern. InCMOS technology, grounded and floating diodes can be real-ized as shown in Fig. 19, with significant resistance arisingfrom the p-substrate or the n-well. The resistance can be low-

4-H- U

p-substrate p-substrateFig. 19. Varactor structures in CMOS technology,

ered by the strapping method depicted in Fig. 20[131.Another important phenomenon in CMOS oscillators is theupconversion of l / f noise. Since in typical submicron CMOSdevices the l / f noise corner may be as high as 1 MHz, oscil-lator phase noise at small frequency offsets is dominated bythis type of noise.LC VCOs also suffer from a trade-off between the phasenoise and the tuning range, especially at low supply voltages.To lower the relative phase noise at a given power dissipation,it is desirable to increase the value of the inductor. This isbecause the equivalent parallel resistance of an inductor canbe expressed as Rp M ( L w ) ~ / R s ,here Rs is the seriesresistance; although L and Rs scale proportionally, Rp stillincreases linearly with L [131. The upper bound on the valueof L is of course determined by its self-resonance frequency,f s ~ .onsidering the substantial parasitic capacitance of theinductor and the transistor(s), we note that the variable compo-nent of the tank capacitance is quite small, e.g., about 30% n[131. At low supply voltages and with large oscillation voltageswings, this component cannot be varied by more than roughly50%, giving a tuning range of approximately 10%.Even with

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Cathode1 1AnodeFig. 20 . Strapping n-we ll to reducethe series resistance.the aid of additional circuit techniques [131, the tuning rangeis still quite limited.The narrow tuning range of LC oscillators has been viewedas both a merit and a drawback! On the one hand, sincethe VCO gain is relatively low, the effect of noise on thecontrol line is small. On the other hand, additional means ofadjusting the frequency are required to ensure operation in theband of interest despite manufacturing variations. In many RFsystems, this is accomplished by adding a small, mechanicallytrimmable capacitor in parallel with the varactor, but the tuningrange must still be wide enough to cover variations with thetemperature.The second rule mentioned above makes one-transistor os-cillator topologies such as the Colpitts configuration of Fig.21(a) attractive. In this circuit, the voltage divider consisting

FrequencyC2 Control- - - FrequencyControl

Frequency

ControlwdFig. 21. (a) Colpitts oscillator, (b ) use of source follower for impedancetranformation, (c ) differential negative-G , oscillator.of C1 and Cz transforms the resistance seen looking into thesource of M I [m / (gml + g m b l ) ] to a higher value, therebyminimizing resistive loading of the tank. As shown in Fig.21(b), this transformation can alternatively be performed bymeans of a source follower, leading to a negative-G, oscilla-tor. With on-chip inductors, a fully differential configuration

[Fig. 21(c)] proves extremely useful in driving mixers andsingle-sideband modulators.The relatively high phase noise and limited tuning range ofmonolithic LC oscillators appear to be difficult problems, call-ing for solutions through synthesizer architecture innovations.B. Frequency Divider s

Single-modulus and multi-modulus dividers are widely usedin RF transceivers. Simple divide-by-two circuits can generatequadrature phases that are required in VQ upconversion anddownconversion. For this purpose, a master-slave D-flipflopemploying a current-steering latch can be used (Fig. 22).Proper sizing of M,-M4 yields speeds in excess of 2 GHz inq-a?JJ

CK

(b)Fig. 2 2 . (a) Divide-by-two circuit, (b) implementation of each latch.

0.6-pm CMOS technology even if each latch is loaded with anoutput differential pair. Simulations and experiments indicatethat this configuration achieves a higher speed than dividersincorporating the true-single-phase-clocking technique [141.An intriguing divide-by-two circuit is the analog dividerproposed by Miller [15]. Illustrated in Fig. 23, the circuitincorporates a mixer and a low-pass filter with a cut-off fre-mfoin-Fig. 23. Miller divider.

quency equal to f in /2. Upon multiplication of the input andoutput signals, the mixer generates components at f i n + oU tand f in - o u t , with the former being suppressed by the filter.Thus, f in - out = fout and hence fov t = f in /2 . Owing tothe simplicity of the feedback loop, this topology operates atspeeds even greater than half of the f~ of the transistors [16].The Miller divider, however, is known to suffer from sub-stantial phase noise. A possible explanation is as follows.Suppose a noise component at fi n /2 +Af appears in the feed-20.1.7

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back path. Multiplication of this component by the input andlow-pass filtering yield the image frequency, f in /2 - Af, tthe output. Now if this component goes around the loop, theoriginal frequency, f i n /2 + Af , is generated. In other words,the loop circulates noise components at f in /2 f f with neg-ligible attenuation if Af s small, a behavior similar to that ofring oscillators.Dual-modulus dividers entail more design difficulties thandivide-by-two circuits. As shown in the +2 /3 circuit of Fig.24, the critical signal path consists of the gate G I and the

CKFig. 24. Dual-modulus 213 divider.

input stage of FF2. Furthermore, the output of PF2 mustdrive the input capacitance of both GI and F F l . For thesereasons, dual-modulus dividers used in frequency synthesizerstypically exhibit a maximum speed roughly half that of +2circuits.The limited speed of CMOS dual-modulus dividers presentan important challenge to the design of multi-gigahertz syn-thesizers, demanding new circuit and architecture techniques.V. EMERGINGPPLICATIONS

A. Dual-Stand ard TransceiversThe existence of various wireless standards within the USand around the world has created a demand for transceivers thatcan operate in more than one mode. In the simplest case, twodifferent receive and transmit frequency bands must be sup-ported while other properties of the system remain unchanged.

For example, GSM and DCS 1800 differ by primarily their fre-quency bands. In a more sophisticated scenario, the transceivercan operate with two vastly different standards, e.g., IS-54 andEven in the simple case of GSM and DCS1800, the fre-quency planning of the transceiver is quite difficult. The needfor two receive bands and two transmit bands raises a num-ber of questions: How many VCOs and synthesizer loops arerequired? How should the frequencies be chosen so that har-monics and intermodulation products fall out of the band ofinterest or below an acceptably low level? How many stagesof upconversion and downconversion are needed?Answering these questions requires that the receive and

transmit paths be designed in conjunction with the frequencysynthesizer(s).

IS-95.

B. Multi-Gigahertz TransceiversThe availability of spectrum at higher frequencies, e.g.,around 2.4 GHz and 5.5 GHz, has heightened the interestin many new standards for applications such as wireless localarea networks (WLANs). An example is the high-performance

radio local area network (HIPERLAN), which is expected tooperate in the vicinity of 5.2 GHz.While initial studies indicate that sub-half-micron CMOStechnologies may provide a reasonable performance in the re-ceive and transmit paths of a HIPERLAN system, the problemof frequency synthesis persists. The substrate loss at 5 GHzmay limit the Q of inductors to less than unity. Furthermore,even simple divide-by-two circuits may not operate reliably atthese frequencies. In this case, too, the transceiver architec-ture and frequency planning must be chosen according to thefrequency synthesis capabilities of the technology.

REFERENCES[11 W. L. Rhode, Digital PLL Frequency Synthesizers, The-ory and Design, Englewood Cliffs, NJ: Prentice-Hall,1983.[2] J. A . Crawford, Frequency Synthesizer Design Hand-

book, Artech House, 1994.[3] W. F. Egan, Frequency Synthesis by Phase Lock, NewYork, Wiley & Sons, 1981.[4] B. Razavi, A Study of Phase Noise in CMOS Oscilla-tors, IEEE J. of Solid-state Circuits, vol. 31, pp. 331-343, March 1996.[5 ] T. D. Stetzler et al, A 2.7-4.5 V Single Chip GSMTransceiver RF Integtrated Circuit, IEEE J. of Solid-State C ircuits, vol. 30, pp. 1421-1429, Dec. 1995.[6] R. Mohindra, Isolator for DECT Open-Loop Modula-tor, RF Design, pp. 30-42, Jan. 1996.[7] V. Manassewitch,Frequency Synthesizer T heory and De-sign, New York: Wiley & Sons, 1976.

[8] T. Aytur and B. Razavi, A 2-GHz 6-mW BiCMOS Fre-quency Synthesizer,ISSCC Dig. Tech. Papers, pp. 264-265, Feb. 1995.[9] Philips Semiconductor, RFNireless CommunicationData Handbook, 1996.[lo] T. A. D. Riley, M. A. Copeland, and T. A. Kwas-niewskiy, Sigma-Delta Modulation in Fractional-N Fre-quency Synthesis,IEEE J. of Solid-state Circuits, vol.28, pp. 553-559, May 1993.

[l I ] D. B. Leeson, A Simple Model of Feedback OscillatorNoise Spectrum, Proc. IEEE, pp. 329-330, Feb. 1966.[121 B. Razavi, Fundamentals of RF Electronics, Prentice-Hall, 1997.[131 B. Razavi, A 1.8-GHz Voltage-Controlled Oscillator,to be presented at ISSCC, Feb. 1997, San Fransisco.[I43 J. Yuan and C. Svensson, High-speed CMOS CircuitTechnique, IEEE J . of Solid-State Circuits, vol. 24, pp.[151 R. L. Miller, Fractional Frequency Generators UtilizingRegenerative Modulation, Proc. IRE, vol. 27, pp, 446-

457, July 1939.[I61 M. Kuriso et al, A Si Bipolar 28 GHz Dynamic Fre-quency Divider, ISSCC Dig. Tech. Papers, pp. 92-93,Feb. 1992.

62-69, 1989.

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Challenges in the Design of Frequency Synthesizers Wireless Applications