chap4-FET

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CHAPTER 4 :JFET

Junction Field Effect Transistor

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Introduction (FET)

Field-effect transistor (FET) are importantdevices such as BJTs

Also used as amplifier and logic switches

Types of FET:

MOSFET (metal-oxide-semiconductor field-effecttransistor)

Depletion-mode MOSFET

JFET (junction field-effect transistor)

What is the difference between JFET andMOSFET?

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Current-controlled amplifiers

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Voltage-controlled amplifiers

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High input impedance (M)(Linear AC amplifier system)

Temperaturestable than BJT

Smaller than BJT

Can be fabricated with fewer processing

BJT is bipolar conduction both hole and

electron FET is unipolar uses only one type of current

carrier

Less noise compare to BJT

Usually use as logic switch

Introduction.. (Advantages ofFET)

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Disadvantages of FET

Easy to damage compare to BJT

???

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Junction field-effect transistor (JFET)

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There are 2 types of JFET

n-channel JFET

p-channel JFET

Three Terminal

Drain D (Saliran)

Gate -G (Get)

Source S (Punca)

Junction field-effect transistor..

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N channel JFET:

Major structure is n-type material (channel)between embedded p-type materialto form 2 p-

n junction. In the normal operation of an n-channel device,

the Drain (D) is positive with respect to theSource (S). Current flows into the Drain (D),through the channel, and out of the Source (S)

Because the resistance of the channel dependson the gate-to-source voltage (VGS), the draincurrent (ID) is controlled by that voltage

N-channel JFET

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N-channel JFET..

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P channel JFET:

Major structure is p-type material(channel) between embedded n-type

materialto form 2 p-n junction.

Current flow : from Source (S) to Drain(D)

Holes injected to Source (S) through p-type channel and flowed to Drain (D)

P-channel JFET

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P-channel JFET..

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Water analogy for the JFET controlmechanism

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JFET Characteristic Curve

To start, suppose VGS=0

Then, when VDS is increased, ID increases.Therefore, ID is proportional to VDS for small

values of VDS For larger value of VDS, as VDS increases, the

depletion layer become wider, causing theresistance of channel increases.

After the pinch-off voltage (Vp) is reached, the IDbecomes nearly constant (called as IDmaximum,IDSS-Drain to Source current with Gate Shorted)

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ID versus VDS for VGS = 0 V.


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JFET for VGS = 0 V and 0

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Pinch-off (VGS = 0 V, VDS= VP).

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Application of a negative voltage tothe gate of a JFET.

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JFET Characteristic Curve..

For negative values of VGS, the gate-to-channeljunction is reverse biased even with VDS=0

Thus, the initial channel resistance is higher (in which

the initial slope of the curves is smaller for values ofVGS closer to the pinch-off voltage (VP)

The resistance value is under the control of VGS If VGS is less than pinch-off voltage, the resistance

becomes an open-circuit ;therefore the device is incutoff (VGS=VGS(off) )

The region where ID constant The saturation/pinch-off region

The region where ID depends on VDS is called thelinear/triode/ohmic region

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n-Channel JFET characteristics curve withIDSS = 8 mA and VP= -4 V.


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p-Channel JFET

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p-Channel JFET characteristics with IDSS= 6mA and VP= +6 V.

Ch t i ti f h l

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Characteristics for n-channelJFET

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P

+

+

+

Characteristics for p-channelJFET

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Operation of n-channel JFET

JFET is biased with two voltage sources: VDD VGG

VDD generate voltage bias between Drain (D)and Source (S) VDS

VDD causes drain current, ID flows from Drain(D) to Source (S)

VGG generate voltage bias between Gate (G)and Source (S) with negative polarity source isconnected to the Gate Junction (G) reverse-biases the gate; therefore gate current, IG = 0.

VGG is to produce depletion region in N channelso that it can control the amount of draincurrent, ID that flows through the channel

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Transfer Characteristics

The input-output transfer characteristic ofthe JFET is not as straight forward as it isfor the BJT. In BJT:

IC= IB

which is defined as the relationshipbetween IB (input current) and IC (outputcurrent).

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Transfer Characteristics..

In JFET, the relationship between VGS (inputvoltage) and ID (output current) is used todefine the transfer characteristics. It is calledas Shockleys Equation:

The relationship is more complicated (and notlinear)As a result, FETs are often referred to asquare law devices

2

GS

D DSS

P

VI = I 1 -

V

VP=VGS (OFF)

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Defined by Shockleys equation:

Relationship between ID and VGS.

Obtaining transfer characteristic curve axis

point from Shockley: When VGS = 0 V, ID = IDSS When VGS = VGS(off) or Vp, ID = 0 mA

)(

2

)(

1offGSP

offGS

GSDSSD VV

V

VII


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JFET Transfer Characteristic Curve JFET Characteristic Curve

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Exercise 1

DGS P

DSS

IV = V 1 -

I

2GS

D DSS

PVI = I 1 -V

VGS ID

0 IDSS

0.3Vp IDSS

/2

0.5Vp IDSS/4

Vp 0 mA

Sketch the transfer defined by

IDSS = 12 mA dan VGS(off) = - 6

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Exercise 1

DGS P

DSS

IV = V 1 -

I

Sketch the transfer defined by IDSS = 12 mA danVGS(off) = Vp= - 6

IDSS

IDSS

/2

IDSS/4

2GS

D DSS

P

VI = I 1 -

VVGS =0.3VP

VGS =0.5VP

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Answer 1

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Exercise 2

DGS P

DSS

IV = V 1 -

I

2GS

D DSS

PVI = I 1 -V

VGS ID

0 IDSS

0.3Vp IDSS

/2

0.5Vp IDSS/4

Vp 0 mA


IDSS = 4 mA dan VGS(off) = 3 V

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Exercise 2

DGS P

DSS

IV = V 1 -

I


IDSS = 4 mA dan VGS(off) = 3V

2

GSD DSS

P

VI = I 1 -V

VGS =0.5VP

VGS =0.3VP

VP

IDSS

IDSS/2

IDSS/4

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Answer 2Answer 2

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DC JFET Biasing

Just as we learned that the BJT must bebiased for proper operation, the JFET alsomust be biased for operation point (ID, VGS,VDS)

In most cases the ideal Q-point will be atthe middle of the transfer characteristiccurve, which is about half of the IDSS.

3 types of DC JFET biasing configurations :

Fixed-bias Self-bias Voltage-Divider Bias

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Fixed-bias

VDS

+

_

VGG

VGS

_

RD

VDD

RG

+C1

C2

Fixed-bias

+

Vin

_

+

Vout

_

+ Use twovoltagesources: VGG,VDD

VGG is reverse-biased at theGate Source(G-S)terminal, thus

no currentflows throughRG (IG = 0).

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Fixed-bias..

DC analysis

All capacitors replaced with open-circuit

VDS

+

_

VGG

VGS

_

RD

VDD

RG

+

Loop 1

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Fixed-bias

1. Input Loop By using KVL at loop 1:

VGG + VGS = 0VGS = - VGG

For graphical solution, use VGS = - VGG to draw the loadline

For mathematical solution, replace VGS = -VGGin ShockleysEq. ,therefore:

2. Output loop- VDD + IDRD + VDS = 0

VDS = VDD IDRD

3. Then, plot transfer characteristic curve by using ShockleysEquation

2

)(

2

)(

11

offGS

GGDSS

offGS

GSDSSD

V

VI

V

VII

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Example : Fixed-bias

2GS

D DSS

P

VI = I 1 -

V

Determine the followingnetwork:

1.VGSQ2.IDQ3.VD4.VG5.V

S

Mathematical Solutions

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GSQ GGV = - V = - 2

2 2GS

DQ DSSP

2

V - 2I = I 1 - = 10mA 1 -

V -8

= 10mA 0 5.6.75 25mA

DS DD D DV = V - I R = 16 - 5.625mA 2k= 16V -11.25V = 4.75V

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Graphical solution for the network

GSQ GGV = - V = - 2

DS 4V = .75V

D

G

S

V =

V =

4.75V

- 2V

V = 0V

Draw load line for:

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Self-bias

Using only one voltage source

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DC analysis of the self-bias configuration.

G G GRG

RG

Since I 0A, V I R

thus V 0A,

Q point for VGS

Graphical Solutions:

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Graphical Solutions:Defining a point on the self-bias line.

VGS ID

0 IDSS

0.3Vp IDSS/20.5Vp IDSS/4

Vp 0 mA


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Graphical Solutions:Sketching the self-bias line.

D DSS

GS D S

DSS S

I = I 2

V = -I R

I R= -

2

DS DD D S DV = V - I R + R

S D SV = I R

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Mathematical Solutions:

Replace in the Shockleys Equation:

By using, quadratic equation and formula, choose value of

ID that relevant within the range (0 to IDSS): nearly to IDSS/2

Find VGS by using ;also choose VGS thatwithin the range (0 to VP)

2

)(

2

)(1

;

1

P

SDDSSD

offGSP

P

GSDSSD

V

RIII

therefore

VVV

VII

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Example : Self-bias configuration

GSQ

DQ

D

G

1. V

2. I

Det

3. V

e

rmine the following for

4. V

the network

5. Vs

G hi l S l ti

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Sketching the transfer characteristics

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S etc g t e t a s e c a acte st cscurve

Vgs ID

0 IDSS

0.3Vp IDSS/2

0.5Vp IDSS/4

Vp 0 mA

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Sketching the self-bias line

D GS

D GS

When I = 4mA, V =

When I = 8mA, V

- 4V

= - 8V

Graphical Solutions: Determining the Q-

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p g Qpoint

Q-point

IDQ=2.6mA

VGSQ=-2.6mV


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VVandmAIchoosetherefore

VV

kmAkmA

RIVRIV

mAImAI

IkI

kIII

MIkIkIm

kIm

kImI

VRII

RIVrecallV

VII

GSD

SDGSSDGS

DD

DD

DDD

DDD

DDD

P

SDDSS

SDGS

P

GSDSSD

6.2588.2;

6.29.13

)1(588.2)1(9.13

588.29.13

0288.01328

896288.036

1663636

8

6

)1(68

6

)1(18

)(1

1

211

2

2

2

22

2

2

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Solutions

GSQV = - 2.6V

DS DD D D SV = V - I R + R

= 20V - 2.6mA 4.3k

= 8.82V

IDQ = 2.6mA

ID=IS

Voltage divider bias

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Voltage-divider bias

A

IG=0A

Redrawn network

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Redrawn network

2G DD

1 2

RV = V

R + R

Sketching the network equation for the

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g qvoltage-divider configuration.

D

GS

GS G I =0mA

GD

SV =0V

V = V

VI

R

G GS RS

GS G RS

GS G D SV

V - V - V = 0

V = V

= V - I

V

R

-

Effect ofRS on the resulting

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gQ-point.

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Example : Voltage-divider bias

DQ GSQ

D

S

DS

DG

1. I andV

2. V

3. V

Determine the following for th

4. V

e netw k

5. V

or

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Solutions

2G DD

1 2

DD

2

RV = V

R + R

270k 16V= V

2.1M + 0.27M

= 1.82V

D GSWhen I = 0mA, V = + 1.82V

GS G D S

D

V = V - I R

= 1.82V - I 1.5k

GS D

+1.82VWhen V = 0V, I = = 1.21mA

1.5k

h f h k

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Determining the Q-point for the network

GS DV = 1.82V -I 1.5k

IDQ=2.4mA

VGSQ=-1.8V

DS DD SS D S D

DS S

V = V + V - I R R

= V + V = 8.82V + 2 11.6V = .42V

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Mathematical solutions

How to get IDS, VGS and VDS forvoltage-divider bias configuration byusing mathematical solutions?

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Exercise 3:

DQ GSQ

DS

D

S

1. I andV

2. V

Determine the

followi

3. V

ng for the networ

4. V

k

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Drawing the self bias line

GS D S

GS D

V + I R -10V = 0

V = 10V - I 1.5k

D GSWhen I = 0mA, V = 10V

GS D

10VWhen V = 0V, I = = 6.67mA

1.5k

Determining the Q-point I =6 9mA

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Determining the Q point IDQ=6.9mA

VGSQ=-0.35V

DS DD SS D S DV = V - V - I R + R

= 20+10- (6.9mA)(1.8k + 1.5k)

= 7.23V

D DD D DV = V - I R = 7.58V

S D DSV = V - V

= 7.58V - 7.23V = 0.35V

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Exercise 4

D S

Determine the required

values of R and R

Determining VGS for the network

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Determining VGSQfor the network.

DD DQRDD

DQ DQ

V VV 20V 12VR = =

I I 2.5mA

= 3.2k

GSQ

S

DQ

V -1R = = 0.4k

I 2.5mA

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