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EE141
1
VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.1
Chapter Chapter 1111
Analog and MixedAnalog and Mixed--Signal TestingSignal Testing
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.2
What is this chapter about?What is this chapter about?
� Introduces AMS circuits, failure modes and fault models.
� Addresses analog testing, including DC and AC parametric testing.
� Discusses mixed-signal circuits, ADC and DAC, and their testing approaches.
� Studies IEEE Std. 1149.4, the standard for mixed-signal test buses
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.3
Chapter 11Chapter 11
Analog and MixedAnalog and Mixed--Signal TestingSignal Testing
� Introduction
� Analog Circuit Testing
� Mixed-Signal Testing
� IEEE Std. 1149.4 Standard for Mixed-Signal Test Bus
� Concluding Remarks
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.4
11.1 Introduction11.1 Introduction
� Analog Circuit Properties
� Analog Defect Mechanism and Fault Models
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.5
Analog, Digital, and MixedAnalog, Digital, and Mixed--Signal Signals Signal Signals
1
0
AnalogAnalog MixedMixed--SignalSignal DigitalDigital
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.6
Analog Circuit PropertiesAnalog Circuit Properties
� Continuous Signal
� Large Range of Circuits
� Nonlinear Characteristics
� Feedback Ambiguity
� Complicated Cause-Effect Relationship
� Absence of Suitable Fault Model
� Accurate Measurements Required
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.7
Properties Properties -- Continuous SignalContinuous Signal
• Logic 1, Logic 0
• VIH, VIL, VOH, VOL• Rise Time, Fall Time
• Propagation Delay H-L/L-H• Noise Margin High/Low
Digital Signal Analog Signal
• Voltage/Current• Slew Rate
• Overshoot• Damping Factor
• Frequency
• Bandwidth
VH
VL
tLH tHL
SR
tSettle
VOV
VA
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.8
Properties Properties -- Large Ranges of CircuitsLarge Ranges of Circuits
Digital Circuits Analog Circuits
•Operation •Static Logic•Dynamic Logic
•Structure•Gates•PLA•Memory
• Operation• Current Mode• Voltage Mode• Switching Cap
• Structure• Amplifier• Multiplier• Rectifier• Resonator
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.9
PropertiesProperties-- Nonlinear CharacteristicsNonlinear Characteristics
� Analog circuits are nonlinear in nature
� Nonlinear cause effect
DI
DV
2)(2
1tgsoxD VV
L
WCI −= µTD VnV
sD eII×
⋅=/
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.10
PropertiesProperties-- Feedback AmbiguitiesFeedback Ambiguities
� Feedback puts circuit parameters together
� Difficult to identify fault location
-
+
-
+
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.11
PropertiesProperties-- Complicated CauseComplicated Cause--Effect RelationshipEffect Relationship
�Difficult to determine the cause of error.
12
i
0
RR
A1
A
V
VA
)( +
−==
1
2
i
0V
R
R
V
VA −==
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.12
Properties Properties –– Absence of Suitable Fault ModelsAbsence of Suitable Fault Models
Digital Faults
• Good Logic Fault Model
• Generally Accepted
• Stuck-at-1, Stuck-at-0
• Stuck-Open, Stuck-On
• Short. Open
• Memory Faults
• PLA Faults
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.13
Properties Properties -- Absence of Suitable Fault ModelsAbsence of Suitable Fault Models
An
alo
g F
au
lts
• No Good Fault Model• Not Generally Accepted
• Open Short• Missing/Extra Devices• Parameter Variation• Performance Deviation• Circuit Structure Related• Functional Faults• ???????????
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.14
PropertiesProperties –– Accurate Measurements RequiredAccurate Measurements Required
Digital Instrument
• Oscilloscope
• Function Generator
• Logic Analyzer
• Frequency Counter
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.15
An
alo
g In
str
um
en
t• Oscilloscope• Function Gen• Freq. Counter• Spectrum Analyzer• Network Analyzer• Impedance Analyzer• Timing Analyzer• Communication Analyzer• RF Instrument• Optical Instrument• Microwave Instrument
Properties Properties –– Accurate Measurements RequiredAccurate Measurements Required
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.16
11.1 Introduction11.1 Introduction
� Analog Circuit Properties
� Analog Defect Mechanism and Fault Models
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.17
Defect Mechanisms (1)Defect Mechanisms (1)� Material Defects
� cracks
� crystal imperfection
� surface impurities
� ion migration
� Processing Faults
� oxide thickness
� mobility change
� impurity density
� diffusion depth
� dielectric constants
� metal sheet
resistance
� missing contacts
� dust
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.18
Defect Mechanisms (2)Defect Mechanisms (2)
� Time-Dependent Failures
� dielectric breakdown
� electron migration
� Packaging Failures
� contact degradation
� seal leakage
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.19
Analog Fault Model Analog Fault Model
Defects/Failure
Hard Faults Soft Faults
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.20
Analog Faults Analog Faults -- DefectDefect
• Defects
• Extra Defects
• Etching Defects
• Source
• Dust
• Lithography
• Layout Oriented
• Statistical Model
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.21
Analog Faults Analog Faults -- Hard FaultsHard Faults
•Fault Models•Open•Short•Missing Device•Extra Devices
•Faulty Effects•Catastrophic Error•Module Malfunction•System Failure
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.22
Analog Faults Analog Faults -- Soft FaultsSoft Faults
• Parametric Faults• Io: 100uA -> 50uA• W: 20um -> 10um
• Deviation Faults• fo: 10MHz -> 5MHz• Gain: 10000 -> 2000
• Sources• Mobility• Oxide Thickness• Impurity Density• Defusion Depth• Dielectric Constants• Metal Sheet Resistance
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.23
Analog Fault Analog Fault -- Model MappingModel Mapping
� Deviation Faults
� Parametric Faults
Functional Level
Circuit Level
Layout Level� Extra Defects
� Etching Defects
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.24
Analog Faults Analog Faults -- Model MappingModel Mapping
Layout to Parametric• Defect Statistics
– Randomly insert dusts of random size.
• Parameter Statistics– Simulate the effect of dust on
transistor parameters
L
WCK oxµ=
Ko
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.25
Analog Faults Analog Faults -- Model MappingModel Mapping
Parametric to Deviation• Use SPICE simulation
and statistics to derive the performance deviation.
L
WCK oxµ=
KoFto
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.26
� Studied the analog test properties� Nonlinearity, Feedback Ambiguity
� No good fault model
� Overview the analog test plan� Test Code, Binning, Sequence Control
� Focused Calibrations, DIB Checkers
� Characterization and Simulation Code
� Analog Fault Model� Extra and Etching Defects
� Parametric and Deviation faults
� Model Mapping
11.1 Summary11.1 Summary
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.27
11.2 Analog Circuit Testing11.2 Analog Circuit Testing
� Analog Test Approaches
� Analog Test Waveforms
� DC Parametric Testing
� AC Parametric Testing
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.28
Analog Testing Analog Testing
Spec Oriented
Waveform
Oriented
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.29
Specification Oriented TestSpecification Oriented Test
Analog Devices, Inc.TM
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.30
Specification Oriented TestSpecification Oriented Test
� Specification Oriented Test
�Check whether all the specs are met
�Tedious and inflexible
� Example: Operational Amplifier�DC Specifications
–Input Offset Voltage
–Input Bias Offset Current
–Open-Loop Gain
–Noise
–Common Rejection Ratio
–Temperature Drift
� AC Specifications– Bandwidth
– Harmonic Distortion
– Slew Rate
– Settling Time
– Noise
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.31
Waveform Oriented TestWaveform Oriented Test
�Waveform Oriented Test
� Compare waveform to the simulated ones
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.32
Waveform Oriented TestWaveform Oriented Test
Settling Time, DC GainD
Overshoot, Damping Factor, BandwidthC
Slew Rate, Damping FactorB
DC Bias, Input OffsetA
A
B
C
D
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.33
Analog Testing Analog Testing -- ComparisonComparison
� Specification Oriented Test� Require more test runs and time
� Require accurate instrument
� Specifications are guaranteed
� Low defect level
� Waveform Oriented Test� Less test runs and test time
� More forgiving on instrument
� Specifications are not guaranteed
� Low cost
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.34
11.2 Analog Circuit Testing11.2 Analog Circuit Testing
� Analog Test Approaches
� Analog Test Waveforms
� DC Parametric Testing
� AC Parametric Testing
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.35
Analog Test WaveformsAnalog Test Waveforms
Sine Square (Step) Ramp Triangular
Chirp (Sweep Sine) Arbitrary Modulated
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.36
� For transient response testing
� Application: Filter, OPs, VCO, etc
� Difficult to generate good steps
Waveform Waveform -- StepStep
Trr
r
oo
Tf
Tf
5.3
1)3~4(
160~45
=
=
±±=θ
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.37
� Step change in voltage: Transient testing
� Step change in frequency: PLL testing
� Step change in amplitude: AGC testing
Waveform Waveform -- StepStep
Frequency StepVoltage Step Amplitude Step
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.38
Waveform Waveform -- RampRamp
� Sawtooth Wave Generation
-
+
� Triangular Wave Generation
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.39
� Also called Sweep Sine
� Generation: Triangular to VCO
� Application: Frequency response plotting
Waveform Waveform -- ChirpChirp
+
-
VCOChirp
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.40
� Application: Frequency response plotting
Waveform Waveform -- ChirpChirp
+
-
VCOCUT
FilterLPF
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.41
�Synthesized by DACs
�Combinations of all kinds of waveform
Waveform Waveform -- ArbitraryArbitrary
DAC LPF
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.42
�Modulated/Synthesized Waveforms
� Communication System Testing
–GSM, CDMA, 1394, USB2, etc.
� Modulation
–AM, FM, PCM, PWM, QAM, PSK, QPSK
�Generated by dedicated instrument
Waveform Waveform -- Modulated/SynthesizedModulated/Synthesized
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.43
11.2 Analog Circuit Testing11.2 Analog Circuit Testing
� Analog Test Approaches
� Analog Test Waveforms
�DC Parametric Testing
� AC Parametric Testing
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.44
DC Parametric TestingDC Parametric Testing
Source: [Sata 1967]Temperature drift
Maximum common mode voltage
Maximum voltage between inputs
Common mode rejectionSupply voltage sensitivity
Input impedanceInput noise
Input offset currentInput offset voltage
Input bias currentOverload recovery
Unity gain small signal response
Unity gain full power response
Slewing rateOpen-loop gain
Rated output voltageRated output current
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.45
DC Test DC Test –– OpenOpen--Loop Gain MeasurementLoop Gain Measurement
y
xo
V
VA
∆
∆⋅= 101
Vi
10K 10K
10K
100
100
y
xo
V
VA
∆
∆⋅=101
OctavedB /6−
102 103 104 105 106101
20
80
60
40 Ao
tf
dBf3
o
oL
I
VR =
yV xV
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.46
DC Test DC Test –– Unit Gain Bandwidth MeasurementUnit Gain Bandwidth Measurement
dBot fAf 3⋅=
100
ti
f
SRV
π2≤
o
of
I
VR =
fR
Inverting Configuration
1k
100
ti
f
SRV
π2≤
o
oL
I
VR =
yV xV yV xV
Noninverting Configuration
ti
f
SRV
π2≤
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.47
DC Test DC Test –– Common Mode Rejection RatioCommon Mode Rejection Ratio
100
CMV
R1
R1R2
R2
oV∆CMV∆
1
2/
R
RV
A
VV o
o
oiCM ∆=
∆=⋅
)/log(20CM
oo
V
VACMRR
∆
∆=
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.48
DC Test DC Test –– Power Supply Rejection RatioPower Supply Rejection Ratio
)/log(20DD
oo
V
VAPSRR
∆
∆=
DDV
oV∆DDV∆
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.49
11.2 Analog Circuit Testing11.2 Analog Circuit Testing
� Analog Test Approaches
� Analog Test Waveforms
� DC Parametric Testing
� AC Parametric Testing
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.50
� Test Types� Gain
� Phase
� Distortion
� Signal Rejection
� Noise
� Test Setup� AGW: Arbitrary Waveform Generator (DAC)
� Digitizer: Sample and convert to digital (ADC)
Analog AC TestingAnalog AC Testing
AWG CUT Digitizer
DSP
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.51
� Input sine wave (1KHz) with fixed amplitude
� Digitize the output waveform
� DSP (FFT) to eliminate distortion and noise.
� Check the fundamental amplitude.
� Detect first order defects in a circuit.
� Voltage in dBV or dBm
AC AC –– Maximal Output AmplitudeMaximal Output Amplitude
DUTAWG Digitizer
VPP
Clipped
DSP
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.52
AC AC -- Frequency ResponseFrequency Response
LPF
Low Pass Filter
HPF
High Pass Filter
BPF
Band Pass Filter
BRF
Band Reject Filter
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.53
AC AC -- Frequency ResponseFrequency Response
A (dB)
101 102 103 104 105 106 107
0
-45
-90
-135
-180
Phase
40
20
0
-20
-40
-20dB/dec
-40dB/dec
-20dB/dec
-45/dec
45/dec
))((
)(
)(
42
6
2
10
jw1
10
jw1
10
jw110
jwA
++
+
=
• Open Loop Gain 102
• Pole 1: 102
• Pole 2: 104
• Zero: 106
Bode Plot
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.54
AC AC -- Frequency ResponseFrequency Response
Pass BandStop Band Stop Band
F
A(dB)
Pass Band Ripple
Stop Band
Rejection
Stop Band
Rejection
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.55
AC AC -- Frequency ResponseFrequency Response
F
A(dB)
Upper Limit
MaskLower Limit
Mask
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.56
AC AC -- Frequency ResponseFrequency ResponseFrequencies of
special interests
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.57
AC AC -- Frequency ResponseFrequency Response
•Multi-tone Test Waveform
∑=
=
ϕ+ϖ=ki
1iiii tAtA )sin()(
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.58
AC AC -- Frequency ResponseFrequency Response
•Multi-tone Test Waveform
∑=
=
ϕ+ϖ=ki
1iiii tAtA )sin()(
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.59
•Distortion•Harmonic Distortion• Intermodulation Distortion•Crossover
•Cause•Nonlinearity of the circuit•Clip (saturation)•Mismatch of the devices
AC AC –– Noise and DistortionNoise and Distortion
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.60
AC AC –– Noise and DistortionNoise and Distortion
•Apply sinusoidal waveform•Do Fourier transform on response waveform•Obtain F domain properties mathematically.
Filter FFT
dB Fundamental
Peak Harm.
Noise Flour
Offset
Analysis
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.61
AC AC –– Noise and DistortionNoise and Distortion
dBFundamental
Harmonics
DC
Offset
F
NoiseF
H2 H3H4
H5
Ni
∑=
2
2
log10
iN
FSNR%100log10
2
2
2
2
∑∑×==
ii H
F
H
FTHD
∑ ∑+=
22
2
log10
ii NH
FSNDR
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.62
AC AC –– IntermodulationIntermodulation DistortionDistortion
tfAtfAtv 2211 2sin2sin)( ππ +=
2 4 6 8 10 12 14 16 18 200 22 24
f2 – f1
2f1 – f2 2f 2 – f1
f1 f2
f1 + f2
2f12f2
3f1 3f2
7 8
f1 f2
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.63
� Studied the analog test approaches� Specification oriented testing
� Waveform oriented testing
� Outlined the analog test waveforms� Sine, step, triangular, chirp, arbitrary, modulated
� Discussed DC parametric testing� Open-loop gain, unit gain bandwidth
� CMRR, PSRR
� Discussed AC parametric testing� Use AWG, Digitizer, and DSP
� Frequency response, Noise, and Distortion
11.2 Summary11.2 Summary
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.64
11.3 Mixed11.3 Mixed--Signal Testing Signal Testing
� Introduction to Analog-Digital Conversion
� ADC and DAC Circuit Structure
� ADC/DAC Specification and Fault Models
� IEEE Std. 1057
� Time-Domain ADC Testing
� Frequency-Domain ADC Testing
EE141VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.65
X in
X out LSBs12
11
10
9
8
7
6
5
4
3
2
1
0
1 2 3 4
1
2
3
4
AD Model AD Model -- QuantizationQuantization
X in
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.66
• Quantization error is sawtooth-like. • Uniform distribute between (-q/2, q/2) (q=LSB).
q
)t(x Original signal Quantized signal
t
t
2/q
2/q−
)t(nq Quantization error
QuantizatoinQuantizatoin –– Noise ModelNoise Model
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.67
• The error contains a lot of jumps.
• Error spectral is much wider than the original signal.
• The bandwidth of the quantization is proportional to
the slop of the signal and inversely proportional to
the quantum size q.
QuantizatoinQuantizatoin –– Noise ModelNoise Model
t
2/q
2/q−
)t(nq Quantization error
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.68
� A sine wave is quantized by a B-bit ADC. How large is the SNR.
Quantization Quantization -- Noise Model Noise Model
qVpn22 =
2
2p
S
VP =
123
22
2
PN =
=
q
)t(x
Original signal
Quantized signal
t
t
2/q
2/q−
)t(nq Quantization error
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.69
Quantization Quantization -- Noise Model Noise Model
)46log(10
12
2log10log10 12
2
−⋅=
== n
p
N
s
q
V
P
PSNR
dBSNR 8.61=For n=10,
dBnSNR )676.1( +==
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.70
11.3 Mixed11.3 Mixed--Signal Testing Signal Testing
� Introduction to Analog-Digital Conversion
� ADC and DAC Circuit Structure
� ADC/DAC Specification and Fault Models
� IEEE Std. 1057
� Time-Domain ADC Testing
� Frequency-Domain ADC Testing
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.71
ADC Architecture ADC Architecture -- Gain StageGain Stage
Gain Filter MUX S/H
ADC
� Gain: Provide offset and full scale conversion
� Filter: Reject off-band noise (anti-aliasing filter)
� MUX: Provide multiple channel access
� S/H: Provide steady signal for A-to-D conversion
� ADC: Actual analog to digital conversion
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.72
ADC Architecture ADC Architecture -- Gain StageGain Stage
Gain Filter MUX S/H
ADC
� Function: Provides gain and offset
� Achieve the maximal A/D resolution by scaling the input signal to match the full A/D input range.
� Drawbacks:� Introduces noise, nonlinearity, drift
� Expense of tight-tolerance
� Require calibration
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.73
ADC Architecture ADC Architecture -- Filter StageFilter Stage
Gain Filter MUX S/H
ADC
� Function: Attenuate the out-of-band noise to prevent aliasing
� Filter Position� Before the MUX (1 per channel) : maximize speed in
switching channels.
� After the MUX: minimize mismatching among channels.
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.74
ADC Architecture ADC Architecture -- Filter StageFilter Stage
� Anti-Aliasing Filter
A(w) A(w) A(w)
Signal
Spectrum
Nyquist Rate
Sampling
4X Over
Sampling
Anti Aliasing Filter Anti Aliasing Filter
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.75
ADC Architecture ADC Architecture -- MUX StageMUX Stage
Gain Filter MUX S/H
A
DC
� Function: Provides multiple access
� Crosstalk:� The most severe problem
� Frequency dependent
� Can be minimized by placing amplifier before the MUX.
� Load Issues� Avoid too many fanins.
� Use hierarchical structure.
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.76
ADC Architecture ADC Architecture -- S/H StageS/H Stage
Gain Filter MUX S/H
A
DC
� Function: � Provides steady signal
� Provides signal synchronization,
� S/H position:� After the MUX for cost reason
� Before MUX for synchronization and crosstalk reduction.
MU
X
S/H
S/H
S/H
S/H
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.77
ADC Architecture ADC Architecture -- S/H Check ListS/H Check List
� Aperture Time: The time aperture (t3)
� Acquisition Time: The total time for the S/H to acquire a full-scale step input signal. (t3 - t1)
� Aperture Jitter: The uncertainty of aperture time due to
noise or jitter in clock. (t4-t2)
Sample Hold
1t 2t 3t 4t
LSBXVc ⋅≤∆ %S
VinVc
HC
R
H
leakdroop
C
IV =
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.78
ADC Architecture ADC Architecture -- ADC StageADC Stage
Gain Filter MUX S/H
ADC
�Executes analog to digital conversion
�Check List:� Bit length
� Accuracy
� Conversion Rate
� System Error Budget
▪ Input Signal Range
▪ Total System Cost Target▪ Input Impedance
▪ AC or DC Inputs BW
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.79
DAC Example DAC Example -- RR--2R Ladder2R Ladder
-+
Vref
S1 S2 S3 S4 S5 S6
2R 2RRf=R
Vout
2R 2R 2R 2R
2RRR R R R
6
00
11
22
33
44
55
605142332415
2)222222(
222222
ref
refrefrefrefrefrefo
VSSSSSS
VS
VS
VS
VS
VS
VSV
⋅⋅+⋅+⋅+⋅+⋅+⋅=
⋅+⋅+⋅+⋅+⋅+⋅=
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.80
ADC Example ADC Example –– Pipelined ADCPipelined ADC
S/H
ADC DAC
X 4
3 bits
S/H
ADC
X 4
3 bits
S/H
ADC DAC
X 4
3 bits
S/H
ADC
2 bits
DAC
s1 s2 s3 s4da3da2da1iV
Calibration and Correction Circuit
d0 d7
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.81
ADC ADC –– Bits Bits v.sv.s. Throughput. Throughput
~ 10 M14 ~ bitsSigma-Delta
10 ~ 100 MHz8 ~ 16 bitsPipelined
100 M ~~ 6 bitsFlash
ThroughputBit-LengthADC
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.82
ADC ADC –– Selection MatrixSelection Matrix
100Mbps+
10 to 100Mbps
1Mbps to
10Mbps
100Kbps
to 1Mbps
10Kbps to
100Kbps
<10kbpsBits
<8
8-9
10-11
12-13
14-16
17+
From Analog Devices Inc.
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.83
ADC ADC ––Example Example
AD775AD775
From Analog Devices Inc.
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.84
11.3 Mixed11.3 Mixed--Signal Testing Signal Testing
� Introduction to Analog-Digital Conversion
� ADC and DAC Circuit Structure
� ADC/DAC Specification and Fault Models
� IEEE Std. 1057
� Time-Domain ADC Testing
� Frequency-Domain ADC Testing
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.85
ADC ADC –– Offset ErrorOffset Error
Offset
X in
Xout
•Offset: constant component of the error that is
independent of the inputs
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.86
ADC ADC –– Gain ErrorGain Error
X in
Xout
•Gain Error: difference between the actual
transfer ratio and the ideal ratio
• Also called Calibration Error
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.87
ADC ADC –– Nonlinearity ErrorNonlinearity Error
X in
Xout
•Nonlinearity error: The deviation of the output
quantity from a specified linear reference
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.88
ADC ADC –– Nonlinearity ErrorNonlinearity Error
• Integral Nonlinearity:
Worst-case deviation from the ideal transfer characteristic curve
• Differential Nonlinearity:
Difference between the actual transfer ratio and the ideal ratio
IN = 2 LSB
DN = 0.5 LSB
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.89
ADC ADC –– TemperatureTemperature--Dependent ErrorDependent Error
•Temperature-Dependent Error: Due to the
change in ambient temperature or temperature
variation due to self-heating (temperature stability,
temperature coefficient)
X in
XoutT 3
T 2
T1
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.90
ADC ADC –– LoadLoad--Dependent ErrorDependent Error
•Load Error: Loading error is due to the effect of a
load impedance upon the converter or signal source
driving it.
X in
XoutRL1
RL2RL1RL1
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.91
ADC ADC –– HysteresisHysteresis ErrorError
X in
X out
•Hysterisis Error: The difference between the increasing and decreasing input values that produce the same output
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.92
ADC ADC –– Resolution ErrorResolution Error
X in
Xout
• Resolution Error: The error due to the inability to
respond to change of a variable smaller than a given
increment
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.93
ADC ADC –– Missing Code ErrorMissing Code Error
Missing Codes
Ideal Input Waveform
Quantized with missing Code
Quantization Error
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.94
11.3 Mixed11.3 Mixed--Signal Testing Signal Testing
� Introduction to Analog-Digital Conversion
� ADC and DAC Circuit Structure
� ADC/DAC Specification and Fault Models
� IEEE Std. 1057
� Time-Domain ADC Testing
� Frequency-Domain ADC Testing
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.95
IEEE 1057 StandardIEEE 1057 Standard
� Scope
� Covers electronic digitizing waveform
recorders, waveform analyzers and
digitizing oscilloscopes with digital outputs.
� Applies to, but is not restricted to, general-
purpose waveform recorders and
analyzers.
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.96
IEEE 1057 StandardIEEE 1057 Standard
� Purpose
� Provides common methods for testing and
terminology for describing the performance
of waveform recorders.
� Benefits users and manufacturers of such
devices.
� Presents many performance features,
sources of error, and test methods.
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.97
IEEE 1057 IEEE 1057 –– General InformationGeneral Information
Calibration interval
Exception to the above parameters where applicable
Available options and accessories
Any special or peculiar characteristics
Environmental conditions (tem., humidity, EMC/EMI, etc.)
Power Requirement
Dimensions and weight
Model Number
EE141
98
VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.98
IEEE 1057 IEEE 1057 –– Minimum SpecificationMinimum Specification
Input signal rangesMemory length
Analog bandwidthSample rates
Input impedanceNumber of digitizing bits
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.99
IEEE 1057 IEEE 1057 –– Additional SpecificationsAdditional Specifications
Maximum common mode signal level
Transition duration of step responseLong-term stability
mode signal levelAperture uncertainty
Maximum operating commonOvershoot and precursors
Differential input impedanceSlew limit
Common mode rejection ratioSettling time
Cycle timeFrequency response
Word error rateRandom noise
Over voltage recoveryPeak error
HystersisEffective bits
MonotonicitySignal to noise ratio
CrosstalkMaximal static error
Trigger coupling to signalSpurious response
Trigger hysteresis bandHarmonic distortion
Trigger minimum rate of changeIntegral nonlinearity
Trigger sensitivityDifferential nonlinearity
Trigger delay and jitterOffset
Fixed error in sample timeGain
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.100
IEEE 1057 IEEE 1057 –– Test MethodsTest Methods
Linearity, harmonic distortion, and spurious responses
Differential Input SpecificationTime base errors
Cycle TimeStep Response parameters
Word Error RateFrequency response
Overvoltage RecoveryAnalog bandwidth
HysteresisNoise
MonotonicityGain and offset
CrosstalkInput impedance
TriggeringGeneral methods
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.101
11.3 Mixed11.3 Mixed--Signal Testing Signal Testing
� Introduction to Analog-Digital Conversion
� ADC and DAC Circuit Structure
� ADC/DAC Specification and Fault Models
� IEEE Std. 1057
� Time-Domain ADC Testing
� Frequency-Domain ADC Testing
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.102
Histogram Histogram –– Code BinsCode BinsCode Bin
T[1]
T[2]
T[6]
T[6]
T[5]
T[4]
T[3]
7
6
5
4
3
2
1
0
W[7]
W[6]
W[5]
W[4]
W[3]
W[2]
W[1]
W[0]Code Level
Code Width W[k]
245
543
456
372
345
472
529
302
Bin Count H[k]
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.103
Test Methods Test Methods -- Code Transition LevelCode Transition Level
Code Bin
T[1]
T[2]
T[6]
T[6]
T[5]
T[4]
T[3]
7
6
5
4
3
2
1
0
0
0
12
45
443
454
30
16
Static Test Method• Start from 2% below the transition level.• Take a number of samples.• Adjust the input level until the 50% codes
are greater than k.
Samples
Precision
64
45%
256
23%
1024
12%
4096
6% % of rms noise
500
500
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.104
Test Methods Test Methods -- Code Transition LevelCode Transition LevelDynamic Test Method• Apply full range sine wave• Calculate the transition level from the bin count
T[1]
T[2]
T[6]
T[6]
T[5]
T[4]
T[3]
7
6
5
4
3
2
1
0
245
543
456
372
345
472
529
302
−⋅−=
M
kHACkT c ]1[
cos][π
• A: Amplitude C: Offset• H[j]: The code count of bin j.
• M: Total number of samples • Record Length M and Number of Cycles Mc must not have common term.
∑=
=j
ic iHjH
0
][][
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.105
Test Methods Test Methods -- Gain and OffsetGain and Offset
• Apply a slow ramp signal
• Construct the code bin table
1)1(][][ TkQkVkTG os +−⋅=++⋅ ε
T[1]
T[2]
T[6]
T[6]
T[5]
T[4]
T[3]
7
6
5
4
3
2
1
0
203
443
440
435
439
429
447
330
Q: ideal width of the code bin
( ) [ ]
( ) [ ] [ ]
( )( ) [ ]
( ) [ ] [ ]∑ ∑
∑
∑ ∑
∑
−
=
−
=
−
=
−
−
=
−
=
−
=
−−
−
−
−−
−
=12
1
212
1
2
12
1
1
12
1
212
1
2
12
1
12
212
12
12
N N
N
N N
N
k k
N
k
NN
k k
N
k
N
kTkT
kT
Q
kTkT
kkT
QG
( ) [ ]∑−
=−−−+=
12
1
112
12
N
kN
N
os kTG
QTV
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.106
Test Methods Test Methods -- Gain and Offset (Example)Gain and Offset (Example)
Ideal Gain Error Offset Error
Transfer Curves
Histograms
128 128 128 128
Game/Offset
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.107
Test Methods Test Methods -- NonlinearityNonlinearity
[ ][ ]
[ ]Q
QkWGDNL
Q
QkWGkDNL
−⋅=
−⋅=
max
[ ] ( )N
Q
TkQkTMSE
2
1max100 1−−−
=
[ ]N
Q
kINL
2
max100
ε=
Differential Nonlinearity
IntegralNonlinearity
MaximalStatic Error
T[1]
T[2]
T[6]
T[6]
T[5]
T[4]
T[3]
7
6
5
4
3
2
1
0
203
443
440
435
439
429
447
330
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.108
Test Methods Test Methods -- Sine Wave FittingSine Wave Fitting
oioi CtAy += ωsin
• Try to fit the sine wave to find the gain A’, offset Co,
and phase shift θ.• There are matrix based and nonmatrix methods.
( )myyy L,, 21
( )mttt L,, 21( ) ( )
∑ −−−=
m
iiii CtBtAyMin
1
2)coscos( ωω
CtAy ii ++= )sin('' θω
CtBtAy iii ++= )cos()sin(' ωω
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.109
Test Methods Test Methods -- Sine Wave FittingSine Wave Fitting
ooo CtAty += )sin()( ϖ
CtBtAty ++= )cos()sin()(' ϖϖ
o
o
A
ABA −+ 22
oCC −
−= −
A
B1tanθ
o
o
ϖ
ϖϖ )( −
Original Signal:
Curve Fitted:
Gain Error:
Offset Error:
Phase Error:
Frequency Error:
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.110
11.3 Mixed11.3 Mixed--Signal Testing Signal Testing
� Introduction to Analog-Digital Conversion
� ADC and DAC Circuit Structure
� ADC/DAC Specification and Fault Models
� IEEE Std. 1057
� Time-Domain ADC Testing
� Frequency-Domain ADC Testing
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.111
ADC ADC –– Frequency Domain TestingFrequency Domain Testing
• Similar to Analog AC Testing• Apply sinusoidal waveform• Do Fourier transform on response waveform• Obtain F domain properties mathematically.
Filter FFT
dB Fundamental
Peak Harm.
Noise Flour
Offset
Analysis
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.112
ADC ADC –– Frequency Domain TestingFrequency Domain Testing
dBFundamental
Harmonics
DC
Offset
F
NoiseF
H2 H3H4
H5
Ni
∑=
2
2
log10
iN
FSNR%100log10
2
2
2
2
∑∑×==
ii H
F
H
FTHD
∑ ∑+=
22
2
log10
ii NH
FSNDR
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.113
11.4 IEEE Std. 1149.4 Standard for a 11.4 IEEE Std. 1149.4 Standard for a
MixedMixed--Signal Test Bus Signal Test Bus
� IEEE Std. 1149.4 Overview
� IEEE Std. 1149.4 Circuit Structures
� IEEE Std. 1149.4 Instructions
� IEEE Std. 1149.4 Test Modes
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.114
IEEE 1149.4 IEEE 1149.4 -- OverviewOverview
� Target mixed signal Printed Circuit Assembles (PCA).
� Components:� Mixed Signal
� Digital
� Analog
� Discrete
D D
A A
M MC
C
CInterconnect
Discrete
Component
M: Mixed-signal Component
A: Analog Component
D: Digital Component
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.115
IEEE 1149.4 IEEE 1149.4 -- ScopeScope
� Provide standardized approaches to
� Interconnect Test
� Parametric Test
� Internal Test
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.116
IEEE 1149.4 IEEE 1149.4 -- Interconnect TestInterconnect Test
A
A
D
D
D
A
A
A
D
D
D
A
A
A
D
D
D
A
A
A
D
D
D
A
Open Defects Short Defects
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.117
IEEE 1149.4 IEEE 1149.4 -- Parametric TestParametric Test
A
A
A
D
D-A
A
A
A
D
D-A
Simple Interconnect Extended Interconnect
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.118
IEEE 1149.4 IEEE 1149.4 -- Internal TestInternal Test
A
A
A
D
D-A
Analog
Analog
Analog
Digital
EE141VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.119
IEEE 1149.4 IEEE 1149.4 -- ArchitectureArchitecture
IC1 IC2 ICnIC Under Test
Analog
AT1
AT2
AB1
AB2
Test Waveform Response Waveform
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.120
11.4 IEEE Std. 1149.4 Standard for a 11.4 IEEE Std. 1149.4 Standard for a
MixedMixed--Signal Test Bus Signal Test Bus
� IEEE Std. 1149.4 Overview
� IEEE Std. 1149.4 Circuit Structures
� IEEE Std. 1149.4 Instructions
� IEEE Std. 1149.4 Test Modes
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.121
IEEE 1149.4 IEEE 1149.4 -- ArchitectureArchitecture
IC
Core
DigitalBM
ABM
ABM
AnalogBM
A Pins
TBIC
Analog
TAP
AT1
AT2
TAP Controller1149.1
TAP
TDITDOTMSTCK
D Pins
InternalA Bus
EE141VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.122
IEEE 1149.4 IEEE 1149.4 -- TBICTBIC
VH
VL
VTH
ABM
ABM
TBIC
Core
TAP
AB1
AB2
AT2
Vc
AB1 AB2
Switch
AT1
AT1
AT2
EE141VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.123
IEEE 1149.4 IEEE 1149.4 -- ABMABM
AT1AT2
AB1AB2
VH VLVTH VG
A PinCD
ACUT
TBIC
ABM
ABM
TBIC
CoreCircuit
Test Control CircuitryTAP Controller
AB1AB2 AT1
AT2
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.124
1149.4 1149.4 –– MixedMixed--Signal ArchitectureSignal Architecture
DigitalCore
Circuit
AnalogInputs
A/D
AnalogCore
TDI TDO
AnalogOutputs
Digital
Inputs
Digital
Outputs
DBMABM
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.125
11.4 IEEE Std. 1149.4 Standard for a 11.4 IEEE Std. 1149.4 Standard for a
MixedMixed--Signal Test Bus Signal Test Bus
� IEEE Std. 1149.4 Overview
� IEEE Std. 1149.4 Circuit Structures
� IEEE Std. 1149.4 Instructions
� IEEE Std. 1149.4 Test Modes
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.126
IEEE 1149.4 IEEE 1149.4 -- InstructionsInstructions
� Mandatory Instructions
� BYPASS
� SAMPLE/PRELOAD
� EXTEST
� PROBE
� Same as IEEE 1149.1
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.127
IEEE 1149.4 IEEE 1149.4 -- InstructionsInstructions
� Optional Instructions
� INTEST
� IDCODE/USERCODE
� RUNBIST
� CLAMP
� HIGHZ
� Same as IEEE 1149.1
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.128
11.4 IEEE Std. 1149.4 Standard for a 11.4 IEEE Std. 1149.4 Standard for a
MixedMixed--Signal Test Bus Signal Test Bus
� IEEE Std. 1149.4 Overview
� IEEE Std. 1149.4 Circuit Structures
� IEEE Std. 1149.4 Instructions
� IEEE Std. 1149.4 Test Modes
EE141VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.129
1149.4 1149.4 –– Open/Short Interconnect TestOpen/Short Interconnect Test
AB1AB2
VH VL
AB1AB2
VTH
Chip 1 Chip 2
1
0
EE141VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.130
1149.4 1149.4 –– ExtenExtendded Interconnect Tested Interconnect Test
AB1
AB2
TBIC
ABM
V
DUT
IV
• Grounded Impedance Measurement• Apply current and measure voltage
ZD
EE141VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.131
1149.4 1149.4 –– ExtenExtendded Interconnect Tested Interconnect Test
• Equivalent Circuit Model.
M
SIOR
SVIR
)(tIs
)(tVm
1PZ
2PZ
DUTZ DUTI
DUTV
DUTPSIO
SIOsDUT
ZZR
RtItI
++⋅=
1
)()(DUTPSVI
SVIDUTM
ZZR
RtVtV
++⋅=
2
)()(
EE141VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.132
1149.4 1149.4 –– ExtenExtendded Interconnect Tested Interconnect Test
AB1
AB2
T
B
IC
A
B
M
V
DUT
VG
I
V
• Floating Impedance Zd Measurement
ZD
EE141VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.133
1149.4 1149.4 –– ExtenExtendded Interconnect Tested Interconnect Test
AB1
AB2
TB
I
C
AB
M
V
DUT
VG
I
V
Vg Option with
Nonzero Vg
• Floating Impedance ZD with optional Vg
ZD
EE141VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.134
T
B
I
C
A
B
M
VA
B
M
T
B
I
C
• Apply voltage and measure current
ZD
1149.4 1149.4 –– ExtenExtendded Interconnect Tested Interconnect Test
EE141VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.135
• Equivalent Circuit Model
1149.4 1149.4 –– ExtenExtendded Interconnect Tested Interconnect Test
SIIR)(tIm
V
SVOR
)(tVs
1PZ
2PZ
DUTZ
DUTV
DUTI
M
SIIPDUTPSVO
DUTsDUT
RZZZR
ZtVtV
++++⋅=
21
)()(SIIPDUTPSVO
sm
RZZZR
tVtI
++++=
21
)()(
21
)()(PDUTP
DUTsDUT
ZZZ
ZtVtV
++⋅=
21
)()(
PDUTP
sm
ZZZ
tVtI
++=
With Ideal Voltage Source and Current Meter
EE141VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.136
• Measure complex interconnect network
V
P1
P2 P4
P3
Z1Z2
Z3V34V12
V13
Vg
1149.4 1149.4 –– ExtenExtendded Interconnect Tested Interconnect Test
EE141VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.137
V
P1
P2 P4
P3
Z1Z2
Z3
Vg
1149.4 1149.4 –– ExtenExtendded Interconnect Tested Interconnect Test
02
222
02
112
01
221
01
111
11
22
==
==
==
==
II
VV
V
Ih
V
Vh
I
Ih
I
Vh
Im: Measure CurrentVs: Apply Voltage
Vm: Measure VoltageIs: Apply CurrentNotations
GNDVs/ImGNDOpenh22
GNDImGNDIsh21
GNDVsGNDVmh12
GNDGNDGNDIs/Vmh11
P4P3P2P1H
EE141VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.138
1149.4 1149.4 -- High Speed ApplicationsHigh Speed Applications
• Use buffers for better frequency response
AB2
VHVL VTHVG
AB1TBIC
ABM
Analog
Core
Current Buffer
Voltage Buffer
EE141
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VLSI Test Principles and Architectures Chap. 11 - Analog and Mixed-Signal Testing - P.139
11.5 Concluding Remarks11.5 Concluding Remarks� AMS testing requires specialized approaches
and experienced engineers because of the large varieties of signals, functions and circuits.
� DSP approaches are so pervasive that even basic analog test items can be accomplished.
� IEEE 1057 with formal terminologies and standardized test methods provides a solid theoretical background for ADC/DAC testing.
� IEEE 1149.4 is one solution to extending and incorporating the digital counterpart.