Chapter 2

MOS Transistor Theory

NMOS Operation Region

Transistor

L

WC

VV

VVVV

I

ox

tgs

dsdstgs

ds

2*2/

2/

0

n=2P

I-V Curve of MOS

Intrinsic MOS CapacitanceCO=WLCox

Diffusion Capacitance

Csb=AS*Cjbs+PS*Cjbssw

In SPICE, simulator will extract AS,AD,PS,PD parameters to calculate the diffusion capacitance of each MOS.

Non-ideal I-V Effects

Channel Length Modulation

)1(*2/ 2dstgsds VVVI

Body Effect

))((0 sVsVV sbtt

Body effect coefficient

For example

))((4.0 sVsV sbt

If Vsb=1.1 V, then

Vt=0.68 V

HW: Exercise 2.6

Junction Leakage

ID= IS[eVD/vt -1]

Gate leakage

Temperature Dependence

In SPICE, all the simulations should pass all the spec. temperature, for example, -40~120C.

Inverter DC CharacteristicC: PMOS and NMOS all in the saturation region

Beta RatioBeta ratio>1 =HI-skewedBeta ratio=1 =UnskewedBeta ratio<1 =LO-skewed

Noise Margin

Ratioed Inverter

Pseudo-nMOS Inverter

Some Issues

HW: Exercise 2.21 & 2.22

Tristate Inverter

Charge sharing effects

RC Circuit Model

)(

11

tgsox VVW

L

CR