35

CHAPTER 2

PRIOR WORK: TECHNIQUES FOR LEAKAGE

POWER REDUCTION

2.1 MOTIVATION

There are three sources of power dissipation in CMOS digital

circuits namely dynamic power, short circuit power and leakage power.

Generally, the dynamic power is dominant and the other two parts are

insignificant. But this will not be the case as the CMOS technology scales

down further. As the CMOS technology scales down, the supply voltage must

be decreased such that dynamic power can be kept at sensible levels.

In order to prevent a harmful effect on performance, the threshold

voltage must be reduced at a rate such that an adequate gate overdrive is

maintained. This reduction in the threshold voltage enhances the leakage

current of about 6 times per generation, which in turn can increase the static

power of the device to undesirable levels. In 100nm CMOS technology, the

leakage power is approaching 35% of the total processor power

(Borkar 1999). The leakage power is as much as 50% of the total power in the

100nm technology (De 1999). Thus, leakage reduction is necessary for

CMOS technologies below 100nm. Also, leakage is significant in both

standby and active operation modes. Essentially, the leakage in active mode is

significantly larger due to the high die temperature in active mode.

36

To solve the leakage problem many leakage reduction techniques have been proposed. Among them, some require modification of the process technology, achieving leakage reduction during the fabrication stage. Others are based on circuit-level optimization schemes that require architecture support. In spite of all these available techniques to reduce leakage power in circuits, leakage power still remains a big problem for deep submicron circuits. Furthermore, most of the available leakage reduction techniques can only reduce the circuit leakage power in standby mode. So, more efficient active leakage power reduction techniques are still necessary to keep the leakage power under control as CMOS technology scales down.

Another crucial driving factor is that excessive power consumption is becoming the limiting factor in integrating more transistors on a single chip or on a multiple-chip module. Unless power consumption is dramatically reduced, the resulting heat will limit the feasible packing and performance of VLSI circuits and systems.

From the environmental viewpoint, the smaller the power dissipation of electronic systems, the lower the heat pumped into the rooms, the lower the electricity consumed and hence the lower the impact on global environment, the less the office noise (e.g., due to elimination of a fan from the desktop), and the less stringent the environment/office power delivery or heat removal requirements.

2.2 PROBLEM STATEMENT

The problem to be solved in this research work is:

To find techniques to reduce the leakage power in the CMOS VLSI circuit significantly without introducing much performance cost. The implementation complexity of the technique should be feasible so that it can be practical for large circuits.

37

To find a new set of logic gates with reduced transistor count

which ultimately results in less power dissipation, smaller area

and high speed low power SOC applications.

2.3 LITERATURE REVIEW

A lot of interesting research work has been done in the attempt to

minimize leakage power. Listed below are some publications, each having its

own unique features:

Sakata et al (1993) proposed circuits featuring a hierarchical power-

line scheme and a switched-power-supply CMOS inverter with a level holder.

The key design issues addressed was Subthreshold-current reduction,

especially at room-temperature operation.

Horiguchi et al (1993) proposed a Switched-Source-Impedance

(SSI) CMOS circuit, as a means of reducing the exponential increase of

subthreshold current with threshold-voltage scaling. Inserting switched

impedance at the source of a MOS transistor reduces the standby subthreshold

current of giga scale LSI's operating at room temperature by three to four

orders of magnitude and suppresses the current variation caused by threshold

voltage and temperature fluctuations. The scheme was applicable to any

combinational and sequential CMOS logic circuits as long as their standby

node voltages are predictable.

Takashima et al (1994) proposed standby/active mode logics for

1 Gb/4 Gb DRAMs and battery operated memories. The circuits realize

sub l-V supply voltage operation with a small 1-

leakage current, by allowing 1mA leakage in the active cycle. First logic was

composed of logic gates using dual threshold voltage transistors, and it can

achieve low standby leakage by adopting high threshold voltage transistors

38

only to transistors which cause a standby leakage current. Second logic uses

dual supply voltage lines, and reduces the standby leakage by controlling the

supply voltage of transistors dissipating a standby leakage current.

Gustavo Tellez et al (1995) investigated activity driven clock trees

to reduce the dynamic power consumption of synchronous digital CMOS

circuits. Sections of an activity-driven clock tree can be turned on/off by

gating the clock signals during the active/idle times of the clocked elements.

A method of obtaining the switching activity patterns of the clocked circuits

during the high level design process and three activity driven problems was

formulated. The objective of these problems was to minimize system's

dynamic power consumption. An approximation algorithm based on recursive

matching to solve the clock tree construction problems was also proposed.

Shibata et al (1995) presented low power circuit techniques for

size-configurable SRAM macro cells with wide range of operating frequency.

Synchronous specification was employed to drastically reduce the power

dissipation for low frequency applications. Dynamic circuits applied to bit

lines and sense circuits contributed to the reduction of power dissipation. To

enhance the high-end limitation of operating frequency, a latch type fast sense

circuit and an accurate activation timing control technique for size-

configurable memory macro cells was proposed, and a special CMOS level

input buffer was devised to enable the minimum cycle time of fast

synchronous memory macro cells.

Mutoh et al (1995) were the pioneers of Multi Threshold voltage

CMOS (MTCMOS) circuits. Here, low-threshold (low Vth ) transistors that

are fast and leaky are used to implement speed-critical logic. High threshold

(high Vth) devices that are slower, but have low subthreshold leakage, are

used as sleep transistors. Multi threshold voltage circuits have degraded noise

immunity when compared to standard low threshold voltage circuits. The

39

sleep transistor has to be sized properly to decrease its voltage drop when it is

on. A sleep control scheme was introduced for efficient power management.

Since data retention was required in standby mode, this work was extended,

and an extra high Vth memory circuit was introduced by Shigematsu et al

(1997).

Iman et al (1996) present POSE, a Power Optimization and

Synthesis Environment for designing low power digital circuits at the logic

level. POSE provides a unified framework for specifying and maintaining

power relevant circuit information. Power optimization techniques were

developed with area-power trade-offs. Low power optimization algorithms

provided in POSE are classified into three categories: Algebraic Restructuring

Techniques, Node Simplification, and Technology Mapping. Experimental

results show an average reduction of power consumption by 29% at the

expense of area increase by 30% on average. The delay of the circuits

increased by 4%. This clearly shows a trade-off between area and power,

while the circuit delay is not much affected.

Another approach of MTCMOS is to use high threshold voltage

devices on noncritical paths to reduce the leakage power while using low

threshold devices on critical paths so that the circuit performance is

maintained. This technique has been called Dual-Threshold CMOS

(DTCMOS) and proposed by Chen et al (1996). It is an integer linear program

to choose an optimal assignment of dual Vth for all of the transistors or gates

in the circuit. Various heuristic algorithms are proposed to solve this problem

for big circuits. Dual-Threshold CMOS is a very effective approach for

leakage reduction in both active mode and standby mode. More than 80% of

leakage power savings have been reported. Compared with other leakage

reduction techniques, it requires very little modification of the circuit design.

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It can also be combined with transistor sizing and multiple VDD to get more

leakage power savings.

Halter et al (1997) proposed a design technique that can be used

during logic design in order to reduce the leakage current and power. They

in use, which is becoming a common approach for low power design. The

proposed design changes consist of minimal overhead circuitry that puts the

circuit into a low leakage standby state, whenever it goes into standby, and

allows it to return to its original state when it is reactivated.

Assaderaghi et al (1997) in dynamic threshold CMOS (DTMOS),

the threshold voltage is altered dynamically to suit the operating state of the

circuit. It can be achieved by tying the gate and body together. DTMOS can

be developed in bulk technologies by using triple wells. Doping engineering

is needed to reduce the parasitic components. The supply voltage of DTMOS

is limited by the diode built in potential in bulk silicon technology. The PN

diode between source and body should be reverse biased. Hence, this

technique is only suitable for ultra low voltage (0.6V and below) circuits in

bulk CMOS. Another way for dynamic threshold design is to control the body

bias voltage dynamically through a bias control circuit depending on the

workload of the system. When the workload becomes less, the bias control

circuit will change the body bias to increase the threshold to reduce the

power.

Ye et al (1998) showed

significantly reduces subthreshold leakage, compared to a single off device.

These stacks are series connected devices between supply and ground

(e.g., PMOS stack in NOR or NMOS stack in NAND gates). Their technique

enables leakage reduction during standby mode by input vector activation. It

involves extensive circuit simulations to install a vector at the input of the

41

circuit, so as to maximize the number of PMOS or NMOS stacks with more

than one off device.

Chen et al (1998) performed an analysis of subthreshold leakage

through a stack of N-transistors. A genetic algorithm based technique was

used to determine the bounds for leakage power in various CMOS circuits. As

part of their analysis, they determined a set of test vectors which places

corresponding circuits in the low-power standby mode.

Bobba et al (1999) presents a graph based algorithms for estimating

the maximum leakage power. The leakage power is dependent on the input

vector. This input pattern dependence of the leakage power makes the

problem of estimating the maximum leakage power a hard problem. The

algorithms proposed by Bobba et al (2013) are pattern-independent and do not

require simulation of the circuit. Instead the circuit structure and the logic

functionality of the components in the circuit are used to create a constraint

graph. The problem of estimating the maximum leakage power is then

transformed to an optimization problem on the constraint graph. Efficient

algorithms on the graph are used to estimate the maximum leakage power

dissipated by a circuit.

Wei et al (1999) presented a Mixed-Vth CMOS circuit design

methodology. Kao et al (2000) used MTCMOS for power gating. A method to

size sleep transistors, based on a mutual exclusion discharge pattern principle,

is described. The introduction of extra devices in series with the power

supplies leads to a performance penalty.

Johnson et al (1999) showed that a particular ordering of the inputs

could potentially make use of the well known stack effect technique to reduce

leakage overheads. Since practical circuits do not consist of only a single

transistor stack, a procedure to evaluate the leakage of a CMOS circuit, given

42

a set of logic signal inputs, is explained. They iteratively choose the input

with the largest leakage observability and assign it a value that results in the

smallest leakage. The input combination constructed by this greedy heuristic

was taken as the Minimum Leakage Vector (MLV).

Keshavarzi et al (1999) proposed VTMOS. Variable threshold

CMOS (VTMOS) is a technique, which uses the body bias voltage to change

the threshold of CMOS transistors. It has been reported that reverse body

biasing lowers integrated circuit leakage by three orders of magnitude in a

0.35 m technology. However, it was also shown that the effectiveness of

reverse body bias in lowering leakage decreases as technology scales. This

technology also requires routing the body grid, which will add to the overall

chip area.

Powell et al (2000) proposed the Dynamically ResIzable instruction

cache (DRI i-cache), an integration of circuit and architecture techniques.

Considering an SRAM cell, Powell et al. showed the effect of NMOS gated-

VDD and PMOS gated VDD in terms of energy, speed and area.

Instead of using low VDD for active mode and high VDD for standby

mode, the power supply can be cut-off during the standby state and resumed

during the active mode by Kawaguchi et al (2000). This is called power cut-

off technology. Two different power cut-off CMOS technologies have been

proposed: Super Cut-off CMOS (SCCMOS) and Zigzag Super Cut-off CMOS

(ZSCCMOS) (Min et al 2003). The SCCMOS scheme was proposed and

demonstrated to achieve high speed and low standby current with sub 1V

supply voltages. A problem associated with this scheme is that data can get

lost during the long sleep period due to the leakage current. SCCMOS also

suffers from a long wake-up time and a high current peak at the sleep-to-

active transition. This is due to the virtual VDD node being discharged

43

(charged) during the sleep period and being charged (discharged) when

returning to active mode.

Amrutur et al (2001) presented a low power decoder design that

involves choosing the optimal circuit style and figuring out their sizing,

including adding buffers if necessary. Two simple heuristics for sizing of real

decoder with integer stages were examined. Amrutur et al (2001) evaluated a

simple technique to reduce power, namely, reducing the sizes of the inputs of

the word drivers, while sizing each of the subchains for maximum speed, and

found that it provided an efficient mechanism to trade off speed and power.

Narendra et al (2001) used a stack-forcing method to reduce

subthreshold leakage. This is achieved by forcing a non-stack transistor of

width - /

effective method does not affect the input load and the switching power.

However, there is a delay penalty to be incurred as a result of this stack-

forcing. Hence, this technique can be used only on devices in paths that are

non-critical.

Durate et al (2002) presented a survey of leakage minimization

techniques. They list the benefits and limitations of various techniques and

optimizations applied at run time. Pedram et al. give a tutorial of various

representative power minimization techniques at the Register Level (RTL)

(Abdollahi 2006).

Anis et al (2002) presented two techniques for efficient gate

clustering in MTCMOS circuits by modeling the problem via Bin-Packing

(BP) and Set-Partitioning (SP) techniques. An automated solution was

presented, and both techniques were applied to six benchmarks to verify

functionality. Both methodologies offer significant reduction in both dynamic

and leakage power over previous techniques during the active and standby

44

modes respectively. Furthermore, the SP technique takes the circuit's routing

complexity into consideration which is critical for Deep Sub-Micron (DSM)

implementations.

Tschanz et al (2003) incorporated the power cut-off technology

with the clock-gating scheme for leakage power reduction in a microprocessor.

The gated-clock signal is used to synchronize the power cut-off controls of

the respective circuit blocks, so that not only dynamic power but also leakage

power can be reduced when the circuit block is in standby mode.

Abdollahi et al (2003) presented a precomputation based guarding

methodology for reducing both dynamic and static power consumption in

CMOS VLSI circuits. Precomputation logic duplicates part of the logic by

precomputing the circuit output values, one clock cycle before they are

required. It is a method in which some inputs of a circuit are frozen, while

some smaller circuit computes the output values. Unlike precomputation,

guarded logic does not require synthesis of additional logic to implement the

shutdown mechanism. It exploits the existing signals in the original circuit,

and no changes to the original combinational circuitry are needed. Guarded

evaluation involves determining which parts of a circuit are computing useful

results and which parts are computing results that are not used. The

unnecessary portions can be shut off. If the guarding signal itself switches

frequently, the power dissipation of the switching sleep transistors may

outweigh the power saving due to guarding. Hence, in their work, Abdollahi

et al (2003) proposed a method to generate a new guard signal, based on the

most recent values of the original guarding signal.

Min et al (2003) proposed Zigzag technique to reduce the wake-up

cost of the sleep transistor technique. The zigzag technique reduces the wake-

up overhead by choosing a particular circuit state (e.g., corresponding to a

state chosen, turning off the Pull-Down

45

Network (PDN) for each gate whose output is high while conversely turning

off the Pull-Up Network (PDN) for each gate whose output is low.

Calhoun et al (2003) identified sneak leakage paths and present a

set of design rules. They partition the Configurable Logic Blocks (CLBs) of

the target Field Programmable Gate Array FPGA architecture into four sleep

regions: A Look-Up Table (LUT) region, an adder region, a flip-flop region

and a control circuitry region. The configuration bits tell each CLB how to

organize its internal parts at run time. These configuration bits also act as

control signals for the sleep regions. Minimal control logic is required for

deciding when to assert the sleep signal for each local sleep region. The

FPGA architecture inherently avoids many interfacing problems for sleep

regions by using transmission gate multiplexers.

Hanchate et al (2004) proposed a technique called LECTOR for

designing CMOS gates, which cuts down leakage current by adapting the

technique of effective stacking of transistors. Automated sizing of sleep

transistors can be done using the technique illustrated by Lakshmikanthan

et al (2004). Narendra et al (2004) present a full-chip subthreshold leakage

current prediction model.

Abdollahi et al (2004) proposed a technique to directly control the

value of internal nodes to reduce leakage. They add PMOS and NMOS

transistors to some of the gates in the circuit to increase the controllability of

the internal signals of the circuit and decrease the leakage current of the gates

Satisfiability (SAT) is then used to

formulate the problem, which is subsequently solved using efficient off-the-

shelf SAT-solvers (Aloul 2002). More precisely, given a combinational

circuit description, first a boolean network is constructed, which computes the

total leakage of that circuit. From this Leakage Computing Network (LCN), a

set of Boolean clauses that capture the leakage current of the original circuit.

46

A SAT-solver is then used to find the Minimum Leakage Vector (MLV). The

time complexity of the SAT solver, however, is exponential in the worst case.

Kursun et al (2004) evaluated the subthreshold leakage current

characteristics of domino logic circuits .It was shown that a discharged

dynamic node is preferred for reducing leakage current in a dual-Vth circuit.

Alternatively, a charged dynamic node is better suited for lower leakage in a

low-Vth circuit. The keeper and output inverter have to be sized in a dual Vth

domino circuit with a high Vth keeper, in order to provide noise immunity

similar to that of a low Vth domino logic circuit. Kursun et al (2004) employs

these techniques, coupled with sleep transistor switches, for placing idle

domino circuits in a low leakage state. A high Vth NMOS sleep transistor is

connected in parallel with the dynamic node of domino logic circuits. In the

standby mode of operation, the pull-up transistor of the domino circuit is off,

while the NMOS sleep transistor is turned on. The dynamic node of the

domino gate is discharged through the sleep transistor, thereby significantly

reducing the subthreshold leakage current.

Yang et al (2005) presented an accurate macro model for the

stacking effect on leakage power for sub-100 nm circuits. Bhunia et al (2005)

presented a novel circuit technique to minimize power dissipation in

combinational circuits. This is achieved by inserting extra supply gating

transistors in the supply to ground paths of the circuit. It was assumed that the

sleep/wake up signals to control these gating transistors are generated from an

external power management unit. In the active mode, the gating transistor is

ON and the circuit behaves as usual.

The sleepy stack technique by Park (2005) has a structure merging

the forced stack technique and the sleep transistor technique. When applying

the sleepy stack technique, each existing transistor is replaced with two half

sized transistors and add one extra sleep transistor. The leakage reduction of

47

the sleepy stack structure occurs in two ways. First, leakage power is

suppressed by high Vth transistors, which are applied to the sleep transistors

and the transistors parallel to the sleep transistors. Second, two stacked and

turned off transistors induce the stack effect, which also suppresses leakage

power consumption. By combining these two effects, the sleepy stack

structure achieves ultra low leakage power consumption during sleep mode

while retaining exact logic state. The price for this, however, is drastically

increased area. And the major disadvantage of having controlling circuitry for

sleep transistors is also carried here. As the sleep transistors are bulky, hence

increases the dynamic power.

To achieve low power benefits without compromising performance,

static and dynamic scaling of supply voltages can be applied. Static supply

scaling is a multiple supply approach in which critical and non critical paths

are clustered and powered by higher and lower supply voltages, respectively.

Since the speed requirements of the non critical clusters are lower than the

critical ones, the supply voltage of non-critical clusters can be lowered

without degrading performance. Hillman (2005), in his work, designs an

SOC, using clusters of components characterized at various voltage levels.

Whenever a node from a low voltage cluster needs to drive a node of a high

voltage cluster (or vice-versa), a level conversion is needed at the interface.

The secondary voltages may be generated off-chip (Wei 1999) or on-chip

(Rajapandian 2005).

Yuan et al (2006) applied Input Vector Control (IVC) techniques

for leakage power reduction. IVC utilizes the transistor stack effect in CMOS

gates by applying a Minimum Leakage Vector (MLV) to the primary inputs

of combinational circuits during the standby mode. The MLV problem is NP-

Complete. Typically, an exhaustive circuit simulation is performed for all

input patterns, to find the pattern with the minimum leakage current.

48

However, this approach is not practical for large circuits. In their work, Yuan

et al (2006) replaced internal gates in their worst leakage states by other

library gates, while maintaining the correct functionality of the circuit during

the active mode. A divide-and-conquer approach is presented that integrates

gate replacement and an optimal MLV searching algorithm for tree circuits.

Design issues and implementation strategies for building on-chip

dc-dc voltage level shifting circuits are presented by Lakshmikanthan et al

(2006). Dynamic supply scaling is much harder to generate, but saves the cost

of using two supply voltages by adapting the single supply voltage to

performance demand.

Elkarablieh et al (2006) present a synthesis technique for reducing

leakage power, based on signal controllability chains. Local re-synthesis of a

large fan-in gate into smaller sleep-embedded gates that achieve the same

functionality is suggested. The sleep signals controlling the corresponding

smaller gates could be judiciously picked from the pattern combination at the

input of the original (large fan-in) gate. Signal controllability measures

predict how controllable the output of a circuit is. This idea is used in their

work to determine which signal should be used to place some portion of the

circuit in sleep mode. They define controllability as the length of the chain of

gates driven by a signal whose output is controlled by the value of the signal.

The idea is basically to assign sleep signals using lines with the longest

controllable chains. A mathematical model for the estimated power saving is

presented.

Sleepy Keeper by Kim (2006) is a better leakage reduction

technique compared to sleepy stack. It gives an excellent alternate for sleepy

transistors to be replaced to one transistor. Sleep transistors are connected to

the circuit along with NMOS connected to VDD and PMOS connected to Gnd.

49

The sleep transistor is turned on when the circuit is active and turned off when

the circuit is in idle state with the help of sleep signal. This creates virtual

power and ground rails in the circuit. Hence, there is a significant detrimental

effect on the switching speed when the circuit is active. The identification of

the idle regions of the circuit and the generation of the sleep signal needs an

additional hardware capable of predicting the circuit states accurately, thereby

increasing the area requirement of the circuit. This technique creates a

negative effect when the circuit is operating in active mode in terms of the

circuit performance.

Agarwal et al (2006) presented a technique for power gating with

multiple sleep modes. In the standby mode, the gating transistor is turned off,

thereby cutting off power to the circuit. Abdollahi et al (2007) considered

another important objective, which is limiting the number of sleep transistors.

Lu et al (2007) combined dual-Vth assignment with path balancing

using integer linear programming to reduce both leakage and dynamic glitch

power simultaneously. Thus, dual-threshold CMOS is widely used in modern

CMOS fabrication lines.

Tanabe et al (2007) have focused on the optimization of low power

operation SRAM circuit for 32 nm node with TCAD optimizing the

relationship among margin, leakage current and access time. To conduct the

circuit design principle, they defined the new quality factor and evaluated the

32nm SRAM performance with this defined formula.

Lakshmikanthan (2007) proposed a novel leakage current

minimization technique for CMOS VLSI circuits. A combination of high-

threshold and standard-threshold sleep transistors embedded within the

CMOS topology was used in voltage balancing of the Pull -Up Network

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(PUN) as well as the Pull-Down Network (PDN), thereby shutting them off

and minimizing leakage loss.

David Levacq et al (2007) presented a new CMOS digital storage

device, that was developed based on the combination of two reverse biased

composite CMOS diodes, each of them featuring ultra-low leakage and a

negative impedance characteristic in reverse mode. The biasing of MOS

transistors in very weak inversion, with negative gate-to-source voltages,

results in a static current that lies in orders of magnitude below that of

conventional cross-coupled CMOS inverters. Based on the device, a

7-transistors SRAM cell was presented. Modeling, simulation and

experimental characterization of the main properties of this cell was reported

for a 0.13µm partially depleted SOI CMOS process.

Chowdhury et al (2008) proposed an alternate power gating

structure for better reduction of leakage currents, especially for low-power,

high-performance portable devices. The proposed technique maintains an

intermediate power saving state as well as the conventional power cut-off

state.

Gjanci et al (2008) presented an analysis of ground bounce due to

power mode transition in power gating structures. An innovative power gating

approach was proposed, which in addition to targeting maximum reduction of

major leakage currents provided a way to control ground bounce during

power mode transition. The proposed power gating technique was having an

additional intermediate HOLD mode along with conventional CUTOFF and

RUN modes. Its stepwise turning on feature provided higher reduction of the

magnitude of peak current and voltage glitches in the power distribution

network as well as the minimum time required to stabilize power and ground.

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Jaehyun Kim et al (2009) have proposed mixed Vth flip-flops,

which have a substantially lower leakage than conventional low Vth flip-flops,

at the cost of an increase in delay, either in the setup time or in the clock-to-Q

delay but not in both. This is achieved without any increase in area, due to the

careful selection of transistors for the high Vth implementation. This concept

is general and any kind of conventional static flip-flop could be transformed

to a mixed Vth flip-flop. Jaehyun Kim et al (2009) have also presented a

heuristic algorithm that substitute mixed Vth flip-flops for conventional

flip-flops as well as allocating high or low Vth to each combinational gate. In

addition, the mixed Vth flip-flops and the allocation algorithm were both

extended to the use of three Vth s.

Vaibhav Neema et al (2010) have presented an efficient method for

reducing leakage power in VLSI design as compared to established methods

called VSECURE (VLSI Standby Subthreshold Leakage Current Reduction

Technique). The VSECURE technique results in ultra low static and dynamic

power consumption without floating output state. Furthermore, the proposed

methods is applicable to single and multiple threshold voltages. With

application of dual-Vth, VSECURE found to be more efficient approach to

reduce leakage current with the negligible increase in delay while

simultaneously providing non-floating output login in sleep mode.

Masud et al (2011) proposed an alternative dual-Vth reduced power

gating structure for better reduction of leakage currents, especially for low

power and high performance portable devices. The proposed technique

maintains an intermediate power saving state as well as the conventional

power cut off state. In addition, it was demonstrated that the proposed

technique provides a way to control ground bounce during power mode

transition. Due to the presence of the intermediate state, its stepwise turning

on feature will provide higher reduction of the magnitudes of peak current and

52

voltage glitches in the power distribution network as well as the minimum

time required to stabilize power and ground.

Jianping Hu et al (2011) have presented new leakage power flip-

flops with power gating scheme for ultra low power systems. The flip-flops

are realized based on CMOS ratioed latches with the master-slave structure.

Dual-Threshold CMOS (DTCMOS) and channel length biasing techniques

are used for the flip-flops with power gating scheme to reduce leakage power

dissipations.

Zhang et al (2011) presented a review of three major leakage

current components of SRAM cells and also discussed some of the leakage

current reduction techniques including body biasing, source biasing, dynamic

VDD, negative wordline, and bitline floating schemes for SRAM cells. All of

them are achieved by controlling different terminal voltages of the SRAM cell

in standby mode. On the other hand, performance loss occurs simultaneously

with leakage saving.

Leela Rani et al (2012) proposed Galeorstack technique which

combines the Galeor and Forced stack techniques. As it combines the features

of the above mentioned techniques, two gated leakage transistors are

introduced between pull up and pull down networks with high threshold

voltage, then stack effect is added to pull up and pull down networks by

dividing each transistor in to half size transistors. As more stack effect can be

introduced, due to high threshold voltage gated leakage transistors and half

size stacked transistors, ultimately more leakage current reduction was

achieved.

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Sanjay Singh et al (2012) analyzed the leakage power behavior in

pulse triggered flip flop. By analyzing the leakage path of flip flops a method

was proposed to reduce the leakage power of flip flops.

Pandey et al (2013) proposed two new XOR circuits to reduce

leakage power consumption and active mode power consumption as

compared to standard XOR circuits. First proposed XOR circuit utilizes

hybrid N- and P-type transistors in the pull-down network with all transistors

are low threshold voltage. Second proposed XOR circuit utilizes hybrid N and

P type transistors in the pull-down network with dual threshold voltage

transistors.

Shyam Akashe et al (2013) focused on the impact of gate leakage

on 7 transistors based static random access memory. Three techniques for

reducing gate leakage currents and sub threshold leakage currents were

examined. In first technique, the supply voltage is decreased. In the second

techniques the voltage of the ground node is increased. While in third

technique the effective voltage of 0.348V and 0.234V are observed across

SRAM cell. In all the techniques the effective voltage across SRAM cell is

decreased in stand-by mode using a dynamic self controllable voltage level

switch.

A high speed low active and leakage power SRAM memory was

developed for mobile processors by Jiafeng Zhu et al (2013). The sleep

controller for cell arrays and power cut-off for peripheral circuits are used for

low leakage current in standby mode, while the leakage power in active mode

is decreased by about 4% using the distributed decoders with virtual ground

54

control. In addition, the read and write divided timing control is adopted to

reduce the write current.

Hu et al (2014) shows a trend of reduction in leakage current by

scaling down the spacing between the edge termination and the Schottky

contact in the External Edge Terminated-SBD (EET-SBD). By embedding the

edge terminations inside the anode region named Gated Edge Terminated-

SBD (GET-SBD), four orders of magnitude reduction in leakage current had

been observed experimentally .

Most of the techniques analyzed above are not complete for RTL

synthesis of low power circuits. They require an external controller that

sequences the working of the entire circuit. The controller should be able to

identify and differentiate between portions of a circuit that are active

generated automatically to synchronize the operation of the datapath (design),

thereby switching devices back and forth between active and standby modes

of operation. This sleep/enable controller generation is assumed to be present

in most of the prior research work.

2.4 OBJECTIVES OF THE PRESENT STUDY

A well known previous technique called the sleep transistor

technique cuts off VDD and/or Gnd connections of transistors to save leakage

power consumption. However, when transistors are allowed to float, a system

may have to wait a long time to reliably restore lost state and thus may

experience seriously degraded performance. Therefore, retaining state is

crucial for a system that requires fast response even while in an inactive state.

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This research work provides new VLSI techniques that achieve ultra-low

leakage power consumption while maintaining logic state, and thus can be

used for a system with long inactive times but a fast response time

requirement.

In this dissertation, (i) two low-power techniques, namely the

Sleepy-pass gate technique and the DT-LECTOR (Dynamic Threshold-

LEakage Control TransisTOR) technique for static power reduction and (ii) a

new set of low power logic gates with reduced transistor count for dynamic

power reduction are presented. The proposed techniques provide new

weapons to designers whose primary concern is low power.

2.5 SUMMARY

Among the technologies described above, Dual-Threshold CMOS,

DTMOS, and all of the device level techniques are effective for active

leakage reduction. Most of the other schemes only work for standby leakage

reduction. However, the dual-threshold technique does not reduce the leakage

on critical paths. Thus, it does not help much for timing optimized circuits,

whose paths are usually well balanced. Thus, more effective active leakage

reduction techniques are still very desirable. This thesis proposes two new

leakage reduction techniques, called the Sleepy-pass gate and DT-LECTOR

followed by logic gates with reduced transistor count respectively.