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Chapter 2
REALIZATION OF FPGA BASED Q-FORMAT ARITHMETIC LOGIC
UNIT FOR POWER ELECTRONIC CONVERTER APPLICATIONS
In this chapter, analysis of FPGA resource utilization using QALU,
and is compared with the existing implementations of integer fixed point
format for data representation is presented. The analysis is carried out
through simulation of QALU using ModelSim 5.7 and synthesis using
Xilinx 9.2i. Further, it also includes the validation of possibility of single
chip implementation in FPGA for generating PWM pulses using VSI fed
induction motor.
2.1. Introduction
The power electronic converter control realization using Q-Format
through FPGA requires the following concepts:
i. Digital data representation using fixed point formats [129-130].
ii. FPGAs and the developments tools [131-139].
In the hardware implementation point of view, fixed point
representations have been used in the computation which yields the
simple hardware, there by the area as well as cost of FPGA is reduced.
Due to the flexibility of simple hardware, the fixed point processors are
commonly used in applications where the accuracy is not a constraint. In
such applications, the designer has to use the proper signal processing
to achieve the required accuracy.
18
The signal processing is a key issue in the performance of a digital
system. In the existing FPGA based PWM implementation, integer fixed
point format is used in the signal processing which requires an
additional processor to implement the arithmetic functions [64-70].
Therefore, an efficient VLSI signal processing is necessary to improve the
performances of FPGA in terms of resource utilizations, reduction of
hardware cost and improved accuracy through single chip solution. To
overcome the above limitation, an alternate solution, called QALU using
Q-Format representation has been implemented [28-32, 95,107,129-
131]. The preliminary concepts like FPGA architecture [126-128],
resources and its domain use [5], development tools [132-137], and
design flow [138-139] are discussed in the literature.
2.2. Digital Data Representation by different Formats
The binary representations of numbers used in digital systems are
sign magnitude, one’s compliment, and two’s compliment. In general, 2’s
compliment data representation is used in processors and it is an
efficient way of representing signed numbers [121-122]. The most
commonly used type of data formats are: (i) Fixed Point Representation
(FXPR) [129-130], and (ii) Floating Point Representation (FLPR) [34]. In
case of fixed point processors, the application specific functions are
performed and the final result is stored in accumulator every time at the
end of each arithmetic operation. At last, the Most Significant Bit (MSB)
of accumulator is left shifted by one and is given as an output. In FPGA
19
based implementations, integer fixed point is commonly used for data
representation [27-54, 64-70], whereas FLPR is used in few FPGA based
applications [33]. The FXPR and arithmetic computation is described in
[130].
The arithmetic calculations for the equation (α × β) + are presented
for fixed point format with integer part (Qm), fixed point format with
fractional part (Qn) and fixed point format with integer + fractional part
(Qm.n) in [26,130] and the corresponding error is shown in Table 2.1.
The procedure is presented in Appendix-1.
Table 2.1. Error in arithmetic computation using different formats
Type of data representation error (8 bitarithmetic operation
Fixed point format with integer part (Qm) 0.34975Fixed point format with fractional part (Qn) 0.20525Fixed point format with integer and fractional part (Qm+Qn) -0.02525
In general, the fixed point format data are scaled to integer number,
after completion of arithmetic computation, the Least Significant Bit
(LSB) in the result is truncated. The MSB is taken as the final result. In
case of integer fixed point format Qm, all 16 bit will give the correct
result. Therefore, the entire result (both MSB and LSB) has to be stored
in memory and considered for the successive computation. Hence, this
kind of representation takes more FPGA resources for an acceptable
accuracy and also this is not suitable for single chip implementations. In
fractional fixed Qn point and Qm.n arithmetic functions, the accuracy of
20
final the result is not affected even after truncation of LSB. Finally, Qn
and Qm.n representation need one WL and Qm needs two WLs which
results, increased in FPGA resource utilization.
2.2.1. Error and Area Analysis in Q-Format Representation
In Table 2.1, the error in 8 bit arithmetic computation in fixed point
formats, compared with floating point format is shown. From the
analysis, Q-Format arithmetic gives improved accuracy in arithmetic
computation compared to traditional fixed integer and fractional
arithmetic. In 16 bit format with proper scaling, the error is still reduced
to negligible level. Therefore, the fixed point representation Qm+Qn (Q-
Format) is used to implement PEC control algorithm in a single FPGA.
In integer multiplication, the multiplication of two 8 bit data will give
result in 16 bit. Therefore a 16 bit register is needed to store the result
where as in fractional / Qm.n Format with proper scaling, the result is in
8 bit format and therefore, it needs only an 8 bit register to store the
results. Hence, the Qm.n Format based signal processing will reduce the
FPGA resource or area utilization [28-32, 95, 107].
2.2.2. Advantages of Q- Format Representation
Arithmetic computations using Q-Format representation in FPGA
gives the following advantages:
i. Occupies less FPGA resources i.e. less area in the chip [28-32, 95,
107].
21
ii. From the analysis of multiplication, the Q-Format gives improved
accuracy for the same number of bits in integer approximation and
fixed fractional Format. In FPGA implementation, Q-Format with
representation and proper dynamic range gives improved accuracy
[28-32, 95, 107].
iii. Multiplications of two 8 bit numbers with proper scaling requires one
8 bit register to store the result [29, 95], whereas, in integer format it
requires a 16 bit register which results in increased FPGA area for
arithmetic operations.
2.3. Realization of Q-Format ALU in FPGA
In most of FPGA based PEC control implementations, FXPR is used to
compute a part of algorithm while the major computation carried by a
DSP. In this Thesis, fixed point implementation with both integer and
fractional part Qm.n is considered to implement PWM algorithm in a
single chip. The data is converted to its equivalent Q- Format in the
representation as well in arithmetic calculations. This computation is
carried out by QALU which consists of arithmetic computation functions
such as adder, subtractor and multiplier. The QALU is developed as a
library function and it is included in the project directory using the
reported literature [28, 95, 107].
The block diagram and the functional flow of QALU is shown in Fig.
2.1 and Fig. 2.2 respectively. The functional flow for addition and its
pseudo code are shown in Fig. 2.3 and Fig. 2.4 respectively.
22
Fig. 2. 1. Functional block diagram of QALU
QADD/QSUB QSQRT
QMULT
QMOD
QDIVIDE
QSQR
QALUCONTROLLER
Start
Find the length of the integer part
Find the length of the fractional part
Represent the number in Qm.n format
Stop
Fig. 2. 2. Functional flow of QALU
23
Pseudo code:
Functional unit name: QADDInput: two numbersOutput: addition result of two numbersSteps:
1. Convert the given tow numbers into Qm.n format
2. If both the numbers are in same Qm.n format then perform the signed
addition else Shift and sign extend to align the decimal places.
3. Setting the overflow bit, if any overflow occurs
End
Fig. 2.4. Pseudo code for addition in QALU
Start
Read the numbers
Is both thenumbers are in
same Qm.n format
Perform signed addition
Shift and sign extend to align the decimal places
Setting overflow bit if any overflow occurs
No
Yes
Stop
Fig. 2. 3. Functional flow chart of Addition in QALU
24
2.3.1. Q-Format multiplication
Since multiplication plays a major role in arithmetic computations, its
basics are discussed in this section and the detailed explanation is given
in Appendix- I. Signal processing in fractional form has the specific
properties. The multiplication of data in the range of -0.999 to +0.999,
the resultant product will not have overflow. The common way for
lowering the operand is called scaling, i.e. operand is divided by the
adequate constant [29, 95].
The functional flow for multiplication and its pseudo code are shown
in Fig. 2.5 and Fig. 2.6 respectively
Fig. 2.5. Functional flow chart of Multiplication in QALU
Start
Read the numbers
Perform signed multiplication
Stop
Integer Part: QIproduct=QImultiplier + QImultiplicandFractional Part: QFproduct=QFmultiplier + QFmultiplicand
Adjust the resultant Qm.n format to the requirement
25
2.3.2. Simulation Results of QALU
The proposed QALU using Q-Format and its application to power
electronic converter control has been simulated using ModelSim 5.7 and
implemented using Xilinx 9.2i. The Q-Format data representation and
the arithmetic operations of addition and multiplication has been
developed and simulated.
The simulation results for addition and multiplication using integer
fixed and Q-Format has been obtained for unsigned and signed data
inputs. The Q-Format implementation has been validated by the
simulation and implementation of an arithmetic operation
(multiplication). The implementation report of multiplication using
integer fixed arithmetic and Q-format is shown in Table 2. 2 and Table
2. 3 respectively. The simulation result for multiplication is shown in
Fig. 2. 7.
Pseudo code:
Functional unit name: QMULTInput: two numbersOutput: multiplication of two numbersSteps:
1. Convert the given tow numbers into Qm.n format
2. Perform the signed multiplication
3. Adjust the resultant Qm.n format according to the requirement(either
16/32-bit)
End
Fig. 2.6. Pseudo code for multiplication in QALU
26
Table 2. 2. Implementation report of multiplication using integer fixed
arithmetic
Logic Utilization Used Available Utilization
Number of 4 input LUTs 94 4, 896 2%
Number of occupied Slices 50 2, 448 2%
Number of Slices containing only related logic 50 50 100%
Total Number of 4 input LUTs 96 4, 896 2%
Number of bonded IOBs 64 158 40%
Number of MULT18X18SIOs 3 12 25%
Total equivalent gate count for design 975
Table 2. 3. Implementation report of multiplication using Q-Format
arithmetic
Logic Utilization Used Available Utilization
Number of 4 input LUTs 30 4, 896
27
From the simulations and synthesis report, the multiplication of two
unsigned data 0.25 and 0.75 is 0.1875 which is the actual result. From
the results shown in Fig. 2.31, the result achieved using Q- Format is
0.1875 which is the actual result. For the same data the result achieved
from integer fixed point format is 0D00H. The actual result evaluated by
the digital controller is 0.203125.
In Q- Format, the result is 0.1875.
In integer fixed point format, the result is 0.203125.
The error is evaluate as
0.1875 -0.203125 = -0.015625 (-1.56% for one multiplication operation)
This procedure utilizes more resources in the FPGA.
2.4. Realization of QALU based PWM control through FPGA
In order to analyze resource utilization in FPGA and to validate the
possibility of single chip implementation of PWM, QALU based SVPWM is
simulation using ModelSim 5.7 and synthesis using Xilinx 9.2i are
considered.
The practical feasibility of QALU for PEC control is verified by
applying to SVPWM generation. The SVPWM patterns have been obtained
for different fs and fo. The result for SVPWM pulse patterns in 6 sectors
with fs=20 kHz is shown in Fig. 2.8. The SVPWM patterns have been
generated using the proposed Q-Format based signal processing.
28
2.4.1. Experimental Results
The Experimental setup for QALU based SVPWM controller fed three
phase VSI is shown in Fig. 2.9. The experimentation has been carried out
with the FPGA hardware SPARTAN XC3S400PQ208 from Xilinx. Inc. The
hardware setup consists of FPGA, three phase bridge inverter with
IGBTs, bridge rectifier to supply DC voltage, opto isolator, pulse driver
and induction motor. In the experiments, the fo has been varied from 0.3
Hz to 50 Hz and the fs is varied from 1 kHz to 15 kHz, and the PWM
switching patterns are achieved. The results for PWM output in the
different channels are obtained and the PWM patterns in the channels
P1-P4 are shown in the Fig. 2. 10. The three phase inverter output wave
forms with varying fo of 15 Hz to 50 Hz and 1.157 kHz to 12.28 kHz
varying fs is obtained. The result of the inverter output line to line voltage
is shown in Fig. 2. 11.
Fig. 2. 8. SVPWM waveforms in 6 sector with fs =20 kHz
29
Fig. 2.9. Experimental setup of the Q-Format ALU applied to FPGA-SVPWM controller fed induction motor
Induction motorFPGA
Power module
Driver circuit
Displacement between two voltage waves
50 V
/ d
iv
20 ms / div
Fig. 2. 11. Inverter output voltage, U Y-B and U B-R Line to linevoltage: f0 = 20 Hz, fs =12.28 kHz
Pulse P1
Pulse P4
Fig. 2. 10. SVPWM wave form in channels P1 and P4with fs =1.157 kHz
5 V
/ d
iv
25 ms /div
30
2.4.2. Discussions
The existing PWM control in power electronic converters is
implemented using DSP and FPGA technologies. In the conventional
PWM control implementations, the integer fixed point based signal
processing is used which takes more FPGA resources for a processing a
part of algorithm and also it requires an additional controller.
The first feature of QALU is, it performs the arithmetic computations
in the algorithm, and it is possible to implement the PWM controller in a
single FPGA. And also the host processor such as DSP is not required.
Therefore, the system complexity is reduced.
From the simulation and experiments, the practical possibility of
QALU applied to a PEC control is verified. The results show that the Q-
Format implementation takes total gate count of 348 and integer fixed
format implementation takes 975. The Q-Format takes less chip
resources and due to this feature the speed of execution will also be
increased. The simulation result for 8 bit multiplication using Q-format
and integer fixed point format is presented in Fig. 2. 7. It is proved that,
the error in Q-format based operation is zero and in integer fixed point
format, it is -1.56%. Therefore, the accuracy has been increased by Q-
Format when compared to integer fixed format. The PWM modulator with
QALU is implemented and the possibility of practical implementation is
verified.
31
2.5. Conclusion
The preliminary requirements to implement the QALU design such as
digital data representation in different data formats and their arithmetic
computation has been discussed. The advantages of QALU are verified
with simulation and synthesis. The QALU is designed and developed
using VHDL which performs the arithmetic and logic functions in the
algorithm. To facilitate the digital implementation of QALU, the single
chip FPGA implementation has been developed. By employing the QALU,
the algorithm accuracy has been improved as well as the FPGA resource
utilization is tremendously reduced. Due to this superiority, the IP core
designed on FPGA requires less resource and provides improved
accuracy in single chip FPGA implementation compared to conventional
integer fixed point for signal processing. The proposed signal processing
concept and QALU can be used for PEC control applications to generate
the accurate PWM pattern in real time. Moreover, the proposed signal
processing method is more suitable for single chip FPGA and SoC
implementations. The main objectives such as implementation of entire
PWM control in a single FPGA and area efficient digital PWM control is
verified.