Embed Size (px)
Citation preview
Chapter 3 – Combinational Logic Design
Logic and Computer Design Fundamentals
Chapter 3 2
Combinational Circuits
A combinational logic circuit has:• A set of m Boolean inputs,
• A set of n Boolean outputs, and
• n switching functions, each mapping the 2m input combinations to an output such that the current output depends only on the current input values
A block diagram:
m Boolean Inputs n Boolean Output
CombinatorialLogicCircuit
Chapter 3 3
Integrated Circuits
Integrated circuit (informally, a “chip”) is a semiconductor crystal (most often silicon) containing the electronic components for digital gates and storage elements which are interconnected on chip.
Terminology - Levels of chip integration• SSI (small-scale integrated) - fewer than 10 gates
• MSI (medium-scale integrated) - 10 to 100 gates
• LSI (large-scale integrated) - 100 to 1000 of gates
• VLSI (very large-scale integrated) – 1000 to 100s of millions of gates
Chapter 3 4
Technology Parameters
Specific gate implementation technologies are characterized by following parameters:• Fan-in – number of inputs available on a gate
• Fan-out – number of standard loads driven by a gate output
• Logic Levels – signal value ranges for 1 and 0 on the inputs and 1 and 0 on the outputs
• Noise Margin – maximum external noise voltage superimposed on a normal input value that will not cause an undesirable change in the circuit output
• Cost for a gate - a measure of contribution by gate to cost of IC
• Propagation Delay – time required for a change in the value of a signal to propagate from an input to an output
• Power Dissipation – amount of power drawn from power supply and consumed by gate
Chapter 3 5
Propagation Delay
Propagation delay is the time for a change on an input of a gate to propagate to the output.
Delay is usually measured at the 50% point with respect to the H and L output voltage levels.
High-to-low (tPHL) and low-to-high (tPLH) output signal changes may have different propagation delays.
High-to-low (HL) and low-to-high (LH) transitions are defined with respect to the output, not the input.
An HL input transition causes:• LH output transition if gate inverts and
• HL output transition if gate does not invert.
Chapter 3 6
Propagation Delay (continued)
Propagation delays measured at the midpoint between the L and H valuesWhat is the expression for the tPHL delay for:• a string of n identical buffers? • a string of n identical inverters?
IN
OUT tPHL tPLH
tpd 5 max (tPHL , tPLH )
IN OUT
Chapter 3 7
Propagation Delay Example
Find tPHL, tPLH and tpd for the signals givenIN
(vol
ts)
OU
T(v
olts
)
t (ns)1.0 ns per division
Chapter 3 8
Fan-out
Fan-out can be defined in terms of a standard load
• Example: 1 standard load equals the load contributed by the input of 1 inverter.
• Transition time -the time required for the gate output to change from H to L, tHL, or from L to H, tLH
• The maximum fan-out that can be driven by a gate is the number of standard loads the gate can drive without exceeding its specified maximum transition time
Chapter 3 9
Fan-out and Delay
Fan-out loading a gate’s output affects gate’s propagation delay
Example:
• One realistic equation for tpd for a NAND gate with 4 inputs is:
tpd = 0.07 + 0.021 SL ns
• SL is the number of standard loads gate is driving, i. e., its fan-out in standard loads
• For SL = 4.5, tpd = 0.165 ns
Chapter 3 10
Cost
In an integrated circuit:• cost of a gate is proportional to chip areaoccupied by gate
• gate area is roughly proportional to number and size of transistors and amount of wiringconnecting them
• Ignoring wiring area, gate area is roughly proportional to gate input count
• So gate input count is a rough measure of gate cost
Chapter 3 11
Positive and Negative Logic
same physical gate has different logical meanings depending on interpretation of signal levels.Positive Logic• HIGH (more positive) signal levels represent Logic 1
• LOW (less positive) signal levels represent Logic 0
Negative Logic• LOW (more negative) signal levels represent Logic 1
• HIGH (less negative) signal levels represent Logic 0
A gate that implements a Positive Logic AND function will implement a Negative Logic OR function, and vice-versa.
Chapter 3 12
Positive and Negative Logic (continued)
Given this signal level table:
What logic function is implemented?Positive Logic
(H = 1)(L = 0)
Negative Logic
(H = 0)(L = 1)
0 0 0 1 1 10 1 1 1 0 01 0 1 0 1 01 1 1 0 0 0
InputX Y
Output
L L LL H HH L HH H H
Chapter 3 13
Positive and Negative Logic (continued)
Rearranging the negative logic terms to the standard function table order:
Positive Logic
(H = 1)(L = 0)
Negative Logic
(H = 0)(L = 1)
0 0 0 0 0 00 1 1 0 1 01 0 1 1 0 01 1 1 1 1 1
Chapter 3 14
Logic Symbol Conventions
Use of polarity indicator to represent use of negative logic convention on gate inputs or outputs
X
CKTXY
Z
Logic Circuit
X
LLHH
Y
LHLH
Z
LHHH
YZ
Positive Logic Negative Logic
XY
Z
Chapter 3 15
Design Procedure
1. Specification• Write a specification for the circuit
2. Formulation • Derive a truth table or initial Boolean equations
that define the required relationships between the inputs and outputs
3. Optimization• Apply 2-level and multiple-level optimization
• Draw a logic diagram or provide a netlist for the resulting circuit using ANDs, ORs, and inverters
Chapter 3 16
Design Procedure
4. Technology Mapping
• Map the logic diagram or netlist to the implementation technology selected
5. Verification
• Verify the correctness of the final design
Chapter 3 17
Design Example
1. Specification • BCD to Excess-3 code converter
• Transforms BCD code for the decimal digits to Excess-3 code for the decimal digits
• BCD code words for digits 0 through 9:
4-bit patterns 0000 to 1001
• Excess-3 code words for digits 0 through 9:
4-bit patterns consisting of 3 (binary 0011) added to each BCD code word
• Implementation:
multiple-level circuit
NAND gates (including inverters)
Chapter 3 18
Design Example (continued)
2. Formulation• Conversion of 4-bit codes can be most easily
formulated by a truth table
• Variables- BCD:A,B,C,D
• Variables- Excess-3W,X,Y,Z
• Don’t Cares- BCD 1010to 1111
Input BCD A B C D
Output Excess-3 WXYZ
0 0 0 0 0 0 1 10 0 0 1 0 1 0 00 0 1 0 0 1 0 10 0 1 1 0 1 1 00 1 0 0 0 1 1 10 1 0 1 1 0 0 00 1 1 0 1 0 0 10 1 1 1 1 0 1 01 0 0 0 1 0 1 11 0 0 1 1 1 0 0
Chapter 3 19
Design Example (continued)
3. Optimizationa. 2-level using
K-mapsW = A + BC + BDX = C + D + BY = CD + Z =
B
C
D
A
0 1 3 2
4 5 7 6
12 13 15 14
8 9 11 10
1
11
1
X X X
X X
X
1
B
C
D
A
0 1 3 2
4 5 7 6
12 13 15 14
8 9 11 10
1
11
1
X X X
X X
X
1
B
C
D
A
0 1 3 2
4 5 7 6
12 13 15 14
8 9 11 10
1 1
1
1
X X X
X X
X
1
B
C
D
A
0 1 3 2
4 5 7 6
12 13 15 14
8 9 11 10
1 1
1
X X X
X X
X
1
1
w
z y
x
B CDBCD
D
Chapter 3 20
Design Example (continued)
3. Optimization (continued)b. Multiple-level using transformations
W = A + BC + BDX = C + D + BY = CD + Z = G = 7 + 10 + 6 + 0 = 23
• Perform extraction, finding factor:T1 = C + DW = A + BT1X = T1 + BY = CD + Z = G = 2 + 4 + 7 + 6 + 0 = 19
B CDBCD
D
B CDCD
D
Chapter 3 21
Design Example (continued)
3. Optimization (continued)b. Multiple-level using transformations
T1 = C + DW = A + BT1X = T1 + BY = CD + Z = G = 19
• An additional extraction not shown in the text since it uses a Boolean transformation: ( = C + D = ):W = A + BT1X = T1 + B Y = CD + Z = G = 2 + 4 + 6 + 4 + 0 = 16!
B CDCD
D
B T1
DT1
CD T1
Chapter 3 22
Design Example (continued)
4. Technology Mapping • Mapping with inverters, 2-input NAND, 2-input NOR, and
2-2 AOI gates A
B
C
D
W
X
Y
Z
A
B
CD
W
X
Y
Z
Chapter 3 23
NAND Mapping Algorithm
1. Replace ANDs and ORs:
2. Repeat the following pair of actions until there is at most one inverter between :a. A circuit input or driving NAND gate output, and
b. The attached NAND gate inputs.
......
......
......
Chapter 3 24
NAND Mapping Example
AB
C
D
F
E(a)
AB
C7
5
1
6
2
4
9
X
Y
38DE
F
(b)
AB
C
D
E
F
(d)
X
5
5
7
6Y
(c)
OI
Chapter 3 25
NOR Mapping Algorithm
1. Replace ANDs and ORs:
2. Repeat the following pair of actions until there is at most one inverter between :a. A circuit input or driving NOR gate output, and
b. The attached NOR gate inputs.
......
...
......
...
Chapter 3 26
NOR Mapping Example
A
B
C
DE
F
(c)
F
A
B
X
C
DE
(b)
AB
C
DE
F
(a)
2
3
1
Chapter 3 27
Programmable Logic Devices
Why programmable logic?
Programmable logic technologies
Read-Only Memory (ROM)
Programmable Logic Array (PLA)
Programmable Array Logic (PAL)
Chapter 3 28
Why Programmable Logic?
Facts:• It is most economical to produce an IC in large volumes
• Many designs required only small volumes of ICs
Need an IC that can be:• Produced in large volumes
• Handle many designs required in small volumes
A programmable logic part can be:• made in large volumes
• programmed to implement large numbers of different low-volume designs
Chapter 3 29
Programmable Logic - Additional Advantages
Many programmable logic devices are field-programmable, i. e., can be programmed outside of the manufacturing environment
Most programmable logic devices are erasable and reprogrammable.• Allows “updating” a device or correction of errors
• Allows reuse device for a different design - ultimate in re-usability!
• Ideal for course laboratories
Programmable logic devices can be used to prototype design that will be implemented for sale in regular ICs.
Chapter 3 30
Technology Characteristics
Permanent - Cannot be erased and reprogrammed
Mask programming
Fuse
Antifuse
Reprogrammable
• Volatile - Programming lost if chip power lost
Single-bit storage element
• Non-Volatile
Erasable
Electrically erasable
Flash (as in Flash Memory)
Chapter 3 31
Programmable Configurations
Read Only Memory (ROM) - a fixed array of AND gates and a programmable array of OR gates
Programmable Array Logic (PAL)Ò - a programmable array of AND gates feeding a fixed array of OR gates.
Programmable Logic Array (PLA) - a programmable array of AND gates feeding a programmable array of OR gates.
Complex Programmable Logic Device (CPLD) /Field-Programmable Gate Array (FPGA) - complex enough to be called “architectures” - See VLSI Programmable Logic Devices reading supplement
PAL is a registered trademark of Lattice Semiconductor Corp.
Chapter 3 32
ROM, PAL and PLA Configurations
(a) Programmable read-only memory (PROM)
InputsFixed
AND array(decoder)
ProgrammableOR array
OutputsProgrammableConnections
(b) Programmable array logic (PAL) device
Inputs ProgrammableAND array
FixedOR array
OutputsProgrammableConnections
(c) Programmable logic array (PLA) device
Inputs ProgrammableOR array
OutputsProgrammableConnections
ProgrammableConnections
ProgrammableAND array
Chapter 3 33
Read Only Memory
Read Only Memories (ROM) or Programmable Read Only Memories (PROM) have:
• N input lines,
• M output lines, and
• 2N decoded minterms.
Fixed AND array with 2N outputs implementing all N-literal minterms.
Programmable OR Array with M outputs lines to form up to M sum of minterm expressions.
Program for ROM or PROM is simply multiple-output truth table
• If 1 entry, a connection is made to the corresponding minterm for corresponding output
• If 0, no connection is made
Can be viewed as a memory with inputs as addresses of data(output values), hence ROM or PROM names!
Chapter 3 34
Example: A 8 X 4 ROM (N = 3 inputs M= 4 outputs )
Fixed "AND" array is a“decoder” with 3 inputs and 8outputs implementing minterms.
Programmable "OR“array uses a single line torepresent all inputs to anOR gate. An “X” in thearray corresponds to attaching theminterm to the OR
Read Example: For input (A2,A1,A0)= 011, output is (F3,F2,F1,F0 ) = 0011.
What are functions F3, F2 , F1,F0 in terms of (A2, A1, A0)?
Read Only Memory Example
D7D6D5D4D3D2D1D0
A2A1A0
ABC
F0F1F2F3
X XX
XX
X
XX
XX
Chapter 3 35
Programmable Array Logic (PAL)
PAL is opposite of ROM, having a programmable set of ANDs combined with fixed ORs.
Disadvantage• ROM guaranteed to implement any M functions of N
inputs. PAL may have too few inputs to OR gates.
Advantages• For given internal complexity, PAL can have larger N and M
• Some PALs have outputs that can be complemented, adding POS functions
• No multilevel circuit implementations in ROM (without external connections from output to input). PAL hasoutputs from OR terms as internal inputs to all ANDterms, making implementation of multi-level circuits easier.
Chapter 3 36
Programmable Array Logic Example
4-input, 3-output PAL with fixed, 3-input OR terms What are equations for F1 through F4?F1 = + F2 = B + AC + ABF3 = F4 =
0 91 2 3 4 5 6 7 8
AND gates inputs0 9
Productterm 1
2
3
4
5
6
7
8
9
10
11
12
F1
F2
F3
F4
I35 C
I25 B
I15 A
1 2 3 4 5 6 7 8
I4
X X
X X
X X X
X X
X
X
X
XX
X
X X
X
X X
B CAA C
Chapter 3 37
Programmable Logic Array (PLA)
Compared to a ROM and a PAL, a PLA is the most flexible having a programmable set of ANDs combined with a programmable set of ORs.
Advantages• PLA can have large N and M permitting implementation of
equations that are impractical for a ROM (because of the number of inputs, N, required)
• PLA has all of its product terms connectable to all outputs, overcoming problem of limited inputs to PAL ORs
• Some PLAs have outputs that can be complemented, adding POS functions
Disadvantage• Often, product term count limits application of a PLA. Two-
level multiple-output optimization reduces the number of product terms in an implementation, helping to fit it into a PLA.
Chapter 3 38
Programmable Logic Array Example
3-input, 3-output PLA with 4 product terms
What are equations for F1 and F2?
Could PLA implement functions without XOR gates?
Fuse intactFuse blown
1
F1
F2
X
A
B
C
C C B B A A 0
1
2
3
4X
XX
X X
X
X
X
X
X
X
X
X
X A B
A C
B C
A B
X
