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Chapter 3 Gate-Level Minimization Chapter 3 Gate-Level Minimization

Chapter 3Gate-Level Minimization Chapter 3 Gate-Level ...eng.uok.ac.ir/daneshfar/DigitalLogicCircuit/ch03-PPT.pdf · Chapter 3 Gate-Level Minimization Department of Electronic Engineering,

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Page 1: Chapter 3Gate-Level Minimization Chapter 3 Gate-Level ...eng.uok.ac.ir/daneshfar/DigitalLogicCircuit/ch03-PPT.pdf · Chapter 3 Gate-Level Minimization Department of Electronic Engineering,

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Chapter 3Gate-Level Minimization

Page 2: Chapter 3Gate-Level Minimization Chapter 3 Gate-Level ...eng.uok.ac.ir/daneshfar/DigitalLogicCircuit/ch03-PPT.pdf · Chapter 3 Gate-Level Minimization Department of Electronic Engineering,

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The Map Method

Complexity of digital circuit complexity of algebraic expression.

A function’s truth-table representation is unique; its algebraic expression is not.

Simplification by algebraic means is awkward (from algorithmic point of view); the map method is straightforward.

Karnaugh map (or K-map) [M. Karnaugh, 1953]A diagram made up of squares each representing one minterm. A pictorial form of the truth table; an extension of the Venn

diagram. A visual diagram of all possible ways a function may be

expressed—the simplest one can easily be identified.

Page 3: Chapter 3Gate-Level Minimization Chapter 3 Gate-Level ...eng.uok.ac.ir/daneshfar/DigitalLogicCircuit/ch03-PPT.pdf · Chapter 3 Gate-Level Minimization Department of Electronic Engineering,

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Two-Variable Maps

Minterms are arranged in the Gray-code sequence. (Why?) Any 2 (horizontally or vertically) adjacent squares differ by exactly 1

variable, which is complemented in one square and uncomplemented in the other.

Page 4: Chapter 3Gate-Level Minimization Chapter 3 Gate-Level ...eng.uok.ac.ir/daneshfar/DigitalLogicCircuit/ch03-PPT.pdf · Chapter 3 Gate-Level Minimization Department of Electronic Engineering,

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Two-Variable Maps

Page 5: Chapter 3Gate-Level Minimization Chapter 3 Gate-Level ...eng.uok.ac.ir/daneshfar/DigitalLogicCircuit/ch03-PPT.pdf · Chapter 3 Gate-Level Minimization Department of Electronic Engineering,

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Three-Variable Maps

Any 2 minterms in adjacent squares that are ORedtogether will cause a removal of the different variable.For example, m5 + m7 = xy’z + xyz = xz (y’+ y) = xz,because y + y’ = 1.

Page 6: Chapter 3Gate-Level Minimization Chapter 3 Gate-Level ...eng.uok.ac.ir/daneshfar/DigitalLogicCircuit/ch03-PPT.pdf · Chapter 3 Gate-Level Minimization Department of Electronic Engineering,

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Example 3-1

Simplify the following function:

Page 7: Chapter 3Gate-Level Minimization Chapter 3 Gate-Level ...eng.uok.ac.ir/daneshfar/DigitalLogicCircuit/ch03-PPT.pdf · Chapter 3 Gate-Level Minimization Department of Electronic Engineering,

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Example 3-1

Page 8: Chapter 3Gate-Level Minimization Chapter 3 Gate-Level ...eng.uok.ac.ir/daneshfar/DigitalLogicCircuit/ch03-PPT.pdf · Chapter 3 Gate-Level Minimization Department of Electronic Engineering,

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Example 3-2

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Example 3-2

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Example 3-3

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Example 3-3

Page 12: Chapter 3Gate-Level Minimization Chapter 3 Gate-Level ...eng.uok.ac.ir/daneshfar/DigitalLogicCircuit/ch03-PPT.pdf · Chapter 3 Gate-Level Minimization Department of Electronic Engineering,

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Example 3-4

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Four-Variable Map

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Example 3-5

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Example 3-6

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Prime Implicant

A prime implicant (PI) is a product term obtained by combining the maximum possible number of adjacent squares in the map.

An essential prime implicant is one that covers a minterm which is not covered by any other PIs.

PIs can be obtained from the map by combining all possible max number of squares.

Pick the essential PIs that minimize the number of literals.

Page 17: Chapter 3Gate-Level Minimization Chapter 3 Gate-Level ...eng.uok.ac.ir/daneshfar/DigitalLogicCircuit/ch03-PPT.pdf · Chapter 3 Gate-Level Minimization Department of Electronic Engineering,

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Prime Implicant

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Prime Implicant

Page 19: Chapter 3Gate-Level Minimization Chapter 3 Gate-Level ...eng.uok.ac.ir/daneshfar/DigitalLogicCircuit/ch03-PPT.pdf · Chapter 3 Gate-Level Minimization Department of Electronic Engineering,

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Five-Variable Map

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Example 3-7

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3-4 Product of Sums Simplification

The 1’s placed in the squares of the map represent the minterms of the function.

The minterms not included in the function denote the complement of the function.

If we mark the empty squares by 0’s and combine them into valid adjacent squares, we obtain a simplified expression of the complement of the function.

The complement of F’ give us back to the function F. DeMorgan’s theorem can be used to derive the

product of sum form.

Page 22: Chapter 3Gate-Level Minimization Chapter 3 Gate-Level ...eng.uok.ac.ir/daneshfar/DigitalLogicCircuit/ch03-PPT.pdf · Chapter 3 Gate-Level Minimization Department of Electronic Engineering,

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Example 3-8

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Gate Implementation

Page 24: Chapter 3Gate-Level Minimization Chapter 3 Gate-Level ...eng.uok.ac.ir/daneshfar/DigitalLogicCircuit/ch03-PPT.pdf · Chapter 3 Gate-Level Minimization Department of Electronic Engineering,

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3-4 Product of Sums Simplification

Page 25: Chapter 3Gate-Level Minimization Chapter 3 Gate-Level ...eng.uok.ac.ir/daneshfar/DigitalLogicCircuit/ch03-PPT.pdf · Chapter 3 Gate-Level Minimization Department of Electronic Engineering,

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NAND & NOR Implementations

Digital circuits are more frequently constructed with NAND/NOR gates than with AND/OR gates due to ease of fabrication.

Page 26: Chapter 3Gate-Level Minimization Chapter 3 Gate-Level ...eng.uok.ac.ir/daneshfar/DigitalLogicCircuit/ch03-PPT.pdf · Chapter 3 Gate-Level Minimization Department of Electronic Engineering,

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NAND & NOR Implementations

A 1-input NAND or NOR gate behaves like an inverter.

Page 27: Chapter 3Gate-Level Minimization Chapter 3 Gate-Level ...eng.uok.ac.ir/daneshfar/DigitalLogicCircuit/ch03-PPT.pdf · Chapter 3 Gate-Level Minimization Department of Electronic Engineering,

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NAND Implementation

(1) Simplify the function and express it in sop: f = AB + CD + E.(2) Transfer it to 2-level NAND-NAND expression (DeMorgan’s Thm): f =

((AB + CD + E)’)’ = ((AB)’ (CD)’ E’)’.(3) Draw the corresponding NAND gate implementation. Note that a 1-input

NAND gate can replace an inverter. AND-OR ≡ NAND-NAND. The process can be done directly on the logic diagram

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Two-Level Implementation

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Gain the NAND Implementation

(1) Simplify the function and express it in sop: f = AB + CD + E.(2) Transfer it to 2-level NAND-NAND expression (DeMorgan’s Thm): f =

((AB + CD + E)’)’ = ((AB)’ (CD)’ E’)’.(3) Draw the corresponding NAND gate implementation. Note that a 1-input

NAND gate can replace an inverter. AND-OR ≡ NAND-NAND. The process can be done directly on the logic diagram

Page 30: Chapter 3Gate-Level Minimization Chapter 3 Gate-Level ...eng.uok.ac.ir/daneshfar/DigitalLogicCircuit/ch03-PPT.pdf · Chapter 3 Gate-Level Minimization Department of Electronic Engineering,

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Example 3-10

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Example 3-10

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Multilevel NAND Circuits

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Logic Operation with NOR Gates

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Logic Operation with NOR Gates

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NOR Implementation

(1) Simplify the function and express it in pos: f = (A + B)(C + D)E.(2) Transfer it to 2-level NOR-NOR expression (DeMorgan’s Thm):

f = (((A + B)(C + D)E)’)’ = ((A + B)’ + (C + D)’ + E’)’.(3) Draw the corresponding NOR gate implementation. Note that a

1-input NOR gate can replace an inverter. It is the dual of theNAND implementation.

OR-AND ≡ NOR-NOR. The process can be done directly on the logic diagram The types of gates most often found in ICs are NAND & NOR, so

NAND & NOR logic implementations are the most important from a practical point of view.

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Example

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Example

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General Rules

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Other Two-Level Implementations

NAND-AND & AND-NOR implementations

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Other Two-Level Implementations

OR-NAND & NOR-OR implementations– Because of the INVERT part in each case, it is

convenient to use the simplification of F’(the complement of the function) instead of F.

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Summary

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Example

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Don’t-Care Conditions

In practice, there are applications where the function is not specified for certain combinations of the input variables. For example, in the 4-bit BCD code for the decimal digits, the outputs are unspecified for the input combinations 1010-1111.

Functions that have unspecified outputs for some input combinations are called incompletely specified functions.

The unspecified minterms of a function are called the don’t-care conditions, or simply the don’t-cares, and are denoted as X’s.

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Don’t-Care Conditions (cont.)

These don’t-care conditions can be used on a map to provide further simplification of the Boolean expression.

Each X can be assigned an arbitrary value, 0 or 1, to help the simplification procedure.

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Example 3-9

Simplify the Boolean function f (w, x, y, z) = Σ(1, 3, 7, 11, 15) that has the don’t-care conditions d (w, x, y, z) = Σ(0, 2, 5).

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Example

Note that the above 2 expressions represent 2 functions that are algebraically unequal: each covers different don’t-care terms.

We may or may not include any of the Xs, while all the 1s must be included.

It is also possible to obtain a simplified pos expression using the don’t-cares.

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Tabulation Method

The map method is convenient when the number of variables does not exceed 5 or 6.

The map method is essentially a trial-and-error method that does not offer any guarantee of producing the best realization.

The map method’s dependence on the somewhat intuitive human ability to recognize patterns makes it unsuitable for design automation (programming for a digital computer).

The tabulation method is a specific step-by-step (algorithmic) procedure that is guaranteed to produce a simplified standard-form expression for a function.

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Tabulation Method (Cont.)

It can be applied to problems with any number of variables.

It is suitable for machine computation. It however is quite tedious for human use. The tabulation method was first formulated by Quine

(1952) and later improved by McCluskey (1956), thus known as the Quine-McCluskey method.

Step 1:Exhaustive search of all prime implicant.

Step 2:Choose among the PIs those that give an expression with the least number of literals.

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Determination of Prime Implicants

The goal of the Quine-McCluskey algorithm is aspecial case of the following: Select the smallest possible subset, D, of a set of

objects, A, so that some criterion, f,is satisfied.

The set D will consist of all products in the minimal sop realization of a given booleanfunction f, of which the set A contains all possible products.

Let f = Σ(0, 1, 2, 8, 10, 11, 14, 15).

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Example

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Example (Cont.)

Step 1:Group the minterms according to the number of 1s (see Column (a)).Step 2:Combine any 2 minterms that differ from each other by exactly onevariable, the unmatched variable removed (see Column (b)). Try thisfor all possible pairs of minterms. A check is placed to the right ofboth minterms if they have been used in a match.Step 3:Repeat the process. Combine any 2 product terms from Step 2 thatdiffer from each other by exactly one variable, the unmatchedvariable removed (see Column (c)).Step 4:The unchecked terms in the table form the PIs. Some of the productterms may appear twice in the table. It of course is unnecessary touse the same term twice.

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Example (Cont.)

Compare the result with the map method (Fig. 3-27, p. 103).

When comparing 2 terms to decide if they can be combined, the comparison can be done directly on the decimal numbers. We combine 2 terms iff the difference of their corresponding decimal numbers is a power of 2.

In most cases, the sum of PIs obtained from the procedure shown above is not necessarily a standard form (which is minimized). The reason is that some of the PIs may be redundant.

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Example (Cont.)

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Example (Cont.)

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Selection of Prime Implicants

The selection of PIs that form the minimized function is made from a PI table: each PI is represented in a row and each minterm in a column.

Suppose we have the following PIs: x´y´z, w´xz´, w´xy, xyz, wyz, & wx´ (from Ex. 3-14).

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Example (Cont.)

Step 1: Check the PIs that cover minterms with a single X in their

columns. These PIs are theessential PIs.

Step 2: Check each column whose minterm is covered by the selected

essential PIs.Step 3: If there are minterms left uncovered (7 & 15 in this example),

some non-essential PIs have to be selected to cover them. We of course will select the PIs with a smallest total number of literals (xyz in this example).