Chapter 4 – Combinational Functions and Circuits

Logic and Computer Design Fundamentals

Chapter 4 2

Rudimentary Logic Functions

Functions of a single variable XCan be used on inputs to functionalblocks to implementother than block’sintended function

0

1

F 5 0

F 5 1

(a)

F 5 0

F 5 1

VCC or VDD

(b)

X F 5 X(c)

X F 5 X

(d)

TABLE 4-1Functions of One Variable

X F = 0 F = X F = F = 1

01

00

01

10

11

X

Chapter 4 3

Multiple-bit Rudimentary Functions

Multi-bit Examples:

A wide line is used to representa bus which is a vector signalIn (b) of the example, F = (F3, F2, F1, F0) is a bus.The bus can be split into individual bits as shown in (b)Sets of bits can be split from the bus as shown in (c)for bits 2 and 1 of F. The sets of bits need not be continuous as shown in (d) for bits 3, 1, and 0 of F.

F(d)

0

F31 F2

F1A F0

(a)

01

A1

2 34

F0

(b)

4 2:1 F(2:1)2

F(c)

4 3,1:0 F(3), F(1:0)3

A A

Chapter 4 4

Enabling Function

Enabling permits an input signal to pass through to an output

Disabling blocks an input signal from passing through to an output, replacing it with a fixed value

The value on output when it is disable can be Hi-Z (as for three-state buffers and transmission gates), 0 , or 1

When disabled, 0 output

When disabled, 1 output

XFEN

(a)

ENX

F

(b)

Chapter 4 5

Decoding - conversion of an n-bit input code to an m-bit output code withn ≤ m ≤ 2n such that each valid code word produces a unique output codeCircuits that perform decoding are called decodersHere, functional blocks for decoding are• called n-to-m line decoders, where m ≤ 2n, and• generate 2n (or fewer) minterms for n input

variables

Decoding

Chapter 4 6

1-to-2-Line Decoder

2-to-4-Line Decoder

Note that 2-4-linemade up of 2 1-to-2-line decoders and 4 AND gates.

Decoder Examples

A D0 D1

0 1 01 0 1

(a) (b)

D1 5 AA

D0 5 A

A1

0011

A0

0101

D0

1000

D1

0100

D2

0010

D3

0001

(a)

D0 5 A 1 A 0

D1 5 A 1 A 0

D2 5 A 1 A 0

D3 5 A 1 A 0

(b)

A 1

A 0

Chapter 4 7

Decoder Expansion

General procedure given in book for any decoder with n inputs and 2n outputs.This procedure builds a decoder backward from outputs.The output AND gates are driven by two decoders with their numbers of inputs either equal or differing by 1.These decoders are then designed using same procedure until 2-to-1-line decoders are reached. Procedure can be modified to apply to decoders with the number of outputs ≠ 2n

Chapter 4 8

Decoder Expansion - Example 1

3-to-8-line decoder • Number of output ANDs = 8• Number of inputs to decoders driving output ANDs = 3• Closest possible split to equal

2-to-4-line decoder1-to-2-line decoder

• 2-to-4-line decoderNumber of output ANDs = 4Number of inputs to decoders driving output ANDs = 2Closest possible split to equal

• Two 1-to-2-line decoders

Chapter 4 9

Decoder Expansion - Example 1

Result

3-to-8 Line decoder

1-to-2-Line decoders

4 2-input ANDs 8 2-input ANDs

2-to-4-Linedecoder

D0A 0

A 1

A 2

D1

D2

D3

D4

D5

D6

D7

Chapter 4 10

Decoder Expansion - Example 2

7-to-128-line decoder • Number of output ANDs = 128• Number of inputs to decoders driving output ANDs

= 7• Closest possible split to equal

4-to-16-line decoder3-to-8-line decoder

• 4-to-16-line decoderNumber of output ANDs = 16Number of inputs to decoders driving output ANDs = 2Closest possible split to equal

• 2 2-to-4-line decoders

• Complete using known 3-8 and 2-to-4 line decoders

Chapter 4 11

In general, attach m-enabling circuits to outputsSee truth table below for function

• Note use of X’s to denote both 0 and 1• Combination containing two X’s represent four binary combinations

Alternatively, can be viewed as distributing value of signal EN to 1 of 4 outputsIn this case, called ademultiplexer

EN

A 1

A 0D0

D1

D2

D3

(b)

EN A1 A0 D0 D1 D2 D3

01111

X0011

X0101

01000

00100

00010

00001

(a)

Decoder with Enable

Chapter 4 12

74LS138 디코더

- NAND 출력 -> active low 출력

enable 입력 : E1', E2',(active low), E3 (active high)

즉, 디코더가 활성화되려면 : E1'E2'E3 = 001

Chapter 4 13

디코더의 확장

4개의 74LS138과 인버터를 사용하여 1-of-32 디코더를 구성

1-of-32 디코더는 5-to-32 디코더, 즉 5개의 입력이 필요

74138을 4개 사용, 출력은 8개 x 4 = 32의 출력을 rename

74138의 원래 입력과 E3E2'E1'를 이용하여 5 입력 A4A3A2A1A0 생성

74138의 각 소자(Z1 - Z4)는 A4A3에 인가된 신호가 각각 00, 01, 10, 11일 때

순차적으로 그 디코더를 활성화하게되고 이때의 A2A1A0값에 따라 출력 신호 중

하나만 활성화

Chapter 4 14

BCD-to-decimal decoder : 7442

- output : low active

- BCD 무효입력 ==>출력이 모두 high (비활성)

- 4-to-10 디코더, 1-of-10 디코더

Chapter 4 15

BCD-7-세그먼트 디코더/구동기

- 7 세그먼트 : 0에서 9까지의 십진수, A에서 F까지의 16 진수 표시

각 세그먼트는 LED를 사용

- 세그먼트의 이름 : a, b, c, d, e, f, g

- 공통 단자에 따라 CA(common anode)와 CC(common cathode)

- BCD to 7 세그먼트 디코더 : TTL 7446 또는 7447

4비트 BCD 입력-> 10 진수(16진수) display

출력 low active

==> CA형 7 세그먼트를 구동

Chapter 4 16

Encoding

Encoding - opposite of decoding - conversion of an m-bit input code to a n-bit output code with n ≤ m ≤2n such that each valid code word produces a unique output codeCircuits that perform encoding are called encodersAn encoder has 2n (or fewer) input lines and n output lines which generate binary code corresponding to input valuesTypically, an encoder converts a code containing exactly one bit that is 1 to a binary code corres-ponding to position in which 1 appears.

Chapter 4 17

Encoder Example

A decimal-to-BCD encoder• Inputs: 10 bits corresponding to decimal

digits 0 through 9, (D0, …, D9)• Outputs: 4 bits with BCD codes• Function: If input bit Di is a 1, then output

(A3, A2, A1, A0) is BCD code for i,Truth table could be formed, but alternatively, equations for each of four outputs can be obtained directly.

Chapter 4 18

Encoder Example (continued)

Input Di is a term in equation Aj if bit Aj is 1 in binary value for i.Equations:A3 = D8 + D9

A2 = D4 + D5 + D6 + D7

A1 = D2 + D3 + D6 + D7

A0 = D1 + D3 + D5 + D7 + D9

F1 = D6 + D7 can be extracted from A2 and A1Is there any cost saving?

Chapter 4 19

Priority Encoder

If more than one input value is 1, then encoder just designed does not work. One encoder that can accept all possible combinations of input values and produce a meaningful result is a priority encoder.Among 1s that appear, it selects the most significant input position (or the least significant input position) containing a 1 and responds with corresponding binary code for that position.

Chapter 4 20

Priority Encoder Example

Priority encoder with 5 inputs (D4, D3, D2, D1, D0) - highest priority to most significant 1 present - Code outputs A2, A1, A0 and V where V indicates at least one 1 present.

Xs in input part of table represent 0 or 1; thus table entries correspond to product terms instead of minterms. The column on left shows that all 32 minterms are present in product terms in table

1684211

No. of Min-terms/Row

0XXX00000

1001XXXX11110XXX101010XX1001100X1000100010000

VA0A1A2D0D1D2D3D4

OutputsInputs

Chapter 4 21

Priority Encoder Example (continued)

Could use a K-map to get equations, but can be read directly from table and manually optimized if careful:A2 = D4

A1 = D3 + D2 = F1, F1 = (D3 + D2)A0 = D3 + D1 = (D3 + D1)V = D4 + F1 + D1 + D0

D4 D3D4 D4

D4 D3D4 D2 D4 D2

Chapter 4 22

74148 Priority Encoder

입력 및 출력은 모두 low active

GS 출력은 유효출력 표시 : GS=0 유효출력

EI와 EO는 확장 연결시 사용

EI=H, 엔코딩 입력에 상관없이 출력 코드=111, EO=H

EI=L, 엔코딩 입력의 유효 유무에 따라 GS와 EO 결정

고순위 입력 인가시에 저순위 입력은 dont'care

Chapter 4 23

74148 확장연결

16 to 4 priority 엔코더 : 74148 cascading

Chapter 4 24

74147 encoder

Decimal-to-BCD encoder : 74147

- 10진수를 BCD 코드로 변환 :

10개입력 (9개만사용), 4개출력

- Active low 입력 및 출력

Chapter 4 25

Multiplexers

여러 개의 데이터 입력 중 하나를 선택하여 출력

- 데이터 선택기 (data selector)

일반적인 MUX : N-to-1, 1 out of N

N개의 입력 중 하나를 선택하기 위한 선택선:

M, N ≤ 2M

Chapter 4 26

2-to-1-Line Multiplexer

Since 2 = 21, n = 1single selection variable S has two values:

• S = 0 selects input I0

• S = 1 selects input I1

Logic equation:Y = I0 + SI1S

S

I0

I 1

DecoderEnablingCircuits

Y

Chapter 4 27

Example: 4-to-1-line Multiplexer

2-to-22-line decoder

22 ´ 2 AND-OR

for an 2n-to-1-line multiplexer:

• n-to-2n-line decoder

• 2n ´ 2 AND-OR

S1Decoder

S0

Y

S1Decoder

S0

Y

S1Decoder

4 3 2 AND-ORS0

Y

I2

I3

I 1

I 0

Y = S1'S0'I0 +S1'S0I1 +S1S0'I2 +S1S0I3

I0

I1

I2

I3

0 0

0 1

1 0

1 1

YS1 S0

Chapter 4 28

74151 : 8 input MUX

8-input MUX : 74151, with enable input (low enable, E)

3개의 선택선 : S2S1S0

정규 및 반전 출력 : Z, Z'

Chapter 4 29

16-to-1 MUX

2개의 74151을 사용한 16-to-1 MUX 회로

S3=0, 위의 74151 동작,

S2S1S0 값에 따라

입력 I7 - I0 중 하나를 출력

S3=1, 아래 74151 동작,

S2S1S0 값에 따라

입력 I15 - I8 중 하나를 출력

Chapter 4 30

Combinational Function Implementation

Alternative implementation techniques:• Decoders and OR gates

• Multiplexers (and inverter)

• ROMs

• PLAs

• PALs

• Lookup TablesCan be referred to as structured implementation methods since a specific underlying structure is assumed in each case

Chapter 4 31

Decoder and OR Gates

Implement m functions of n variables with:• Sum-of-minterms expressions• One n-to-2n-line decoder• m OR gates, one for each output

Approach 1:• Find the truth table for the functions• Make a connection to the corresponding OR from

the corresponding decoder output wherever a 1 appears in the truth table

Approach 2• Find the minterms for each output function• OR the minterms together

Chapter 4 32

Decoder and OR Gates Example

Implement the following set of odd parity functions of (A7, A6, A5, A3)P1 = A7 A5 A3P2 = A7 A6 A3P4 = A7 A6 A5

Finding sum ofminterms expressionsP1 = Σm(1,2,5,6,8,11,12,15)P2 = Σm(1,3,4,6,8,10,13,15)P4 = Σm(2,3,4,5,8,9,14,15)Find circuit4-to-16 decoder + ORs

+++

+++

0123456789

101112131415

A7A6A5A4

P1

P4

P2

Chapter 4 33

Mux로 논리함수 구현 1

진리표에서 직접논리기능을 구현하는 데 사용

선택입력은 논리변수로 사용

각 데이터 입력은 진리표를 만족하기 위한 1 또는 0로

연결

Chapter 4 34

MUX로 논리함수 구현 2

3 입력 논리 함수인 경우-> 2(3-1)개의 선택선을 가진 MUX로 구현 가능4-to-1 MUX 사용으로 위 함수를 구현가능BA=> S1S0에 연결, C 신호에 대한 implementation table B'A' BA' BA'BAI0 I1 I2 I3

C’ 0 ① ② 3C 4 5 6 ⑦0 C' C' C <- 입력에 인가될 신호값

구현표의 열은 입력선에 인가할 신호의 반전 및 정규 열 구성행에는 선택선에 인가할 신호의 이진값 차례로 구성- 총 2N개의 minterm을 나타낼수 있는 항이 항에 진리표에서 1이 되는 minterm을 원으로 표시

-각 열의 단위로 원이 둘다 (C와 C') 그려지면 1, 둘 다 없으면 0,

- C' 행만 있으면 C', C행만 있으면 C로 표시

최종회로 :

Z= C'B'A+C'BA'+CBA <- 진리표 만족

Chapter 4 35

Read Only Memory

Address decoder + 메모리

Chapter 4 36

Productterm

AND Inputs

OutputsA B C D W

123

W = C

456

F1 = X = A + B + W

789

101112

———

———

———

———

———

A B

C

+ ABC

F2 = Y = AB + BC +AC

B CA

10—

01—

00—

———

——1

— —

01

01

11—

—

—

———

—

1—1

11—

—11

—

—

———

—

Equations: F1 = A + B + C + ABCF2 = AB + BC + AC

F1 must befactoredsince fourtermsFactor outlast twoterms as W

A BB C C A

Programmable Array Logic Example

Chapter 4 37

Programmable Array Logic Example

X

XX

XX

XX

X XX

X X X

XX X

X X X

AND gates inputs

A C WProductterm

1

2

3

4

5

6

7

8

9

10

11

12

A

B

C

D

W

F1

F2

All fuses intact(always 5 0)

X Fuse intact

X

A B B C D D W

A C WA B B C D D W

1 Fuse blown

Chapter 4 38

Programmable Logic Array Example

K-mapspecificationHow can thisbe implementedwith four terms?Complete the programming table

Outputs

1234

F2

11

–1

ABACBC

Inputs

–11

C

11–

A

1–1

B

PLA programming table

(T)F1

( )Productterm

F1 5 A BC + A B C + A B CF1 5 AB + AC + BC + A B C

0

C

0

1

0 1

0 0

00 01 11 10BC

A

0

B

1

1A

0

C

0

1 0

1 1

00 01 11 10BC

A

1

B

0

1A

F2 5 AB + AC + BCF2 5 AC + AB + B C

0

Chapter 4 39

Programmable Logic Array Example

X Fuse intact1 Fuse blown

0

1

F1

F2

A

B

C

C B AC B A

1

2

4

3

X X

X X

X X

X XX

X

X

X X

X

X

X

X

X

Chapter 4 40

Lookup Tables

Lookup tables are used for implementing logic in Field-Programmable Gate Arrays (FPGAs) and Complex Logic Devices (CPLDs)Lookup tables are typically small, often with four inputs, one output, and 16 entriesSince lookup tables store truth tables, it is possible to implement any 4-input functionThus, design problem is how to optimally decompose a set of given functions into a set of 4-input two- level functions.

Chapter 4 41

Lookup Table Example

Equations to be implemented:F1(A,B,C,D,E) = A D E + B D E + C D E F2(A,B,D,E,F) = A D E + B D E + F D EExtract 4-input function:F3(A,B,D,E) = A D E + B D EF1(C,D,E,F3) = F3 + C D EF2(D,E,F,F3) = F3 + F D EThe cost of the solution is 3 lookup tables

Chapter 4 42

Demultiplxer

디멀티플렉서(demultiplexer : DEMUX) - 데이터 분배기

MUX의 역동작으로 하나의 입력을 여러 개의 출력으로 분배

<- 다중 스위치처럼 1부터 N까지의 출력채널 선택 분배

일반적인 DEMUX : 1-to- N

N개의 출력으로 분배하기 위한

선택선이 M이라면

N ≤ 2M

Chapter 4 43

1-to-8 Demux

디코더를 DEMUX로 사용

74138디코더를 DEMUX 사용 예

인에이블 E1은데이타입력 I로사용

A2,A1,A0 입력은 선택선으로 사용

Chapter 4 44

비교기 (comparator)

7485 : 4비트 비교기

8개의 비교 입력

3개의 cascading 입력

3개의 출력

비교기 논리 :

Xi = AiBi+Ai'Bi',

cascading 입력고려안함

(A>B) = A3B3' + X3A2B2' +

X3X2A1B1' + X3X2X1A0B0'

(A<B) = A3'B3 + X3A2'B2 +

X3X2A1'B1 + X3X2X1A0'B0

(A=B) = X3X2X1X0

<= 논리도 작성해볼것

Chapter 4 45

비교기 확장

Cascading 입력 사용

높은자리의 두수가 먼저 비교되어 서로 같을 때는

낮은자리의 수가 비교된다.

Chapter 4 46

Gray to Binary converter

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

0 0 0 0

0 0 0 1

0 0 1 1

0 0 1 0

0 1 1 0

0 1 1 1

0 1 0 1

0 1 0 0

1 1 0 0

1 1 0 1

1 1 1 1

1 1 1 0

1 0 1 0

1 0 1 1

1 0 0 1

1 0 0 1

Binary

w x y z

Gray

D C B A Binary to Gray

w x y z

<== XOR

1 0 0 1 Binary 9

↓ ↓ ↓ ↓

1 1 0 1 Gray 9

<== XOR

0 1 1 1 Binary 7

↓ ↓ ↓ ↓

0 1 0 0 Gray 7

Gray to binary

D C B A

0 1 0 1 Gray 6

↓ ↗↓ ↗↓ ↗↓ <== XOR

0 1 1 0 Binary 6

1 0 1 1 Gray 13

↓ ↗↓ ↗↓↗↓ <== XOR

1 1 0 1 Binary 13

- XOR 게이트 3개를 이용하여 구현