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Chapter 6-1ALU, Adder and Subtractor
Simple ALUSimple ALU AdderAdder SubtractSubtractoorr Next LectureNext Lecture
MultiplierMultiplier DividerDivider Floating Point NumbersFloating Point Numbers
2
Let's build an ALU to support the Let's build an ALU to support the ““andand”” and and ““oror”” instructionsinstructions Just build a 1-bit ALU, and use 32 of them Just build a 1-bit ALU, and use 32 of them
(bit-slice)(bit-slice)
b
a
operation
result
op a b res
Simple ALU (arithmetic logic unit)
32
32
32
operation
result
a
b
ALU
3
Selects one of the inputs to be the output, based on a Selects one of the inputs to be the output, based on a control inputcontrol input
Lets build our ALU using a MUX:Lets build our ALU using a MUX:
S
CA
B0
1
Review: The Multiplexer
note: we call this a 2-to-1 mux
4
AND and OR ALU
0
1A
B
Result
Operation
5
Add an Adder to the 1-bit ALU
b
0
2
Result
Operation
a
1
CarryIn
CarryOut
FA
6
Building a 32-bit ALU
b
0
2
Result
Operation
a
1
CarryIn
CarryOut
Result31a31
b31
Result0
CarryIn
a0
b0
Result1a1
b1
Result2a2
b2
Operation
ALU0
CarryIn
CarryOut
ALU1
CarryIn
CarryOut
ALU2
CarryIn
CarryOut
ALU31
CarryIn
FA
7
Two's complement approach: just negate b and add 1 Two's complement approach: just negate b and add 1 using XOR gatesusing XOR gates
Subtraction Support
Binvert
b31
b0
b1
b2
Result31a31
Result0
CarryIn
a0
Result1a1
Result2a2
Operation
ALU0
CarryIn
CarryOut
ALU1
CarryIn
CarryOut
ALU2
CarryIn
CarryOut
ALU31
CarryIn
0
2
Result
Operation
a
1
CarryIn
CarryOut
0
1
Binvert
b
sub
8
Full Adder
AAii BBii CCii SSii CCi+1i+1
00 00 00 00 00
00 00 11 11 00
00 11 00 11 00
00 11 11 00 11
11 00 00 11 00
11 00 11 00 11
11 11 00 00 11
11 11 11 11 11
The K-maps forCi+1:
Si:
0101
1010
BBiiCCiiAAii
1110
0100
BBiiCCii
AAii
Truth TableTruth Table
SumA
B
Ci
Ci+1
+
9
Full Adder (cont.)
Boolean equations:Boolean equations: CCi+1i+1 = A= AiiBBii + A + AiiCCii + B + BiiCCii
= A= AiiBBii + (A + (Aii+B+Bii)C)Cii
SSii = A= AiiBBii’ C’ Cii’ + A’ + Aii’B’Bii’C’Cii + A + Aii’B’BiiCCii’ + A’ + AiiBBiiCCii
= A= Aii B Bii C Cii
CCi+1i+1 = A= AiiBBii + A + AiiBBii’C’Cii + + AAii’’BBiiCCii
= A= AiiBBii + + ((AAiiBBii’ + A’ + Aii’B’Bii))CCii
= A= AiiBBii + (A + (Aii B Bii))CCii
1110
0100
BBiiCCii
AAii
0101
1010
BBiiCCiiAAii
10
Full Adder using 2 Half Adders
Ci+1 = AiBi + (Ai Bi)Ci
Si = Ai Bi Ci
AAii
BBii
CCii
CCi+i+
11
SSii
11
1-bit Full Adder
Ai
Bi
Ci
Cout
Sum
SumAi
Bi
Ci
Cout
+
12
CC44 C3 C2 C1 C0 C3 C2 C1 C0
A3 A2 A1 A0 A3 A2 A1 A0 +B3 B2 B1 B0 +B3 B2 B1 B0 -------------- -------------- S3 S2 S1 S0 S3 S2 S1 S0
4-bit Ripple-Carry Adder
1 1 0 1 01 1 0 1 0 1 1 0 1 1 1 0 1 +1 1 0 1 +1 1 0 1 ---------- ---------- 1 0 1 0 1 0 1 0
4-bit Ripple Adder
Critical Path = DXOR+4*(DAND+DOR) for 4-bit ripple adder (9 gate levels)
For an N-bit ripple carry adderCritical Path Delay 2(N-1)+3 = (2N+1) Gate delays
S0
A0 B0
C0
S1
A1 B1
S2
A2 B2
S3
A3 B3
Cout
carry1carry2carry3
AiBiCi
Cout
S
A Full Adder
Cout C3 C2 C1 C0Cout C3 C2 C1 C0 A3 A2 A1 A0 A3 A2 A1 A0 +B3 B2 B1 B0 +B3 B2 B1 B0 -------------- -------------- S3 S2 S1 S0S3 S2 S1 S0
14
Design of Fast Adders
n-bit ripple carry adder may have too much delay in n-bit ripple carry adder may have too much delay in developing its outputs, sdeveloping its outputs, s00 through s through sn-1n-1 and c and cnn
TThe delay through a network of logic gates depends on he delay through a network of logic gates depends on IIntegrated circuit ntegrated circuit fabricationfabrication technology technology TThe number of gates in the pathhe number of gates in the path(s)(s) from input from input(s)(s) to to
outputoutput(s)(s) TThe delay incurred with any combinational logic network he delay incurred with any combinational logic network
constructed from gates in a given technology can be constructed from gates in a given technology can be determined by adding up the determined by adding up the amountamount of logic gate delays of logic gate delays along the longest path through the networkalong the longest path through the network
WWe require that an arithmetic operation is completed in e require that an arithmetic operation is completed in one clock cycleone clock cycle
Example: fExample: for a processor operating at 1or a processor operating at 100M00Mhz, an addition hz, an addition must complete in 1must complete in 100nsns
15
SSuppose that the delay from from cuppose that the delay from from c ii to c to ci+1i+1 of any adder of any adder block is 1nsblock is 1ns
an n-bit addition can be performed in the time it takes the an n-bit addition can be performed in the time it takes the carry signal to reach ccarry signal to reach cn-1n-1 position plus the time it takes to position plus the time it takes to develop sdevelop sn-1n-1
A 32-bit addition may A 32-bit addition may approximately approximately take 32 nstake 32 ns TTwo approaches can be used to reduce this delaywo approaches can be used to reduce this delay
FFaster circuit technologyaster circuit technology Make SMake Sii and C and Ci+1i+1 independent ofindependent of C Cii
Design of Fast Adders (cont.)
FA c0
B1
A1
s1
FA
c1
B0
A0
s0
FA
cn 1-
Bn 1-
An 1-
cn
sn 1-
Most significant bit(MSB) position
Least significant bit(LSB) position
16
How to mHow to make Sake Sii and C and Ci+1i+1 independent ofindependent of C Cii Motivation: Motivation:
If we didn't know the value of carry-in, what could we If we didn't know the value of carry-in, what could we do?do?
CCi+1i+1= A= AiiBBii + A + AiiCCi i + B+ BiiCCii = = AAiiBBii + (+ (AAii+B+Bii))CCii
When do we always generate a carry? When do we always generate a carry? GGii = A = AiiBBii
When do we propagate the carry? When do we propagate the carry? PPii = A = Aii+B+Bii
Design of Fast Adders (cont.)
17
Express Sum and Carry as a function of P, G Full adder expressions
CCi+1i+1= A= AiiBBii+A+AiiCCii+B+BiiCCii = = AAiiBBii+(+(AAii+B+Bii)C)Ci i = = AAiiBBii++((AAiiBBii)C)Cii
SSi i = A= Ai i BBi i CCii
GGii = A = AiiBBii
PPii = A = Aii+B+Bii = A = AiiBBii
CCi+1i+1(G,P)= (G,P)= GGii++PPiiCCii (do you still see ripple (do you still see ripple here?)here?)
SSi i (G,P)(G,P) = = PPii CCii (no ripple) (no ripple)
Independent of CIndependent of Cii
18
Carry Lookahead Equations
)B(ACBAC iiiii1i
)(propagate BAp
(generate) BAg
iii
iii
iii1i CpgC
0012301231232333334
00120121222223
0010111112
0001
CppppgpppgppgpgCpgC
CpppgppgpgCpgC
CppgpgCpgC
CpgC
Do you still see ripple here? Do you still see ripple here? AAll Gi and Pi functions can be formed independentlyll Gi and Pi functions can be formed independently
So, all the carry’s are only dependent on inputs Ai and Bi and So, all the carry’s are only dependent on inputs Ai and Bi and CC00
Two levels onlyTwo levels only
19
4-bit Carry Lookahead Adder
0012301231232333334
00120121222223
0010111112
0001
CppppgpppgppgpgCpgC
CpppgppgpgCpgC
CppgpgCpgC
CpgC
Only 3 Gate Delay for each Carry COnly 3 Gate Delay for each Carry C ii
= = DDANDAND + 2*D + 2*DOROR
4 Gate Delay for each Sum S4 Gate Delay for each Sum Sii
= = DDANDAND + 2*D + 2*DOROR + D+ DXORXOR
C4C4
a0 b0S0S0a1 b1S1S1
C0C0
a2 b2S2S2a3 b3S3S3
C3C3g3g3 p3p3 g0g0 p0p0C2C2g2g2 p2p2 C1C1g1g1 p1p1
Carry Lookahead circuitryCarry Lookahead circuitry
20
CC11 = G = G00 + P + P00CC00 CC22 = G = G11 + P + P11GG00+P+P11PP00CC00 CC33 = G = G22 + P + P22GG11+P+P22PP11GG00 + P + P22PP11PP00CC00 ((Two gate Two gate
delaydelay)) CC44 = G = G33 + P + P33GG22+P+P33PP22GG11 + P + P33PP22PP11GG00 + P + P33PP22PP11PP00CC00
OOne ne gate gate delay for all Gdelay for all Gii and P and Pii TwoTwo additional additional gate delaygate delay for each Cfor each Cii f for i!=0or i!=0 One additionalOne additional gate delay for S gate delay for Si i (G,P)(G,P) = = PPii CCii for i!=0for i!=0
Note: Note: CC44 requires a fan-in of five for the basic gates requires a fan-in of five for the basic gates
4-bit Carry-Lookahead Adder
21
Therefore, the addition requires Therefore, the addition requires 4 4 levels of logic levels of logic independent of independent of nn, the number of bits, the number of bits
Can we build n-bit carry lookahead adder in this way?Can we build n-bit carry lookahead adder in this way?
Constraints in practice : fan-in constraintsConstraints in practice : fan-in constraints CCi+1i+1 requires i+2 inputs to the largest AND term and requires i+2 inputs to the largest AND term and
i+2 inputs to the OR termi+2 inputs to the OR term LLogic gate fanogic gate fan--in is restricted in practicein is restricted in practice
Carry Lookahead Adder
22
CC11 = G = G00 + P + P00CC00 CC22 = G = G11 + P + P11GG00+P+P11PP00CC00 CC33 = G = G22 + P + P22GG11+P+P22PP11GG00 + P + P22PP11PP00CC00 CC44 = G = G33 + P + P33GG22+P+P33PP22GG11 + P + P33PP22PP11GG00 + P + P33PP22PP11PP00CC00
CC55 = G = G44 + P + P44CC44 CC66 = G = G55 + P + P55GG44+P+P55PP44CC44 CC77 = G = G66+ P+ P66GG55+P+P66PP55GG44 + P + P66PP55PP44CC44 CC88 = G = G77 + P + P77GG66+P+P77PP66GG55 + P + P77PP66PP66GG44 + P + P77PP66PP55PP44CC44
……
IInside each block, carries are generated using look nside each block, carries are generated using look ahead, however carries still ripple between blocksahead, however carries still ripple between blocks
n-bit Carry-Lookahead AdderMethod 1: Using 4-bit Carry-Lookahead Adders
23
UUse carry look ahead technique between blocksse carry look ahead technique between blocks Example design of 16 bit adderExample design of 16 bit adder
CC44 = G = G33 + P + P33GG22+P+P33PP22GG11 + P + P33PP22PP11GG00 + P + P33PP22PP11PP00CC00
LetLet GG00II = G = G33 + P + P33GG22 + P + P33PP22GG11 + P + P33PP22PP11GG00
PP00II = P = P33PP22PP11PP00
CC44 = G = G00II + P + P00
IICC00
EEach of the 4 bit adders provides two new outputach of the 4 bit adders provides two new outputss: G: GkkII and P and Pkk
II where k = 0 for the first 4where k = 0 for the first 4--bit adder and k = 1 for the second bit adder and k = 1 for the second 4-4-
bit adderbit adder
GGkkII and P and Pkk
II determine whether block k generates or propagates a determine whether block k generates or propagates a carrycarry
In this fashion, iIn this fashion, it is not necessary to wait for carries to ripple t is not necessary to wait for carries to ripple between all the 4-bit blocksbetween all the 4-bit blocks
n-bit Carry-Lookahead Adder Method 2
24
Carry-lookahead logic
4-bit adder 4-bit adder 4-bit adder 4-bit adder
s15-12
P3IG3
I
c12
P2IG2
I
c8
s11-8
G1I
c4
P1I
s7-4
G0I
c0
P0I
s3-0
c16
A15-12
B15-12
A11-8
B11-8
A7-4
B7-4
A3-0
B3-0
.
G0II P0
II
16-bit Carry-Lookahead Adder
25
CC11 = G = G00 + P + P00CC00
CC22 = G = G11 + P + P11GG00+P+P11PP00CC00
CC33 = G = G22 + P + P22GG11+P+P22PP11GG00 + P + P22PP11PP00CC00
CC44 = G = G33 + P + P33GG22+P+P33PP22GG11 + P + P33PP22PP11GG00 + P + P33PP22PP11PP00CC00
CC44 = G = G00II + P + P00
IICC00
CC88 = = G G11II + P + P11
IIGG00II + P + P11
IIPP00IICC00
CC1212 = G = G22II+P+P22
IIGG11II + P + P22
IIPP11IIGG00
II + P + P22IIPP11
IIPP00IICC00
CC1616 = G = G33II + P + P33
IIGG22II+P+P33
IIPP22IIGG11
II + P + P33IIPP22
IIPP11IIGG00
II + P + P33IIPP22
IIPP11IIPP00
IICC00
16-bit Carry-Lookahead Adder
26
16-bit Adder Delay Calculation
GGii = = AAiiBBii PPii = = AAii++BBii (O (One gate delayne gate delay))
PP00II = P = P33PP22PP11PP00
GG00II = G = G33 + P + P33GG22 + P + P33PP22GG11 + P + P33PP22PP11GG0 0 ((Two gate delayTwo gate delay))
CC44 = G = G00II + P + P00
IICC00 CC88 = = G G11
II + P + P11IIGG00
II + P + P11IIPP00
IICC00 CC1212 = G = G22
II+P+P22IIGG11
II + P + P22IIPP11
IIGG00II + P + P22
IIPP11IIPP00
IICC0 0 ( (Two gate delayTwo gate delay))
CC1616 = G = G33II + P + P33
IIGG22II+P+P33
IIPP22IIGG11
II + P + P33IIPP22
IIPP11IIGG00
II + P + P33IIPP22
IIPP11IIPP00
IICC00
Need 5 gate delays to get C4, C8, C12, and C16Need 5 gate delays to get C4, C8, C12, and C16 Need Need additional 2 gate delaysadditional 2 gate delays to get C5,C6,C7,C9,C10,C11,C13,C14, and to get C5,C6,C7,C9,C10,C11,C13,C14, and
C15C15
FFor a sixteen bit adder with two levels carry look aheador a sixteen bit adder with two levels carry look ahead 7 gate delays are needed to get all carry bits7 gate delays are needed to get all carry bits With one more gate delay, With one more gate delay, all sum bits can be obtained in 8 gate delaysall sum bits can be obtained in 8 gate delays
27
CC44 = G = G00II + P + P00
IICC00 CC88 = = G G11
II + P + P11IIGG00
II + P + P11IIPP00
IICC00 CC1212 = G = G22
II+P+P22IIGG11
II + P + P22IIPP11
IIGG00II + P + P22
IIPP11IIPP00
IICC00 ((Two gate Two gate delaydelay))
CC1616 = G = G33II + P + P33
IIGG22II+P+P33
IIPP22IIGG11
II + P + P33IIPP22
IIPP11IIGG00
II + P + P33IIPP22
IIPP11IIPP00
IICC00
Let GLet G00IIII = G = G33
II + P + P33IIGG22
II+P+P33IIPP22
IIGG11II + P + P33
IIPP22IIPP11
IIGG00II
PP00II = II = PP33
IIPP22IIPP11
IIPP00II
C16, C32, C48, and C64 can be obtained using similar C16, C32, C48, and C64 can be obtained using similar formulas formulas applied toapplied to C4, C4, C8,C8, C12,C12, C16C16,, respectively respectively
Since Since C16 needs 5 gate delaysC16 needs 5 gate delays, , C32, C48, and C64 can be obtained in C32, C48, and C64 can be obtained in 7 gate delays7 gate delays All other carry bits can be obtained in 11 gate delaysAll other carry bits can be obtained in 11 gate delays
2 gate delay to get C20, C24 and C38 from C162 gate delay to get C20, C24 and C38 from C16 2 gate delay to get C21,2 gate delay to get C21, C22C22 and C23 from C20and C23 from C20
All sum bits can be obtained in 12 gate delaysAll sum bits can be obtained in 12 gate delays
64-bit Carry-Lookahead Adder Using Two Hierarchical Levels 4-bit Carry-Lookahead Adders
28
Binary Adder/Subtractors (cont.)
The subtraction The subtraction AA--BB can be performed by taking the 2's can be performed by taking the 2's complement of complement of BB and adding to and adding to AA
The logical simplicity and speed of either adding or subtracting signed numbers in 2's complement representation is the reason why this number system is used in the ALU of most modern computers
The 2's complement of The 2's complement of BB can be obtained by can be obtained by complementing B and adding one to the result.complementing B and adding one to the result.
A-B A-B = A + = A + 2C2C(B) (B) = A + = A + 1C1C(B) + 1(B) + 1
= A + = A + ((B’ + 1B’ + 1))
29
4-bit Binary Adder/Subtractor
If S=0, performs A+B; if S=1, performs A-BIf S=0, performs A+B; if S=1, performs A-BXOR gates act as programmable invertersXOR gates act as programmable inverters
30
TThe he resultresult will be the algebraically correct value in the will be the algebraically correct value in the 2's complement representation as long as the answer is 2's complement representation as long as the answer is in the range –2in the range –2n-1n-1 through 2 through 2n-1n-1–1–1
WWhen answers do not fall within the range: arithmetic hen answers do not fall within the range: arithmetic overflowoverflow Exception occursException occurs
TThehe A Add/Sub control wire is connected to Cdd/Sub control wire is connected to C00 TTo do addition, o do addition, AAdd/Sub control wire set to 0 for additiondd/Sub control wire set to 0 for addition TTo do subtraction, o do subtraction, AAdd/Sub control wire is set to 1dd/Sub control wire is set to 1,, and and
the the BB vector is 1's complemented vector is 1's complemented
n-bit Addition and Subtraction
31
n-bit Binary Addition-Subtraction Logic
Add/Subcontrol
n -bit adder
An 1-
A1
A0
cn
sn 1- s
1s0
c0
Bn 1-
B1
B0
32
Sign Extension in Binary Addition-Subtraction
Often we need to represent a given number in 2's complement by using a large number of bits
for positive numbers: add 0s to the left for negative numbers : the sign bit '1' is replicated to
the left as many times as needed (sign extension)
33
WWhen adding hen adding unsignedunsigned numbers, the carry-out c numbers, the carry-out cnn serves as serves as the overflow indicatorthe overflow indicator
When adding When adding signedsigned numbers, we need another indicator numbers, we need another indicator TThe addition of numbers with different signs cannot cause he addition of numbers with different signs cannot cause
overflow because the absolute value of the sum is always overflow because the absolute value of the sum is always smaller than the absolute value of one of the two summandssmaller than the absolute value of one of the two summands
What about adding numbers with the same signWhat about adding numbers with the same sign Example: adding +7 and +4 in 4-bit adder, the output Example: adding +7 and +4 in 4-bit adder, the output
vector S = 1011 = -5 and the carry-out signal from the MSB vector S = 1011 = -5 and the carry-out signal from the MSB is 0is 0
AAdd -4 and -6 , S = +6, and the carry-out signal is 1dd -4 and -6 , S = +6, and the carry-out signal is 1
0111 (7)0111 (7)
+ 0100 (4)+ 0100 (4)
= 1011 (-5)= 1011 (-5)
Overflow in Integer Arithmetic
1100 (-4)1100 (-4)+ 1010 (-6)+ 1010 (-6)= 0110 (+6)= 0110 (+6)
34
Overflow Detection
Examine the Examine the MSBMSB bit bit Bottom line:Bottom line:
P: positive; N: negativeP: positive; N: negative P+N or N+P always fall P+N or N+P always fall
into the range into the range E.g. -128+P cannot E.g. -128+P cannot
be smaller than -128 be smaller than -128 or bigger than 127or bigger than 127
N + N = N N + N = N P + P = PP + P = P
Problem lies inProblem lies in N+N = PN+N = P P+P = NP+P = N
CCn-1n-1 AAn-1n-1 BBn-1n-1 SSn-1n-1 CCnn OFOF
00 00 00 00 00 00
00 00 11 11 00 00
00 11 00 11 00 00
00 11 11 00 11 11
11 00 00 11 00 11
11 00 11 00 11 00
11 11 00 00 11 00
11 11 11 11 11 00
Discarded
35
Overflow Detection
CCn-n-
11
AAn-1n-1 BBn-1n-1 SSn-1n-1 CCnn OFOF
00 00 00 00 00 00
00 00 11 11 00 00
00 11 00 11 00 00
00 11 11 00 11 11
11 00 00 11 00 11
11 00 11 00 11 00
11 11 00 00 11 00
11 11 11 11 11 00
BACABCOF
Discarded
n1n CCOF
or
Cn-1
n-bit n-bit Adder/SubtractorAdder/Subtractor
Overflow
Cn