Chapter 6 Multi-channel Buffered Serial Port (McBSP)

Chapter 6Chapter 6

Multi-channel Buffered Serial Port Multi-channel Buffered Serial Port (McBSP)(McBSP)

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004

Chapter 6, Slide 2

ObjectivesObjectives

Definition of Terms: Definition of Terms: Bit, word or channel, frame and phase.Bit, word or channel, frame and phase.

Understand basic serial port operation.Understand basic serial port operation. Understand clock generation.Understand clock generation. Pin polarity.Pin polarity. Serial port interrupts.Serial port interrupts. Describe multi-channel operation.Describe multi-channel operation. Programming the serial port.Programming the serial port.


Chapter 6, Slide 3

Basic Definitions: Basic Definitions: BitsBits, , WordsWords ? ?

SP Ctrl (SPCR)SP Ctrl (SPCR)

Rcv Ctrl (RCR)Rcv Ctrl (RCR)

Xmt Ctrl (XCR)Xmt Ctrl (XCR)

Rate (SRGR)Rate (SRGR)

Pin Ctrl (PCR)Pin Ctrl (PCR)

Serial PortSerial Port

CLKCLK

b7b7 b6b6 b5b5 b4b4 b3b3 b2b2 b1b1 b0b0

WordWord

FSFS

a1a1 a0a0

BitBit

DataData

“ “WordWord” or “” or “channelchannel” contains #bits specified ” contains #bits specified byby WDLEN1WDLEN1 (8, 12, 16, 20, 24, 32). (8, 12, 16, 20, 24, 32).

RWDLEN1RWDLEN15577

XWDLEN1XWDLEN15577

“ “BitBit” - one data bit per SP clock period. ” - one data bit per SP clock period.

DataData


Chapter 6, Slide 4

Basic Definitions: Basic Definitions: FrameFrame??







“ “FrameFrame” - contains one or multiple words” - contains one or multiple words FRLEN1FRLEN1 specifies #words per frame (1-128) specifies #words per frame (1-128)

RWDLEN1RWDLEN1

5577

XWDLEN1XWDLEN1

5577

RFRLEN1RFRLEN1

881414

XFRLEN1XFRLEN1

881414

w0w0 w1w1 w2w2 w3w3 w4w4 w5w5 w6w6 w7w7

FrameFrameWordWord

w6w6 w7w7DataData

FSFS


Chapter 6, Slide 5

Basic Definitions - Basic Definitions - PhasePhase

FSFS

Phase 1Phase 1 Phase 2Phase 2

AA BB332211DataData

FrameFrame







RFRLEN1RFRLEN1 RWDLEN1RWDLEN1

55881414 77

XFRLEN1XFRLEN1 XWDLEN1XWDLEN1

55881414


23232424 21213030


23232424 21213030

PHASEPHASE

3131

PHASEPHASE

3131 77


Note: dual-phaseNote: dual-phase used in Audio used in Audio Codec97 (AC97) Std Codec97 (AC97) Std

Each PHASE can contain different #bits (Each PHASE can contain different #bits (WDLEN1WDLEN1//22) and #words ) and #words ((FRLEN1/2FRLEN1/2) .) .

Each FRAME can contain Each FRAME can contain only 1 or 2only 1 or 2 PHASES ( PHASES (PHASEPHASE).).


Chapter 6, Slide 6

Basic Definitions - PhaseBasic Definitions - Phase

FSFS

AA BB332211


DataData

FrameFrame







RFRLEN2RFRLEN2PHASEPHASE RWDLEN2RWDLEN2 RFRLEN1RFRLEN1 RWDLEN1RWDLEN1558823232424 1414212130303131 77

XFRLEN2XFRLEN2PHASEPHASE XWDLEN2XWDLEN2 XFRLEN1XFRLEN1 XWDLEN1XWDLEN1558823232424 1414212130303131 77

From above example some of the bit fields of RCR and XCR can From above example some of the bit fields of RCR and XCR can be initialised as shown below.be initialised as shown below.

11

11

00010001

00010001

010010

010010

00100010

00100010

000000

000000

88 1616

Each PHASE can contain different #bits (Each PHASE can contain different #bits (WDLEN1WDLEN1//22) and #words ) and #words ((FRLEN1FRLEN1//22) .) .

Each FRAME can contain 1 or 2 PHASES (Each FRAME can contain 1 or 2 PHASES (PHASEPHASE).).



Chapter 6, Slide 8

Definitions - ReviewDefinitions - Review

b1b1 b2b2

CLKCLK

Word 1Word 1

Frame 1Frame 1

Phase 2Phase 2Phase 1Phase 1

FSFS








55881414 77


55881414


23232424 21213030


23232424 21213030

3131

3131 77

PHASEPHASE

PHASEPHASE


Frame 2Frame 2

Word 2Word 2 Word 3Word 3


Chapter 6, Slide 9





Chapter 6, Slide 10

McBSP Block Diagram (Read)McBSP Block Diagram (Read)

CPUCPU

DMADMA

PPeerriipphheerraall

BBuuss

RINTRINT

REVTREVT

RRBBRR

DDRRRR3232

DRDR

CLKRCLKR

FSRFSR

RSRRSR


Chapter 6, Slide 11

McBSP Block Diagram (Write)McBSP Block Diagram (Write)

DXDXDDXXRR

CPUCPU

DMADMA

PPeerriipphheerraall

BBuuss

RINTRINT

REVTREVT

RRBBRR

DDRRRR3232

CLKXCLKX

FSXFSX

DRDR

CLKRCLKR

FSRFSR

RSRRSR

XEVTXEVT

XINTXINT

XSRXSR


Chapter 6, Slide 12

McBSP Block Diagram (Configuration)McBSP Block Diagram (Configuration)

RBRRBRRSRRSR DRRDRR

XSRXSR DXRDXR

Multi-Channel BufferedMulti-Channel BufferedSerial Port (McBSP)Serial Port (McBSP)

PPeerriipphh

BBuuss

DRDR

CLKRCLKR

DXDX

CLKXCLKX

FSXFSX

CPUCPUCPUCPU

DMADMADMADMA

Peripheral BusPeripheral Bus

Serial PortSerial PortControl LogicControl Logic

SPCRSPCRRCRRCR

XCRXCR ??

??FSRFSR


Chapter 6, Slide 13

Serial Port - Basic OperationSerial Port - Basic Operation

RBRRBRRSRRSR DRRDRR

XSRXSR DXRDXR


PPeerriipphh

BBuuss

DRDR

CLKRCLKR

FSRFSR

DXDX

CLKXCLKX

FSXFSX

CPUCPU

DMADMA

““RECEIVE”RECEIVE”““TRANSMIT”TRANSMIT”Peripheral BusPeripheral Bus


SPCRSPCRRCRRCR

XCRXCR PCRPCR

SRGRSRGR


Chapter 6, Slide 14

McBSP Registers (1)McBSP Registers (1)RSRRSR Receive Shift RegReceive Shift RegRBRRBR Receive Buffer RegReceive Buffer RegDRRDRR Data Receive RegData Receive Reg

XSRXSR Transmit Shift RegTransmit Shift RegDXRDXR Data Transmit RegData Transmit Reg

SPCRSPCR Serial Port Control RegSerial Port Control RegRCRRCR Receive Control RegReceive Control RegXCRXCR Transmit Control RegTransmit Control Reg

ReceiveReceive

TransmitTransmit

ControlControl


Chapter 6, Slide 15





Chapter 6, Slide 16

Configure CLK and FS as inputs or outputsConfigure CLK and FS as inputs or outputs

FSR, FSX, CLKR and CLKX can be configured FSR, FSX, CLKR and CLKX can be configured either as inputs or outputs, depending on the either as inputs or outputs, depending on the application.application.


CLKRCLKR

CLKXCLKX

FSRFSRFSXFSX


SPCRSPCRRCRRCR

XCRXCR PCRPCR

SRGRSRGR


Chapter 6, Slide 17

Configure CLK and FS as inputs or outputsConfigure CLK and FS as inputs or outputs


CLKRCLKR

CLKXCLKX

FSRFSRFSXFSX


SPCRSPCRRCRRCR

XCRXCR PCRPCR

SRGRSRGR

CLK/FS ModeCLK/FS Mode0: Input0: Input1: Output1: Output







CLKRMCLKRMFSRMFSRM

1010

FSXMFSXM

1111

CLKXMCLKXM

8899


Chapter 6, Slide 18

Generating CLK and FS as outputGenerating CLK and FS as output

‘‘C6000C6000

FSRFSRFSXFSX

CLKRCLKRCLKXCLKX







CLKRMCLKRMFSRMFSRM

1010

FSXMFSXM

1111

CLKXMCLKXM

8899

CLK/FS ModeCLK/FS Mode0: Input0: Input1: Output1: Output


Chapter 6, Slide 19

Generating the CLK as outputGenerating the CLK as output

‘‘C6000C6000

FSRFSRFSXFSX

CLKRCLKRCLKXCLKX







CLKSMCLKSM

2929

Sample Rate Generator (SRGR)Sample Rate Generator (SRGR)

CLKSMCLKSM

CLKOUT1CLKOUT1

CLKSCLKS

CLKGDVCLKGDVCLKGCLKG

CLKGDVCLKGDV - divide down (1-255) - divide down (1-255) CLKGCLKG = (input clock) / (1 + = (input clock) / (1 + CLKGDVCLKGDV)) Max transfer rate = CLKG = 150 MHz/2 = 75 Mb/sMax transfer rate = CLKG = 150 MHz/2 = 75 Mb/s

CLKSMCLKSM - - selects clock src (selects clock src (CLKOUT1 CLKOUT1 oror CLKS CLKS))

CLKGDVCLKGDV

0077


Chapter 6, Slide 20

Generating the FS as outputGenerating the FS as output

‘‘C6000C6000







FSRFSRFSXFSX

CLKRCLKRCLKXCLKX

Sample Rate Generator (SRGR)Sample Rate Generator (SRGR)

CLKSMCLKSM

CLKGDVCLKGDVCLKGCLKG

FPERFPER FSGFSG

CLKSMCLKSM

2929

CLKGDVCLKGDV

0077

FSGMFSGM

2828

FWIDFWID

881515

FPERFPER

2727 1616

CLKOUT1CLKOUT1

CLKSCLKS

FPER: FPER: frame sync period (12 bits)frame sync period (12 bits) FWID:FWID: frame sync pulse width (8 bits)frame sync pulse width (8 bits)

FSGM: FSGM: 0 - FS gen’d on every DXR XSR copy0 - FS gen’d on every DXR XSR copy1 - FS gen’d by FSG1 - FS gen’d by FSG


Chapter 6, Slide 21



SPCRSPCR Serial Port Control RegSerial Port Control RegRCRRCR Receive Control RegReceive Control RegXCRXCR Transmit Control RegTransmit Control RegSRGRSRGR Sample Rate GeneratorSample Rate Generator

ReceiveReceive

TransmitTransmit

ControlControl


Chapter 6, Slide 22





Chapter 6, Slide 23

Configure CLK and FS pin polarityConfigure CLK and FS pin polarity


CLKRCLKR

CLKXCLKX

FSRFSRFSXFSX


SPCRSPCRRCRRCR

XCRXCR PCRPCR

SRGRSRGR

CLK/FS PolarityCLK/FS Polarity0: Falling edge0: Falling edge1: Rising Edge1: Rising Edge







CLKRPCLKRPFSRPFSRP

22

FSXPFSXP

33

CLKXPCLKXP

0011


Chapter 6, Slide 24



Understand basic serial port operation.Understand basic serial port operation. Understand clock generation.Understand clock generation. Pin polarity.Pin polarity. Serial port status and interrupts.Serial port status and interrupts. Describe multi-channel operation.Describe multi-channel operation. Programming the serial port.Programming the serial port.


Chapter 6, Slide 25

RRDY/XRDY Status and InterruptsRRDY/XRDY Status and Interrupts

CPUCPU

RINTRINTXINTXINT

EDMAEDMA

SyncSync

RRDY/XRDY displays the RRDY/XRDY displays the “status” of the read and “status” of the read and transmit ports:transmit ports:

0: not ready.0: not ready. 1: ready to read/write.1: ready to read/write.

RBRRBR DRRDRR

XSRXSR DXRDXR

RRDYRRDY=1=1

XRDYXRDY=1=1

““Ready to Read”Ready to Read”

““Ready to Write”Ready to Write”

SP Ctrl (SP Ctrl (SPCRSPCR))






RRDYRRDY

11

XRDYXRDY

1717

There are 3 methods for There are 3 methods for detecting if data is ready:detecting if data is ready:

Poll Poll SPCRSPCR bits via s/w. bits via s/w. Config CPU ints Config CPU ints (RINT/XINT).(RINT/XINT).

Program DMA sync events.Program DMA sync events.


Chapter 6, Slide 26

Other sources of Interrupts (R/XINT)Other sources of Interrupts (R/XINT)

CPUCPURINTRINT

XINTXINT

RRDY RRDY ( (RINTM=00bRINTM=00b))

End of Block (RCV) End of Block (RCV) ( (RINTM=01RINTM=01))

New FSR (frame begin)New FSR (frame begin) ( (RINTM=10bRINTM=10b))

Receive Sync ErrorReceive Sync Error ( (RINTM=11bRINTM=11b))

XRDY XRDY ((XINTM=00bXINTM=00b))

End of Block (XMT) End of Block (XMT) ((XINTM=01bXINTM=01b))

New FSX (frame begin) New FSX (frame begin) ((XINTM=10bXINTM=10b))

Transmit Sync Error Transmit Sync Error ((XINTM=11bXINTM=11b))

““Trigger Event”Trigger Event”







RRDYRRDY

11

XRDYXRDY

1717

XINTMXINTM

20202121

RINTMRINTM

4455


Chapter 6, Slide 27


Definition of Terms:Definition of Terms: Bit, word or channel, frame and phase.Bit, word or channel, frame and phase.



Chapter 6, Slide 28

Multi-Channel operationMulti-Channel operation

How do you enable/disable each channel?How do you enable/disable each channel?

Ch0Ch0 Ch1Ch1 Ch31Ch31 Ch0Ch0 Ch1Ch1 Ch31Ch31DR/XDR/X

FSR/XFSR/X

. . .. . . . . .. . .


Chapter 6, Slide 29

Multi-Channel operationMulti-Channel operation

Ch0Ch0 Ch1Ch1 Ch31Ch31 Ch0Ch0 Ch1Ch1 Ch31Ch31DR/XDR/X

FSR/XFSR/X

. . .. . . . . .. . .

You can You can enableenable or or disabledisable any channel. any channel.

Master (MCR)Master (MCR)

Rcv En (RCER)Rcv En (RCER)

Xmt En (XCER)Xmt En (XCER)

Multi-ChannelMulti-Channel

RCER/XCER Enable BitsRCER/XCER Enable BitsEnableEnable [1][1]DisableDisable [0][0]

003131

003131

RCERRCER

XCERXCER

00111111……00


Chapter 6, Slide 30

MemoryMemory

44 33 22 11Frame 3Frame 3

Multi-channel exampleMulti-channel example

1133

......

11

11Frame 1Frame 1

44 33 22

33

1144 33 22Frame 2Frame 2

1133

FFrraammeerr

Allows multiple channels (words) to Allows multiple channels (words) to be be independentlyindependently selected for selected for transmit and receive.transmit and receive.

MMccBBSSPP


Chapter 6, Slide 31

EDMA’s can sort each channel EDMA’s can sort each channel into separate buffers!into separate buffers!

MemoryMemory


3333

......

11

11Frame 1Frame 1

44 33 22

11


11

33

FFrraammeerr

MMccBBSSPP

EEDDMMAA

Multi-channel and EDMA combination used Multi-channel and EDMA combination used for channel sortingfor channel sorting


Chapter 6, Slide 32

MemoryMemory


3333

......

11

11Frame 1Frame 1

44 33 22

11


11

33

FFrraammeerr

MMccBBSSPP

EEDDMMAA

EDMA Channel SortingEDMA Channel Sorting

EDMA’s flexible (indexed) addressing allows EDMA’s flexible (indexed) addressing allows it to sort each channel into separate buffers!it to sort each channel into separate buffers!

How do you select channels? ...How do you select channels? ...


Chapter 6, Slide 33

Enable/Disable ChannelsEnable/Disable Channels





003131

003131

RCERRCER

XCERXCER

00110011……

RCER / XCER registers allow you to enable or RCER / XCER registers allow you to enable or disable only 32-channels.disable only 32-channels.

So how does the C6000 supports 128 channels?So how does the C6000 supports 128 channels?


Chapter 6, Slide 34

128 Channels!128 Channels!

0-150-15 16-3116-31 32-4732-47 48-6348-63 64-7964-79 80-9580-95 96-11196-111 112-127112-127ChannelsChannels

AA BB

To be able to support 128 channels the following applies:To be able to support 128 channels the following applies: Channels are broken into Channels are broken into BLOCKBLOCK’s (16 contiguous channels).’s (16 contiguous channels). Up to 32 channels (2 Up to 32 channels (2 BLOCKBLOCK’s) can be enabled at any one time.’s) can be enabled at any one time. Channels are enabled via _CER registers and _BLK bits in MCR.Channels are enabled via _CER registers and _BLK bits in MCR. After 16 channels, McBSP issues After 16 channels, McBSP issues END_OF_BLOCKEND_OF_BLOCK interrupt. interrupt. CPU ISR re-programs RCER (or XCER) for channels 32-47 and CPU ISR re-programs RCER (or XCER) for channels 32-47 and

so on.so on.





003131

003131

RCERRCER

XCERXCER

AA15-015-0BB15-015-0

AA15-015-0BB15-015-0

15151616

15151616

InterruptInterrupt


Chapter 6, Slide 35



SPCRSPCR Serial Port Control RegSerial Port Control RegRCRRCR Receive Control RegReceive Control RegXCRXCR Transmit Control RegTransmit Control RegSRGRSRGR Sample Rate GeneratorSample Rate GeneratorPCRPCR Pin Control RegPin Control Reg

ReceiveReceive

TransmitTransmit

ControlControl

MCRMCR Multi-Channel Ctrl RegMulti-Channel Ctrl RegRCERRCER Rcv Channel Enable RegRcv Channel Enable RegXCERXCER Xmit Channel Enable RegXmit Channel Enable Reg


Chapter 6, Slide 36


Definition of Terms:Definition of Terms: Bit, word or channel, frame and phase.Bit, word or channel, frame and phase.



Chapter 6, Slide 37

Programming the Serial PortProgramming the Serial Port

There are three methods available for programming the serial port:There are three methods available for programming the serial port:

1.1. Writing directly to the serial port registers.Writing directly to the serial port registers.

2.2. Using the Chip Support Library (CSL).Using the Chip Support Library (CSL).

3.3. Graphically using the DSP/BIOS GUI configuration tool.Graphically using the DSP/BIOS GUI configuration tool.


Chapter 6, Slide 38

Programming the Serial Port - DirectProgramming the Serial Port - Direct

(A)(A) Writing directly to the serial port registers:Writing directly to the serial port registers: Although this method is straight forward, it relies on a good understanding of the serial port Although this method is straight forward, it relies on a good understanding of the serial port

functionality.functionality. This method can be tedious and is prone to errors.This method can be tedious and is prone to errors.

#include <c6211dsk.h>#include <c6211dsk.h>

void mcbsp0_init(){ *(unsigned volatile int *)McBSP0_SPCR = 0; *(unsigned volatile int *)McBSP0_PCR = 0; *(unsigned volatile int *)McBSP0_RCR = 0x10040; *(unsigned volatile int *)McBSP0_XCR = 0x10040; *(unsigned volatile int *)McBSP0_DXR = 0; *(unsigned volatile int *)McBSP0_SPCR = 0x12001;}


Chapter 6, Slide 39

Programming the Serial Port - CSL (1/4)Programming the Serial Port - CSL (1/4)

(B)(B) Using the Chip Support Library:Using the Chip Support Library: The CSL provides a C language interface for configuring and controlling the on-chip peripherals, in this case the Serial Ports.The CSL provides a C language interface for configuring and controlling the on-chip peripherals, in this case the Serial Ports. The library is modular with each module corresponding to a specific peripheral. This has the advantage of reducing the code size.The library is modular with each module corresponding to a specific peripheral. This has the advantage of reducing the code size. Some modules rely on other modules also being included, for example the IRQ module is required when using the EDMA module.Some modules rely on other modules also being included, for example the IRQ module is required when using the EDMA module.


Chapter 6, Slide 40

CSL programming procedure:CSL programming procedure:(1)(1) Create handles for the serial ports:Create handles for the serial ports:

(2)(2) Open the serial port:Open the serial port:


MCBSP_Handle hMcbsp;

hMcbsp = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET);


Chapter 6, Slide 41

CSL programming procedure:CSL programming procedure:(3)(3) Create a configuration structure for serial port:Create a configuration structure for serial port:

\Links\\Links\McBSP_Config_Struct.pdfMcBSP_Config_Struct.pdf



Chapter 6, Slide 42


CSL programming procedure (cont):CSL programming procedure (cont):(4)(4) Configure the serial port:Configure the serial port:

(5)(5) Close the Serial Port after use:Close the Serial Port after use:

MCBSP_config(hMcbsp,&ConfigLoopback);

MCBSP_close(hMcbsp);


Chapter 6, Slide 43


Practical example on DSP Code 6711Practical example on DSP Code 6711 Project name: Project name: mcbsp_dynamiccfg.pjtmcbsp_dynamiccfg.pjt

Location: Location: \Code\Chapter 06 - McBSP\Dynamic_CSL_Config\\Code\Chapter 06 - McBSP\Dynamic_CSL_Config\


Chapter 6, Slide 44

Programming the Serial Port using the Programming the Serial Port using the DSP/BIOS GUIDSP/BIOS GUI

(C)(C) DSP/BIOS GUI Interface:DSP/BIOS GUI Interface: With this method the configuration structure is created graphically With this method the configuration structure is created graphically

and the setup code is generated automatically.and the setup code is generated automatically.


Chapter 6, Slide 45

Procedure:Procedure:(1)(1) Create a configuration using the MCBSP Create a configuration using the MCBSP

Configuration manager (eg. mcbspCfg0).Configuration manager (eg. mcbspCfg0).



Chapter 6, Slide 46


Procedure:Procedure:(2)(2) Right click on mcbspCfg0 and select “Properties”, see figures below, Right click on mcbspCfg0 and select “Properties”, see figures below,

and then select “Advanced” and fill all parameters as shown below:and then select “Advanced” and fill all parameters as shown below:


Chapter 6, Slide 47


Procedure:Procedure:(3)(3) Select the serial port you would like to use from the MCBSP Select the serial port you would like to use from the MCBSP

Resource manager (eg. Mcbsp_Port1).Resource manager (eg. Mcbsp_Port1).

Right click and select properties.Right click and select properties.

Select the mcbspCfg0 configuration just created. Select the mcbspCfg0 configuration just created.


Chapter 6, Slide 48


Procedure:Procedure:(4)(4) A file is then generated that contains the configuration code. The file A file is then generated that contains the configuration code. The file

generated for this example is shown on the next slide.generated for this example is shown on the next slide.


Chapter 6, Slide 49


/* Do *not* directly modify this file. It was *//* generated by the Configuration Tool; any *//* changes risk being overwritten. */

/* INPUT mcbsp1.cdb */

/* Include Header File */#include "mcbsp1cfg.h"

/* Config Structures */MCBSP_Config mcbspCfg0 = { 0x00008000, /* Serial Port Control Reg. (SPCR) */ 0x000000A0, /* Receiver Control Reg. (RCR) */ 0x000000A0, /* Transmitter Control Reg. (XCR) */ 0x203F1F0F, /* Sample-Rate Generator Reg. (SRGR) */ 0x00000000, /* Multichannel Control Reg. (MCR) */ 0x00000000, /* Receiver Channel Enable(RCER) */ 0x00000000, /* Transmitter Channel Enable(XCER) */ 0x00000A00 /* Pin Control Reg. (PCR) */};

/* Handles */MCBSP_Handle hMcbsp1;

/* * ======== CSL_cfgInit() ======== */void CSL_cfgInit(){ hMcbsp1 = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET); MCBSP_config(hMcbsp1, &mcbspCfg0);}


Chapter 6, Slide 50


Few remarks:Few remarks:

(1) Notice that values in the code generated are the (1) Notice that values in the code generated are the same as the values inserted using the GUI interface.same as the values inserted using the GUI interface.

/* Do *not* directly modify this file. It was *//* Config Structures */MCBSP_Config mcbspCfg0 = { 0x00008000, /* Serial Port Control Reg. (SPCR) */ 0x000000A0, /* Receiver Control Reg. (RCR) */ 0x000000A0, /* Transmitter Control Reg. (XCR) */ 0x203F1F0F, /* Sample-Rate Generator Reg. (SRGR) */ 0x00000000, /* Multichannel Control Reg. (MCR) */ 0x00000000, /* Receiver Channel Enable(RCER) */ 0x00000000, /* Transmitter Channel Enable(XCER) */ 0x00000A00 /* Pin Control Reg. (PCR) */};


Chapter 6, Slide 51


Few remarks:Few remarks:

(2) Do not forget to close the serial port after use.(2) Do not forget to close the serial port after use.

(3) To visualise the output (3) To visualise the output of the logprintf () of the logprintf () function make sure function make sure that the that the Message Log Message Log window is open window is open (DSP/BIOS > Message (DSP/BIOS > Message Log).Log).


Chapter 6, Slide 52

Programming the Serial Port - CSL (4/4)Programming the Serial Port - CSL (4/4)Practical examplePractical example

Project name: Project name: mcbsp_staticcfg.pjtmcbsp_staticcfg.pjt

Location: Location: \Code\Chapter 06 - McBSP\Static_CSL_Config\\Code\Chapter 06 - McBSP\Static_CSL_Config\

Extra Topic: Extra Topic: Digital Digital LoopbackLoopback

Chapter 6Chapter 6

Multi-channel Buffered Serial Port Multi-channel Buffered Serial Port (McBSP)(McBSP)

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Chapter 6 Multi-channel Buffered Serial Port (McBSP)