CHAPTER 6 THREE-LEVEL INVERTER WITH LC FILTERshodhganga.inflibnet.ac.in/bitstream/10603/50214/11/11... · 2018-07-03 · of the inverter to a smooth profile. 6.3 DIODE CLAMPED THREE-LEVEL

97

CHAPTER 6

THREE-LEVEL INVERTER WITH LC FILTER

6.1 INTRODUCTION

Multi level inverters are proven to be an ideal technique for

improving the voltage and current profile to closely match with the sinusoidal

profile in order to reduce the voltage and current harmonics. Various filtering

techniques discussed in previous chapters minimize the harmonics present in

the stator input and torque ripple in the output of the BLDC motor. The

passive filters used in minimizing the harmonics and torque ripple are limited

to a narrow range of speed and load operation of the motor. The Fuzzy logic

based dynamic pulse width modulation technique reduces the harmonics, but

it needs adequate training to tune the fuzzy system based on the load

requirements. The shunt active filter is effective in minimizing the current

harmonics and the voltage harmonics is still to be reduced.

Multi level inverter topologies are prominently used for shaping the

voltage and current profile close to the sinusoidal profile. This in turn

provides the smooth torque profile of the motor. So there is a need of altering

the inverter system for the BLDC motor drive which can reduce the

harmonics and improve the performance. The conventional two-level inverter

for BLDCM shall be replaced by the three-level inverter where the voltage

and current profile can be improved for minimizing the harmonics.

98

Multilevel inverters with different Pulse Width Modulation (PWM)

techniques are proposed for medium and high voltage applications for

converting the pulsating two level AC voltages to near sinusoidal nature.

Rodriguez et al (2002) and Shi et al (2010) discussed different types of three

phase multi-level inverters. Diode Clamped Inverter, Flying Capacitor

Inverter and Cascade Inverter, Cascaded H-Bridge inverters are some of the

multilevel inverter topologies applied to different applications. Three-level

inverter has many advantages such as low harmonic distortion, low switching

frequency, and lower common mode voltages, near sinusoidal output voltage,

less requirement of filtering. Wang & Ahmadi (2010) and Zare et al (2011)

stated that the multilevel inverters have a unique advantage of low dv/dt,

which reduces the danger of motor failure due to high frequency switching.

Moreover, the possibility of achieving smooth sinusoidal profile by altering

the switching pattern of the multilevel inverters is discussed.

Perez & Leon (2010) Zhao et al (2012) pointed out that the three-

level diode clamped inverters are widely applied in control of medium voltage

drives due to the simplicity in inverter topology and the ease of control

methodology. Bouhali & Rizoug (2013) stated that higher level inverters are

used to obtain a close match with the sinusoidal profile of voltage and current.

With multilevel inverter topology it is possible to attain low Total Harmonic

Distortion in both voltages as well as current. As the level of inverter

increases, the complexity of the controller also increases and the cost of the

controller also will increase.

The objective of the work described in this chapter is to experiment

the possible implementation of a diode clamped three level inverter as the

commutation system for the BLDC motor to reduce the harmonic components

in both voltage and current input to motor. A three-level diode clamped

99

inverter cascaded with a low pass filter is found to be a low cost, less complex

system, which can improve the performance of the BLDC motor.

Figure 6.1 shows the overall functional block diagram of the three-

level inverter with the passive filter for the BLDC motor drive system which

is discussed in this chapter. The conventional two level inverter which is the

commutation system is replaced with the diode clamped three-level inverter.

The three phase output of the inverter is connected to the stator of the motor

through the passive LC filter which can minimize the higher order harmonics

present in the stator voltage and current. The field programmable gate arrays

(FPGA) performs the control action to be implemented and generates the

switching gate signals for the three-level inverter in synchronization with the

instantaneous position of the rotor.

Figure 6.1 Functional Blocks of the three-level inverter with passive filter

Drive System

Three Level Inverter

BLDCM

+

_ DC Input

Decoder/ Gate Drive System

Three Level Inverter

Controller

(FPGA)

Hall Signals

Filter

Passive LC Filter

Gate Signals

G1. . . . . . . G12

This work is distinct from the conventional threeapplications used in power system applications. The conventional threeinverter operates with fixed fundamental frequency. But the threeinverter acts as the commutation system for the BLDCM operates with variable fundamental frequency proportional to the instantaneous speed of the motor. Further, the commutation sequthe Hall positional bits from the BLDCM. The gate switching signals for this three level inverter operation is generated by the Field Programmable Gate Array which acts as the controller for this motor.

6.2 FUNCTIONAL ELEMENTS

The functional elements of the three level inverter based commutation system for the brushless DC motor drive is presented in Figure 6.2. The BLDCM is connected with the diode clamped threeinverter in cascade with the LC filter. The FPGA (Spartan 3) is used as the controller for the three- level inverter to generate the 12 switching gate pulse for the three level operation of the inverter. The speed is controlled by the conventional voltage control method using PI

Figure 6.2 Functional elements of the three level inverter based BLDC motor drive

This work is distinct from the conventional three-level inverter applications used in power system applications. The conventional threeinverter operates with fixed fundamental frequency. But the threeinverter acts as the commutation system for the BLDCM operates with variable fundamental frequency proportional to the instantaneous speed of the motor. Further, the commutation sequence of each phase will be decided upon the Hall positional bits from the BLDCM. The gate switching signals for this three level inverter operation is generated by the Field Programmable Gate Array which acts as the controller for this motor.

FUNCTIONAL ELEMENTS OF THE SYSTEM

The functional elements of the three level inverter based commutation system for the brushless DC motor drive is presented in Figure 6.2. The BLDCM is connected with the diode clamped three

the LC filter. The FPGA (Spartan 3) is used as the level inverter to generate the 12 switching gate pulse

for the three level operation of the inverter. The speed is controlled by the conventional voltage control method using PI control.

Functional elements of the three level inverter based BLDC

FPGA Controller

Signal Conditioner

iabc

100

level inverter applications used in power system applications. The conventional three-level inverter operates with fixed fundamental frequency. But the three-level inverter acts as the commutation system for the BLDCM operates with variable fundamental frequency proportional to the instantaneous speed of the

ence of each phase will be decided upon the Hall positional bits from the BLDCM. The gate switching signals for this three level inverter operation is generated by the Field Programmable Gate

The functional elements of the three level inverter based commutation system for the brushless DC motor drive is presented in Figure 6.2. The BLDCM is connected with the diode clamped three-level

the LC filter. The FPGA (Spartan 3) is used as the level inverter to generate the 12 switching gate pulse

for the three level operation of the inverter. The speed is controlled by the

Functional elements of the three level inverter based BLDC

101

The BLDCM consists of three Hall Sensors displaced in 120° each

in the stator of the motor. This gives the instantaneous position of the rotor.

Also the pulse width of a Hall sensor output pulse is directly proportional to

the speed of the motor. The phase current data and the instantaneous speed of

the motor are fed to the FPGA through the analog to digital converter which

are used for speed control action. The switching signal to the inverter are

combined with the PWM signals to perform the commutation and speed

control of the motor. A low pass LC filter is used to filter out the high

frequency harmonic components and to transform the stepped voltage output

of the inverter to a smooth profile.

6.3 DIODE CLAMPED THREE-LEVEL INVERTER

The diode clamped three phase three-level inverter is shown in

Figure 6.3. The DC voltage applied from the rectifier (Vdc1) is divided into

three voltage levels by the two bulk identical capacitors (C) connected in

series. The central point between the capacitor is assigned as neutral point “n”

and the lower reference point is assigned as “0”.

Figure 6.3 Diode clamped three- Level inverter

The phase voltage between any phase to neutral point (V

Vcn) has three states: Vdc1/2, 0,

“a” clamp the switch voltage half the level of V

switches on phase ‘a’. The fundamental modes of operation of diode clamped

three-level inverter for forward and reverse current is described in six current

paths. The one phase of the inverter three level operation is shown in modes

A, B, C, D, E and F as shown in the

positive, zero and negative voltage states in the forward current direction.

Figure 6.4 Fundamental modes of three phase “a”

Depends on the direction of current and the switching

current chose either the switching device or the forward biased diode which is

shown in Figure 6.4. The phase voltage with reference to the neutral point

(Van) is an AC voltage with three levels +V

with reference to the point “0” (V

Vdc1, the voltage difference between V

states and the phase voltage levels for phase “a” is tabulated in Table 6.1.

The phase voltage between any phase to neutral point (V

/2, 0, -Vdc1/2. The two diodes D1 and D11 of phase

“a” clamp the switch voltage half the level of Vdc1. Sa1, Sa2, Sa3 and Sa4

hase ‘a’. The fundamental modes of operation of diode clamped

level inverter for forward and reverse current is described in six current


A, B, C, D, E and F as shown in the Figure 6.4. The A, B, C modes are for


Fundamental modes of three-level inverter operation for

Depends on the direction of current and the switching state the



) is an AC voltage with three levels +Vdc1, 0 and –Vdc1. The phase voltage

e to the point “0” (Va0) is DC with three levels 0, +Vdc1

, the voltage difference between Van and Va0 is Vdc1/2. The switching


102

The phase voltage between any phase to neutral point (Van, Vbn,

of phase

a4 are the

hase ‘a’. The fundamental modes of operation of diode clamped

level inverter for forward and reverse current is described in six current


Figure 6.4. The A, B, C modes are for


level inverter operation for

state the



. The phase voltage

dc1/2 and

/2. The switching


103

Table 6.1 Diode clamped three-level inverter output voltage level and switching states for phase “a”

Switching states Phase Voltage

(Van)

Phase voltage

(Va0) Sa1 Sa2 Sa3 Sa4

1 1 0 0 +Vdc1/2 +Vdc1 0 1 1 0 0 +Vdc1/2 0 0 1 1 -Vdc1/2 0

The brushless DC motor is constructed with three Hall Sensors

positioned in 120° apart on the stator. The stator windings of the BLDC motor

have to be energized in coordination with the hall positional bits. The

switching table for the three level inverter operations with hall positional bits

is presented in Table 6.2.

Table 6.2 Switching table for three-level inverter for BLDCM

Stat

es

Hall Input Inverter Switching Pulse Phase a Phase b Phase c

HA

HB

HC

S a1

S a2

S a3

S a4

S b1

S b2

S b3

S b4

S c1

S c2

S c3

S c4

1 1 0 1 1 1 0 0 0 0 1 1 0 1 1 0 2 1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 3 1 1 0 0 1 1 0 1 1 0 0 0 0 1 1 4 0 1 0 0 0 1 1 1 1 0 0 0 1 1 0 5 0 1 1 0 0 1 1 0 1 1 0 1 1 0 0 6 0 0 1 0 1 1 0 0 0 1 1 1 1 0 0

The Table 6.2 indicates the switching cycles for the switching

devices of the three level inverter in order to obtain the continuous three

phase output for the stator input of the motor. The 0 and 1 corresponds to

phases indicates the ON and OFF states respectively of the switching devices

for the three level inverter in coordination with the Hall sensor positional

104

three bit code. Figure 6.5 shows the simulated switching gate pulses for a

specific phase “a” of the three-level inverter. At any instant two switching

devices will be in on state as per the switching table indicated in Table 6.2

Figure 6.5 Three-level Switching pulse for Phase “a” (Sa1-Sa4)

6.4 FPGA CONTROLLER FOR THREE-LEVEL INVERTER

Programmable Gate Array (SPARTON 3E) is used to generate the

12 switching pulses of the three-level inverter and also to perform the speed

control of the motor. The three Hall sensor positional bits (HA, HB and HC) are

given as the input to the FPGA for deciding the commutation of stator coil of

the BLDCM. The pre processed three phase current input is given as 12 bit

digital data to the controller for PI speed control action. The speed control

action is performed using the V/f control method. The speed of the motor is

estimated from the hall pulses. The duration of each pulse is directly related to

the speed. The top level schematic of the FPGA controller for three-level

inverter for the BLDC motor is presented in Figure 6.6.

Time (s)

105

Figure 6.6 Top level schematic of the FPGA controller for Three-level inverter

6.5 DESIGN OF FILTER ELEMENTS

The higher order harmonics produced during the switching of power devices of the inverter, causes EMI problems. Akagi & Tamura et al (2006) stated that the EMI problems can be rectified using a low pass filter with the appropriate frequency limit. The lower order harmonics are minimized by the three-level inverter and the higher order harmonics are reduced by the passive low pass filter. The filter elements are designed based on the motor parameters and the range of fundamental frequencies of stator voltage.

Table 6.3 Design Parameters

Parameter Range Units

Max. Motor EMF (Line – Line) 200 Volts

Speed (rated) 6000 rpm

Stator Current (rated) 7.2 Amps

Stator Resistance (Line-Line) 10.4 Ohms

Stator Inductance (Line-Line) 43 MilliHenrys

Number of poles 4 -

The Design parameters and specification of the motor used for real

time experimentation is given in Table 6.3. For the wide range of speed of the

motor specified, for a 4 pole BLDC motor, the fundamental frequency of the

stator voltage varies from DC level to 200Hz for the maximum speed of

6000rpm. The low pass filter is designed to limit the high frequency

component of voltage above 200Hz. The filter elements are designed based

on equation (6.1) and (6.2).

* fo

c

ZL Henry

0

1 Z * * fc

C Farads

Where Zo-characteristic impedance in ohms, C

Farads, L-Inductance in Henries, f

Figure 6.7 Low pass LC harmonic Filter a) Circuit filter

The Design parameters and specification of the motor used for real



rom DC level to 200Hz for the maximum speed of



on equation (6.1) and (6.2).

Henry

Farads

characteristic impedance in ohms, C-Capacitance in

Inductance in Henries, fc-Cutoff frequency in Hertz.

(a)

(b)

Low pass LC harmonic Filter a) Circuit b) Response of

106

The Design parameters and specification of the motor used for real-



rom DC level to 200Hz for the maximum speed of



(6.1)

(6.2)

Capacitance in

b) Response of the

107

The Figure 6.7 shows the low pass LC filter and the response of the

filter for the cutoff frequency of 200Hz. L1 2 1is filter inductance,

L2- is considered as the line-line inductance of the stator winding, C- filter

capacitance. For the characteristic impedance of 50 ohms, based on the

equation (6.1) and (6.2), value of L1 and L2 are approximately 43mH and the

capacitance C is 31.83µF.

6.6 RESULTS AND DISCUSSIONS

This work is simulated using MATLAB/Simulink environment to

investigate the performance enhancement in terms of harmonics reduction. An

experimental prototype was developed to test the effectiveness of the

methodology. The experimented results and the simulated results confirm the

reduction in harmonics.

6.6.1 Simulation Results

The simulated stator voltage, stator current for the diode clamped

three-level inverter applied to BLDCM is presented for analyzing the

reduction in harmonics. The phase- phase stator voltage output of the three-

level inverter (Vab1, Vbc

1and Vca1) before filtering is presented in Figure 6.8.

The three level stator voltage profile exhibits the close match with the stepped

sinusoidal profile.

108

Figure 6.8 Stator voltages between two phases of the three-level inverter (Vab

1, Vbc1, Vca

1)

Figure 6.9 Three phase stator voltage and current to the BLDCM with load of 2Nm

The simulated three phase stator voltage and current during the

steady operation of the BLDCM are presented in Figure 6.9. The stepped

sinusoidal profile is transformed towards the smooth sinusoidal profile by the

LC filter. The current profile also transformed towards the sinusoidal profile.

This transformed voltage and current profile contain less harmonic

components.

109

Figure 6.10 Stator voltage and current with a step change of load at 0.5 s (a) Three phase stator voltage (b) Three phase stator current (c) Phase-phase stator voltage (d) Per phase stator current

Figure 6.10 shows the simulated stator voltage and current with the

step change of load (2Nm) at 0.5s time. Figure 6.10a shows the three phase

stator voltage. The instant at which the load applied, the speed drops. The PI

controller responds immediately to maintain the speed by increasing the stator

voltage by the V/f control method. So a rise in stator voltage is observed after

the load applied at the simulation time of 0.5s. Simultaneously the stator

current also increases proportional to the load shown in Figure 6.10b. The

phase to phase voltage and the phase current are shown in Figure 6.10c and

6.10d respectively.

(a)

(d)

(c)

(b)

Time (s)

Time (s)

Time (s)

Time (s)

V

A

V

A

110

(a)

(b)

Figure 6.11 a) Speed profile of the BLDCM (b) Torque Profile of BLDCM

The speed and the torque profile of the BLDC motor are shown in

Figure 6.11. The simulation is carried out for the reference speed of 1000rpm

and the closed loop PI speed controller is designed to maintain the speed. The

load applied to the motor at 0.5s causes a dip in the speed and further the

speed is maintained by the controller by increasing the stator voltage. The

corresponding variation of torque is observed in Figure 6.11b. It is observed

that the hysteresis width of the torque pulsation is reduced in three-level

inverter than the conventional two level inverter controlled BLDC motor.

Figure 6.12 (a) Simulated stator current profile and Harmonics graph (b) Simulated

The harmonic spectrum of the simulated stator voltag

current are presented in Figure 6.12. The fundamental frequency is basically

related to the speed of the motor and it is also proportional to the f

the back-emf. Figure 6.12a presents the harmonic spectrum of the stator

current, and is 4.32%THD. Figure 6.12b shows the harmonic spectrum of the

stator voltage and is 3.40%THD. The third order harmonics are very low and

the 5th order current harmonics are almost 4% with reference to the

fundamental.

(a)

(b)

(a) Simulated stator current profile and Harmonics graph (b) Simulated Stator voltage profile and harmonic graph

The harmonic spectrum of the simulated stator voltage and stator

presented in Figure 6.12. The fundamental frequency is basically

related to the speed of the motor and it is also proportional to the frequency of

emf. Figure 6.12a presents the harmonic spectrum of the stator


ltage and is 3.40%THD. The third order harmonics are very low and

harmonics are almost 4% with reference to the

111

(a) Simulated stator current profile and Harmonics graph Stator voltage profile and harmonic graph

e and stator

presented in Figure 6.12. The fundamental frequency is basically

requency of

emf. Figure 6.12a presents the harmonic spectrum of the stator


ltage and is 3.40%THD. The third order harmonics are very low and

harmonics are almost 4% with reference to the

112

6.6.2 Experimental Results

Figure 6.13 shows the experimented results of stator voltage and the harmonic spectrum before passing through the LC filter. From Figure 6.13a, it is observed that the voltage profile is matching towards sinusoidal profile. The harmonic spectrum presented in Figure 6.13.b shows that the lower order voltage harmonics are reduced much and the THD is observed as 24.98%. The higher order harmonics still exists in smaller level which contributes rise of THD value. These higher order harmonics can be reduced by passing this voltage profile through the LC low pass filter.

(a)

(b)

Figure 6.13 (a) Experimented three phase inverter output voltage before LC filter (b) Voltage Harmonics spectrum for stator voltage

Waveform V260.47 Vrms, 24.98 %THD

0102030405060708090

100

1 5 10 15 20 25 30 35 40 45 50

-100.0

-50.00

0.000

50.00

V

4 mSec/Div

113

The stator voltage after the LC filter section is presented in

Figure 6.14a, and the harmonic spectrum is presented in Figure 6.14b. It is

observed that the harmonic components are very much reduced. The THD is

5.86% which very closely matching with the IEEE STD 519 value of 5%.

(a)

(b)

Figure 6.14 a) Experimented three phase stator voltage to the BLDCM b) Harmonics spectrum for stator voltage

-60.00

-40.00

-20.00

0.000

20.00

40.00

60.00

V

1/29/2013 1/29/201321.308 (mS)

Waveform V240.28 Vrms, 5.86 %THD

0102030405060708090

100

1 5 10 15 20 25 30 35 40 45 50

114

The Stator current and the corresponding harmonic spectrum of the motor running at steady no load is presented in Figure 6.15. It is observed that the current profile is well matched with the sinusoidal profile. The harmonic spectrum of stator current is presented in Figure 6.15b. The harmonics are observed as 13.1%. The 5th order current harmonics is 11.1%, but the higher order harmonics are greatly reduced. The consolidated voltage and current harmonics for both simulation and experimentation are presented in Figure 6.16a and Figure 6.16b.

(a)

(b)

Figure 6.15 (a) Experimented three phase stator current (b) Harmonic spectrum for stator current

-400.0

-200.0

0.000

200.0

400.0

A

Waveform I1333.23 Arms, 13.10 %THD

0102030405060708090

100

1 5 10 15 20 25 30 35 40 45 50

Figure 6.16 Harmonics comparison a) current harmonics b) voltage harmonics

The consolidated torque ripple analysis of the previous

methodologies and for the three level inverter based commutations system are

presented in Figure 6.18. It is observed that the torque ripple is considerably

reduced with reference to the previous meth

based drive system, the passive filter and the dynamic PWM methods. The

torque ripple linearly varies for the increase of load.

methodology may be suitable for BLDC motor with high voltage,

and light load applications.

05

10152025303540

%THD (I) Simulated

32.06

0

10

20

30

40

50

60

%THD (V) Simulated

42.36

(a)

(b)

Harmonics comparison a) current harmonics b) voltage




reduced with reference to the previous methodologies of two level inverter


torque ripple linearly varies for the increase of load. It is observed that this

methodology may be suitable for BLDC motor with high voltage, high spee

%THD (I) Simulated %THD (I) Experimented

32.0636.96

4.32

13.1

Two level inverter

Three level inverter with filter

%THD (V) Simulated %THD (V) Experimented

42.36

51.96

3.4 5.86

Two level inverter

Three level inverter with filter

115

Harmonics comparison a) current harmonics b) voltage




odologies of two level inverter


t is observed that this

igh speed

116

Figure 6.17 Torque Ripple analysis

6.7 CONCLUSION

This chapter describes a combined diode clamped three level

inverter which acts as a commutation system cascaded with an LC filter for a

Brushless DC motor for minimizing the harmonics present in the stator

voltage and current. The entire system is simulated using MATLAB/Simulink

and it is observed that there is a considerable reduction in harmonics. The real

time experimentation is carried out with an FPGA controller for investigating

the effectiveness of the system. The voltage harmonics are considerably

reduced and the current harmonics are marginally reduced. The torque ripple

for this motor drive is also reduced.

The next chapter presents the consolidated experimental outcome

of various methodologies applied on the BLDC motor drive system for

reducing the harmonics and torque ripple.

0

1

2

3

4

5

6

0 1 2 3 4 5

Rip

ple

Tor

que

(Nm

)

Load (kg)

Two level inverter

Two level inverter with filterTwo level inverter with dynamic PWMTwo level inverter with SAFThree level inverter with filter

Documents

CHAPTER 6 THREE-LEVEL INVERTER WITH LC FILTERshodhganga.inflibnet.ac.in/bitstream/10603/50214/11/11... · 2018-07-03 · of the inverter to a smooth profile. 6.3 DIODE CLAMPED THREE-LEVEL