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Chapter 7. Designing Sequential Logic Circuits. Rev 1.0: 05/11/03 1.1: 5/23/03 1.2: 5/30/03. Sequential Logic. Finite State Machine (FSM) Pipelined System. 2 storage mechanisms: Positive feedback (SRAM) Charge-based (DRAM). Naming Conventions. In our textbook: - PowerPoint PPT Presentation
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Chapter 7Chapter 7
Designing SequentialDesigning SequentialLogic CircuitsLogic Circuits
Rev 1.0: 05/11/031.1: 5/23/031.2: 5/30/03
Sequential LogicSequential Logic
(1) Finite State Machine (FSM)
(2) Pipelined System
2 storage mechanisms:
- Positive feedback (SRAM)
- Charge-based (DRAM)
Naming ConventionsNaming Conventions
In our textbook: a latch is Level-sensitive flip-flop a register is Edge-triggered flip-flop
There are many different naming conventions For instance, many books call Edge-
triggered elements flip-flops (asynchronous JK, SR) This leads to confusion
Latch v.s. RegisterLatch v.s. Register Latch
stores data when clock is low (or high)
D
Clk
Q D
Clk
Q
Register
stores data when clock rises (on edges)
Clk Clk
D D
Q Q
LatchesLatches
In
clk
In
Out
Positive Latch
CLK
DG
Q
Out
Outstable
Outfollows In
In
clk
In
Out
Negative Latch
CLK
DG
Q
Out
Outstable
Outfollows In
transparent
holdholdhold
Latch-Based DesignLatch-Based Design
• N latch is transparentwhen = 0; hold when = 1
• P latch is transparent when = 1; hold when = 0
NLatch
Logic
Logic
PLatch
Timing DefinitionsTiming Definitions
t
CLK
t
D
tc - q
tholdtsu
t
Q DATASTABLE
DATASTABLE
Register
CLK
D Q
•(a) Setup time (T_su): the time before the clock edge that the D input has to be stable•(b) Hold time (T_hold): the time after tue clock edge that the D input has to main stable•(c) Clock-to-Q delay (Tc-q): the delay from the positive clock input to the new value of the Q output.
Characterizing TimingCharacterizing Timing
Clk
D Q
tC-Q
Clk
D Q
tC-Q
tD-Q
Register Latch
Maximum Clock FrequencyMaximum Clock Frequency
FF’s
LOGIC
tp,comb
Also:
tcdreg + tcdlogic >= thold
tcd:
Contamination Delay
= Minimum delay
tclk-Q + tp,comb + tsetup <= T
CLK
T
tclk-Q + tp,comb + tsetup
Mux-Based LatchesMux-Based LatchesNegative latch(transparent when CLK= 0)
Positive latch(transparent when CLK= 1)
CLK
1
0D
Q 0
CLK
1D
Q
InClkQClkQ InClkQClkQ
Mux-Based LatchMux-Based Latch
CLK
CLK
CLK
D
Q
Mux-Based LatchMux-Based Latch
CLK
CLK
CLK
CLK
QM
QM
NMOS only Non-overlapping clocks
Writing into a Static LatchWriting into a Static Latch
CLK
CLK
CLK
D
Q D
CLK
CLK
D
Converting into a MUXForcing the state(can implement as NMOS-only)
Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states
Master-Slave (Edge-Triggered) RegisterMaster-Slave (Edge-Triggered) Register
1
0D
CLK
QM
Master
0
1
CLK
Q
Slave
QM
Q
D
Two opposite latches trigger on edgeAlso called “master-slave latch Pair “
Negative LatchPositive Latch
Master Slave
Master-Slave RegisterMaster-Slave RegisterMultiplexer-based latch pair
QM
Q
D
CLK
T2I2
T1I1
I3 T4I5
T3I4
I6I5
INVpdTXpdQC
Hold
TXpdINVpdSU
TTITT
T
TTIITIT
,,63
,,2311
0
3
Setup Time of MS-RegisterSetup Time of MS-Register
D
Q
QM
CLK
I2 2 T2
2 0.5
Volt
s
0.0
0.2 0.4time (nsec)
(a) Tsetup5 0.21 nsec
0.6 0.8 10
0.5
1.0
1.5
2.0
2.5
3.0
DQ
QM
CLK
I2 2 T2
2 0.5V
olt
s
0.0
0.2 0.4time (nsec)
(b) Tsetup5 0.20 nsec
0.6 0.8 10
0.5
1.0
1.5
2.0
2.5
3.0
•I2-T2 : I2 output to T2
•Check input of T2 and output of T2 are the same
Clk-Q DelayClk-Q Delay
D
Q
CLK
2 0.5
0.5
1.5
2.5
tc- q(lh)
0.5 1 1.5 2 2.50time, nsec
tc- q(hl)
Reduced Clock Load Reduced Clock Load Master-Slave RegisterMaster-Slave Register
D QT1 I1
CLK
CLK
T2
CLK
CLKI2
I3
I4
c.f: 8 Clock loads in Mater-Slave Register Design
Avoiding Clock OverlapAvoiding Clock OverlapCLK
CLK
A
B
(a) Schematic diagram
(b) Overlapping clock pairs
X
D
Q
CLK
CLK
CLK
CLK
SR Flip-Flop: Cross-Coupled PairsSR Flip-Flop: Cross-Coupled Pairs
Forbidden State
QRS Q
Q00 Q
101 0
010 1
011 0
SQ
RQ
Cross-coupled NORs
S
R
Q
Q
NOR-based Set-Reset
Flop-Flop
S
QR
Q
Cross-coupled NANDs
Clocked NOR-based SR Flip-FlopClocked NOR-based SR Flip-Flop
M1
M2
M3
M4
Q
M5S
M6CLK
M7 R
M8 CLK
VDD
Q
Added Clock Control
This asynchronous SR FFis NOT used in datapaths any more,but is a basic building memory cell
SQ
RQ
Cross-coupled NORs
Sizing IssuesSizing Issues
Output voltage dependence on transistor width
Transient response
4.03.53.0W/L5 and 6
(a)
2.52.00.0
0.5
1.0
1.5
2.0
Q (
Vo
lts)
time (ns)
(b)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20
1
2
W = 1 m
3
Vo
lts
Q S
W = 0.9 m
W = 0.8 m
W = 0.7 mW = 0.6 m
W = 0.5 m
Storage MechanismsStorage Mechanisms
D
CLK
CLK
Q
Dynamic (charge-based)CLK
CLK
CLK
D
Q
Static
Clock OverlapClock Overlap
T0-0: T1 and T2 on Race Condition
Making a Dynamic Latch Pseudo-StaticMaking a Dynamic Latch Pseudo-Static
D
CLK
CLK
D
Adding a weak feedback inverter
Clocked CMOS (CClocked CMOS (C22MOS)MOS)
M1
D Q
M3CLK
M4
M2
CLK
VDD
CL1
X
CL2
Master Stage
M5
M7CLK
CLK M8
M6
VDD
“ Keepers” can be added to make circuit pseudo-static
Clock 0 1
Master Evaluate Hold
Slave High-impedance: Hold
Evaluate
Output Previous value stored in CL2
New Value of CL1
Insensitive to Clock-OverlapInsensitive to Clock-Overlap
M1
D Q
M4
M2
0 0
VDD
X
M5
M8
M6
VDD
(a) (0-0) overlap
M3
M1
D Q
M2
1
VDD
X
M71
M5
M6
VDD
(b) (1-1) overlap
True Single-Phase Clocked Register (TSPC)True Single-Phase Clocked Register (TSPC)
CLKIn
VDD
CLK
VDD
In
Out
CLK
VDD
CLK
VDD
Negative latch(transparent when CLK= 0)
Positive latch(transparent when CLK= 1)
A register can be constructed by cascading Positive and Negative Latches 12 transistors are used!
Including Logic in TSPCIncluding Logic in TSPC
CLKIn CLK
VDDVDD
QPUN
PDN
CLK
VDD
Q
CLK
VDD
In1
In1 In2
AND latchExample: logic inside the latch
Pipelined TSPC CMOS SystemPipelined TSPC CMOS System
(a) Compared with NORA CMOS, we need two extra transistors per stage. But we can operate at a true singe-phase clock signal.
(b) Very attractive from system-design point of view.
Positive Edge-triggered Register in TSPCPositive Edge-triggered Register in TSPC
CLK
CLK
D
VDD
M3
M2
M1
CLK
Y
VDD
Q
Q
M9
M8
M7
CLK
X
VDD
M6
M5
M4
TSPC-based Positive Edge-Triggered DFFTSPC-based Positive Edge-Triggered DFF
From Referenced Textbooks: [1] “CMOS Integrated Circuits: Analysis and Design,” 3rd Ed., by Sung-Mo Kang and Yusuf Leblebici, McGraw-Hill, 2003.
Pipelined Systems using Dynamic Pipelined Systems using Dynamic CMOS CircuitsCMOS Circuits
PipeliningPipeliningR
EG
RE
G
RE
G
log
a
CLK
CLK
CLK
Out
b
RE
GR
EG
RE
G
log
a
CLK
CLK
CLK
RE
G
CLK
RE
G
CLK
Out
b
Reference Pipelined
T_(non-pipe)
= 3 x T_(pipeline)
PipeliningPipelining
)(pipelined),,max(
pipeline)(non
sulogpd,abspd,addpd,qcmin,
sulogicpd,qcmin
tttttT
tttT
pipe
At the expense of “Latency (input-to-output delay)”
Not good for interactive communicaitons
Latch-Based PipelineLatch-Based Pipeline
F G
CLK
CLK
In Out
C1 C2
CLK
C3
CLK
CLK
Compute F compute G
Hold FHold G
Be carefulof Race!
Review of NP-Domino LogicReview of NP-Domino Logic
NP-Domino Logic ExampleNP-Domino Logic Example
NORA CMOS NORA CMOS
(a) Evaluation at Phi=1(b) Evaluation at Phi=0(c) Pipelined NORA CMOS
system
Latch-based Pipeline using C2MOSLatch-based Pipeline using C2MOS
Race-free as long as function F (implemented by static logic) between the Latches are Non-inverting!
Potential Race Condition Potential Race Condition during 0-0 (if F is inverting)during 0-0 (if F is inverting)
Example of NORA-CMOS (I)Example of NORA-CMOS (I)
Example of NORA-CMOS (II)Example of NORA-CMOS (II)NOR2 + INV = OR2
(Dynamic + Static Stages)
SummarySummary
Sequential circuits need good latches and
registers for speed performance.
Dynamic circuits can realize the pipelined
system in a very efficient and compact way. But
it should be designed with extreme care.
Current trend is NOT to use dynamic CMOS for
normal-speed operations good for design,
maintain, and verification.