Chapter 7 Memory and Programmable Logic


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MEMORY UNIT

A memory unit isa device to which binary

information is transferred for storage andfrom which information is retrieved whenneeded for processing.

A memory unit is a collection of cellscapable of storing a large quantity ofbinary information.

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Types of memories There are two types of memories that are used in

digital systems Random AccessMemory Read Only Memory

The process of storing new information intomemory is referred to as a memory writeinformation and the process of transferring thestored information out of memory is referred toas memory read operation.

RAM can perform both write and read operationwhile ROM allowsonly read operation.

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ROM ROM is a Programmable Logic Device (PLD)

As the ROM can only perform read operation, it means asuitable binary information is already stored (In a processcalled programming the device) inside the memory, whichcan be retrieved or read at any time.

However, the existing information cannot be altered bywritingbecause the ROM can only read; it cannot write.

Programming means that the hardware procedure whichspecifies the bits that are inserted into the hardwareconfiguration of the device.

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Programming Logic Device

A PLD is an integrated circuit with internal

logic gates connected through electronicpathsthat behavessimilarly to fuses.

In start, all fuses are intact. Programming

means that blowing those fuses along thepaths that must be removed in order toobtain the particular configuration of thedesired logic function.

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Memory RAM

Write and Read from the system ROM

Read from the system Written during configuration

Programmable Logic Device ROM PLA FPGA

Symbol used in Array Logic diagrams 7


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Random Access Memory

Block diagram of a Memory unit

It is customary to refer to the number of words (or bytes) in a memory with oneof the letters K(kilo) = 2 10, M(mega) = 2 20, or G(giga) = 2 30

For Example: 4K = 2 12, 16M = 2 24, 8G = 2 33 8


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Random Access Memory

Content of a 1024 16 Memory

The memory unit with acapacity of 1K words of 16bits each

As 1K = 1024 = 2 10 and16bits constitutes of 2bytes so the memory canaccommodate 2048 = 2K bytes

Each binary addressconsists of 10 bits

The memory is named as1K(210) x 16 memory, with10 bits binary address

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Memory Control

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The steps that must be taken for the purposeof transferring a new word to be stored intomemory are as follows

Apply the binary address of the desired word onthe address lines

Apply the data bits that must be stored in memoryto the data input lines

Activate the write input

Write operation

(Cycle Time)

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Write operation

(Cycle Time)

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The steps that must be taken for the purposeof transferring a stored word out of memoryare as follows

Apply the binary address of the desired word onthe address lines

Activate the read input

READ OPERATION

(Access time)

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READ OPERATION

(Access time)

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Type of Memories There are two type of memories

Random Access Memory Sequential Access Memory

RAMs (Volatile Memory) SRAM (Static RAM)

Latches are used to store binary information DRAM (Dynamic RAM)

Store binary information in the form of electrical charges on capacitors

ROMs Non Volatile Memory

CD (PROM) RW/ CD (EPROM) Memory Sticks (EEPROM)

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RAM TYPES - I Followingare different type of RAMs

DRAM (Dynamic RAM) Must be constantly refreshed by CPU or it will lose its information

SDRAM (Synchronous Dynamic RAM) Used in most PCs today

Synchronized by system clock

Faster than DRAM SRAM (Static RAM)

Faster than DRAM

Retainscontents without being refreshed16


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RAM TYPES - II RDRAM (RambusDynamic RAM)

Faster and more expensive than RDRAM

Used in P-IVPCs

DDR-SDRAM (Double Data Rate Synchronous Dynamic RAM) Just Like SDRAM

But higher speed

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Quiz18/1/12

It is required to generate six repeated timingsignalsT 0 through T 5.

Design a circuit using Flip FlopsOnly ACounter and a Decoder

Max Time: 10 mins

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Memory Decoding

In addition to the storage components in amemory unit, there is a need for decodingcircuits to select the memory word specifiedby the input address

Block diagram of a memory cell

BinaryCell

1 bit storingdevice

Enables the cell forReading and Writing

1 for Read and 0for Write

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Memory Cell Logic diagram of 1 Bit storage Cell

0

X

X

X

1

Read = 1

1

1

0

X

X

0

0

1 1

Write = 0

0X

1

0 0

1

0

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Memory Decoding (4x4 RAM)

4 4 (2 2 X 4) RAM

2 bit address 4 bits at eachaddress

00

A memory with 2 k words of nbits per word would require k address lines that goes into ak X 2k decoder

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Coincident Decoding

A decoder with k inputs and 2 k outputsrequires 2 k AND gates with k inputs per gate,the number of inputs and number of gates canbe reduced by employing two decoders in a2D selection scheme

Two k/2 input decoders are used instead of k

input decoder One performs row selection while other

perform column selection22


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Coincident Decoding Two dimensional decoding structure for a 1K

(210) word memoryTwo 5x32

decoders instead

of one 10x1024decoder

5 MSBs ofmemory

address goes

into X

5 LSBs of thememory address

goes into Y

01100

1 0 1 0 0

Example = Consider a word whose address is 404 = 01100 10100

Each word within thememory array is selected bythe coincidence of one X lineand one Y line

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Address Multiplexing

for a 64K DRAM64K = 2 16, so we use two 8 x 256 decoders for 2D decoding i.e. 2 8 x 2 8 = 2 16

ColumnAddress Strobe

Row AddressStrobe

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Read Only Memory Permanent Storage Allows for configuration of devices to be

stored on device without requiring load

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Read Only Memory 32 8 ROM

5 Address Lines 8 bits at each Memory Address

Each OR gatehas 32 inputs

Each connection isprogrammable

(either open or close e.g. fuse)32 x 8 = 256connections

2k

x nROM w illhave k x

2 k decoderand n OR

gates,each ORgate willhave 2 kinputs

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Read Only Memory ROM Truth Table

The programmable connectionsare made according to the

contents of each memory location

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Read Only Memory

Programming the ROM

00000 1011011000001 0001110100010 11000101

11110 0100101011111 00110011

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Read Only Memory Combinational circuit implementation using ROM Input a 3-bit number & Output should be square of

the number

B1 = 0

B0 = A0

8 x 4 ROM wouldbe required

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Read Only Memory Block diagram & truth table

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Types of ROM Mask Programming

Done during the fab process

Programmable ROM (PROM) All fusesare intact (set to 1) and are Blown

Erasable PROM (EPROM) Ultraviolet light used to reprogram

Electronically Erasable PROM (EEPROM) Programmed connections can be erased via

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Programmable Logic Devices

Combinational PLDsImplement functionas sum of minterms

Provides productterms of the function

Sum provided bythe OR gates

Provide sum of productimplementation

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Programmable Logic ArrayF1 = AB+AC+ABC F2 = (AC+BC)

A

AB

BCC

PLA with 3-inputs 4-terms 2-outputs

XOR are used toeither have the

same output or thecompliment outpute.g. XOR(X,1) = X

XOR (X,0) = X

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Programmable Logic Array PLA Programming table:

F1 = AB+AC+ABC F2 = (AC+BC)

If a variable in the product term appear in its true form, the input variable is 1 If a variable in the product term appear in its compliment form, the input variable is 0 If the variable is not there in the product term, the input variable is -

One input of XORconnected to 0

One input of XORconnected to 1

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Programmable Array LogicTypical PAL

PAL with 4-inputs / outputs / sections 3 wide AND- OR array per section

Examplew(A,B,C,D) = (2,12,13)x(A,B,C,D) = (7,8,9,10,11,12,13,14,15)y(A,B,C,D) = (0,2,3,4,5,6,7,8,10,11,15)z(A,B,C,D) = (1,2,8,12,13)

Simplified Boolean Functionsw = ABC +ABCD x = A+BCDy = AB+CD+BD z = ABC+ABCD+ACD+ABCD

= w+ACD+ABCD

Commercial PAL Eight inputs / outputs / sections

with eight wide AND-OR array

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Programmable Array Logic

PAL Programming table:Simplified Boolean Functions

w = ABC +ABCD x = A+BCDy = AB+CD+BD z = ABC+ABCD+ACD+ABCD

= w+ACD+ABCD

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Programmable Array Logic

Simplified Boolean Functionsw = ABC +ABCD x = A+BCDy = AB+CD+BD z = ABC+ABCD+ACD+ABCD

= w+ACD+ABCD

w

x

y

z

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Sequential Programmable

Devices Sequential Programmable Logic Device (SPLD)

Some times referred as simple PLD to differentiateit from complex PLD Complex Programmable Logic Device (CPLD)

Field Programmable Gate Array (FPGA)

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Sequential (Simple) PLDs

The configuration mostly used for SPLD is thecombinational PALtogether with D flip flops

Each section of the SPLD is called a Macrocell A macrocell is a circuit that contains a SOP

combinational logic function and an optional flipflop 39


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SPLD Macrocell

A typical SPLD has from 8 to 10macrocells within one IC package

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Complex PLDs The design of a digital system using PLD often

requires the connection of several devices toproduce the complete specifications.

It is more economical to use a CPLD8-16

macrocells

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Field Programmable Gate Array(FPGA)

A typical FPGA consists of an array ofhundreds or thousands of logic blocks

The logic blocks are surrounded byprogrammable input and output blocks

All the blocks are connected together viaprogrammable interconnections

A typical FPGA logic block consist of look uptables, multiplexers, gatesand flip flops

The look up table is a truth table stored in a SRAM andprovides the combinational circuit functions for the logic

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Field Programmable Gate Array(FPGA)

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Chapter 7 Memory and Programmable Logic