Chapter FourCombinational Logic

1

COMBINATIONAL CIRCUITS

It consists of input variables, logic gates and output variables.

Output is function of input onlyi.e. no feedback

When input changes, output changes (after a delay)

•••

•••

n inputs m outputsCombinational

Circuits

2

COMBINATIONAL CIRCUITS

Analysis Given a circuit, find out its function Function may be expressed as:

Boolean function Truth table

Design Given a desired function, determine its circuit Function may be expressed as:

Boolean function Truth table

CBA

CBA

BA

CA

CB

F1

F2

?

?

?3

ANALYSIS PROCEDURE Boolean Expression Approach

F1=T2+T3= AB'C'+A'BC'+A'B'C+ABCF2=AB+AC+BC

CBA

CBA

BA

CA

CB

F1

F2

T2=ABCT1=A+B+C

F2=AB+AC+BC

F’2=(A’+B’)(A’+C’)(B’+C’)

T3=AB'C'+A'BC'+A'B'C

4

CBA

CBA

BA

CA

CB

F1

F2

ANALYSIS PROCEDURE

We can obtain the truth table directly from the logic diagram

Truth Table Approach

A B C F1 F2

0 0 0= 0 = 0= 0= 0= 0= 0

= 0= 0

= 0= 0

= 0= 0

T2 = 0

T1 = 0

0

0

0

F2 = 0

F’2 = 1

T3 = 0

0 0 0

5

6

Full Adder Circuit

CBA

CBA

BA

CA

CB

F1

F2

ANALYSIS PROCEDURE

Truth Table Approach= 0 = 0= 1= 0= 0= 1

= 0= 0

= 0= 1

= 0= 1

0

1

0

0

0

0

1

1

1

A B C F1 F2

0 0 0 0 00 0 1 1 0

7

CBA

CBA

BA

CA

CB

F1

F2

ANALYSIS PROCEDURE

Truth Table Approach= 0 = 1= 0= 0= 1= 0

= 0= 1

= 0= 0

= 1= 0

0

1

0

0

0

0

1

1

1

A B C F1 F2

0 0 0 0 00 0 1 1 00 1 0 1 0

8

CBA

CBA

BA

CA

CB

F1

F2

ANALYSIS PROCEDURE

Truth Table Approach= 0 = 1= 1= 0= 1= 1

= 0= 1

= 0= 1

= 1= 1

0

1

0

0

1

1

0

0

0

A B C F1 F2

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 1

9

CBA

CBA

BA

CA

CB

F1

F2

ANALYSIS PROCEDURE

Truth Table Approach= 1 = 1= 1= 1= 1= 1

= 1= 1

= 1= 1

= 1= 1

1

1

1

1

1

1

0

0

1

A B C F1 F2

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

B

0 1 0 1

A 1 0 1 0C

B

0 0 1 0

A 0 1 1 1C

F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC10

DESIGN PROCEDURE Given a problem statement:

Determine the number of inputs and outputs Derive the truth table Simplify the Boolean expression for each output Produce the required circuit

Example: Design a circuit to convert a “BCD” code to

“Excess -3” code

4-bits 0-9 values

4-bits Value+3

?11

DESIGN PROCEDURE BCD-to-Excess 3 Converter

A B C D w x y z

0 0 0 0 0 0 1 10 0 0 1 0 1 0 00 0 1 0 0 1 0 10 0 1 1 0 1 1 00 1 0 0 0 1 1 10 1 0 1 1 0 0 00 1 1 0 1 0 0 10 1 1 1 1 0 1 01 0 0 0 1 0 1 11 0 0 1 1 1 0 01 0 1 0 x x x x

1 0 1 1 x x x x1 1 0 0 x x x x1 1 0 1 x x x x1 1 1 0 x x x x1 1 1 1 x x x x

C

1 1 1B

Ax x x x

1 1 x x

D

C

1 1 11

BA

x x x x

1 x x

D

C

1 11 1

BA

x x x x

1 x x

D

C

1 11 1

BA

x x x x

1 x x

D

w = A+BC+BD x = B’C+B’D+BC’D’

y = C’D’+CD z = D’ 12

It needs 7 AND gates and 3 OR gates

13

DESIGN PROCEDURE

w = A + B(C+D)

x = B’(C+D) + B(C+D)’

y = (C+D)’ + CD

z = D’14

A B C D w x y z

0 0 0 0 0 0 1 10 0 0 1 0 1 0 00 0 1 0 0 1 0 10 0 1 1 0 1 1 00 1 0 0 0 1 1 10 1 0 1 1 0 0 00 1 1 0 1 0 0 10 1 1 1 1 0 1 01 0 0 0 1 0 1 11 0 0 1 1 1 0 01 0 1 0 x x x x

1 0 1 1 x x x x1 1 0 0 x x x x1 1 0 1 x x x x1 1 1 0 x x x x1 1 1 1 x x x x

It needs 4 AND gates and 4 OR gates

SEVEN-SEGMENT DECODER a

b

c

g

e

d

f?

w

x

y

z

abcdefg

w x y z a b c d e f g

0 0 0 0 1 1 1 1 1 1 00 0 0 1 0 1 1 0 0 0 00 0 1 0 1 1 0 1 1 0 10 0 1 1 1 1 1 1 0 0 10 1 0 0 0 1 1 0 0 1 10 1 0 1 1 0 1 1 0 1 10 1 1 0 1 0 1 1 1 1 10 1 1 1 1 1 1 0 0 0 01 0 0 0 1 1 1 1 1 1 11 0 0 1 1 1 1 1 0 1 11 0 1 0 x x x x x x x

1 0 1 1 x x x x x x x1 1 0 0 x x x x x x x1 1 0 1 x x x x x x x1 1 1 0 x x x x x x x1 1 1 1 x x x x x x x

y

1 1 1

1 1 1x

wx x x x

1 1 x x

z

BCD code

a = w + y + xz + x’z’ b = . . .c = . . .d = . . .

15

BINARY ADDER – SUBTRACTOR Digital computers perform a variety of information-processing tasks. Among the functions encountered are the various arithmetic operations. The most basic arithmetic operation is the addition of two binary digits.

Half Adder Adds 1-bit plus 1-bit Produces Sum and Carry

HAx

yS

C

x y C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

x+ y───C S

x

y

S

C 16

Full Adder Adds 1-bit plus 1-bit plus 1-bit Two significant bits and a previous carry Produces Sum and Carry

x y z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

x+ y+ z───C S

FAxyz

S

C

y

0 1 0 1

x 1 0 1 0z

y

0 0 1 0

x 0 1 1 1z

S = xy'z'+x'yz'+x'y'z+xyz = x y z

C = xy + xz + yz 17

BINARY ADDER Full Adder

xyzx

y

z

xy

xz

yz

S

C

S = xy'z'+x'yz'+x'y'z+xyz = x y z

C = xy + xz + yz

18

Implementation of full adder in sum of products form

BINARY ADDER Implementation of Full Adder with two half adder

and an OR gate.

x

y

z

S

C

HAxy

z

HAS

C

19

BINARY ADDER c3 c2 c1 .+ x3 x2 x1 x0

+ y3 y2 y1 y0

────────Cy S3 S2 S1 S0

FA

x3 x2 x1 x0

FAFAFA

y3 y2 y1 y0

S3 S2 S1 S0

C4 C3 C2 C1

0

Binary Adder

x3x2x1x0 y3y2y1y0

S3S2S1S0

C0C4

20

Subscript i 3 2 1 0

Input carry 0 1 1 0 Ci

1 0 1 1 xi

0 0 1 1 yi

Sum 1 1 1 0 Si

Output carry

0 0 1 1 Ci+1

21

BINARY SUBTRACTOR

Use 2’s complement with binary adder x – y = x + (-y) = x + y’ + 1

Binary Adder A3 A2 A1 A0 B3 B2 B1 B0

S3 S2 S1 S0

CiCy 1

x3 x2 x1 x0 y3 y2 y1 y0

F3 F2 F1 F022

BINARY ADDER/SUBTRACTOR

Binary Adder A3 A2 A1 A0 B3 B2 B1 B0

S3 S2 S1 S0

CiCy

Mx3 x2 x1 x0 y3 y2 y1 y0

F3 F2 F1 F0

M: Control Signal (Mode) M = 0 F = x + y M = 1 F = x – y

F = x + y’+ 1

y Å 0 = yy Å1 = y'

23

OVERFLOW: When two numbers with n digits each are added and the sum is a number occupying n + 1 digits,we say that an overflow occurred.

Unsigned Binary Numbers

2’s Complement Numbers (signed numbers)

FA

x3 x2 x1 x0

FAFAFA

y3 y2 y1 y0

S3 S2 S1 S0

C4 C3 C2 C1

0

Carry

Overflow

0 1+70 0 1000110+80 0 1010000

+150 1 0010110 1 0-70 1 0111010- 80 1 0110000

-150 0 1101010

25

An overflow cannot occur after an addition if one number is positive and the other is negative. Since adding a positive number to a negative number produces a result whose magnitude is smaller than the larger of the two original numbers.

An overflow may occur when the two numbers added are both (+) or both (-). Consider 8 bit register (127 --- -128).

10 1101 1010-------- 0111

11 1110 1101-------- 1011

01 0011 0110-------- 1001

00 0010 0011-------- 0101

00 0010 1100-------- 1110

11 1110 0100-------- 0010

Addition cases and overflow

OFL OFL

+2+3+5

+3+6-7

-2-3-5

-3-6+7

+2-4-2

-2+4+2

MAGNITUDE COMPARATOR

Compare 4-bit number to 4-bit number 3 Outputs: < , = , > Expandable to more number of bits 0010, 1000 (Using XNOR Gates for equality)

Magnitude Comparator

A3A2A1A0 B3B2B1B0

A<B A=B A>B

33333 BABAx

22222 BABAx

11111 BABAx

00000 BABAx

0123)( xxxxBA

00123112322333)( BAxxxBAxxBAxBABA

00123112322333)( BAxxxBAxxBAxBABA

MAGNITUDE COMPARATOR