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PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Points of contact: [email protected], [email protected], [email protected]
Xin Zhao Bo Gao
Douglas C. Hopkins
North Carolina State University
Characterization of Ultra-Thin Flexible Ceramics for High-Density, 3D-Stackable Substrates
for Wearable Power Electronics
Presented at the 2016 Electronics Packaging Symp & Heterogeneous Integration Workshop, Binghamton, NY, Oct 6-7, 2016
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Points of contact: [email protected], [email protected], [email protected]
Douglas C. Hopkins, Ph.D.Director – PREES Laboratory
FREEDM System CenterNorth Carolina State Univ.1791 Varsity Dr., Suite 100Raleigh, NC 27606-7571
www.prees.org
WelcomePackaging Research in Electronic Energy
Systems (PREES)
Feb 2016
CIRCUIT DESIGN BEYOND THE SCHEMATIC
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Multiphysics Simulation, Test & Assembly
Heavy wire & ribbon (Al, Cu) bonding research with:
Hesse Mechatronics –
fully automated BJ939
Manual high-precision Pick ’n Place (≥0403 chips)
Torch-TP39V with video assist
Thermal Imaging Flir
Hand Soldering and Re-work station
3D Optical Profiler (1.7um resolution)ACS VisionMaster
Electrical circuit analysis, CAD layout, and thermo-mechanical analysis with:
COMSOL & ANSYS (MultiPhysics simulators),
AutoCad, SolidWorks, Q3D, PLECS, SPICE
Wet Bench for cleaning& “formulation”
High End Electrical Test:• Tektronix 371A Power Curve Tracer • Oscilloscopes (2GHz/5GS/s)• Arb Funct Gen., Multimeters (6.5 digit),
Power supplies (kV&HC),
• ≤500A & ≤40kV probes
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Full Processing Including Cu Systems
3-Zone Rapid Deep Infrared Furnace (150˚C - 1000˚C)(curing, sintering, thick film, glass sealing, controlled atmosphere-Cu)
Vacuum Oven (0˚C – 250˚C)(curing, drying, soldering, controlled
atmosphere; Cu)
5-Zone Reflow Oven (0˚C – 450˚C)Sakama - (curing, solder reflow, polymer thick-
film, controlled atmosphere; Cu)
4-axis Robotic Dispenser EFD – w/ 3 Valves (10µm)
(3D printing; thick film & PTF, and solder & sinter inks)
UV Curing Oven & Wands
3D Printer - Thermoplastic MakerBot Rep2X (200˚C – 290˚C)
3D scanner
Class 1000 Flow Hood
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Flexible PCB for Ultra Dense VRMs By Bo Gao
1. Stackable for FREE– Eliminates board to board connectors.2. Flat surface for GaN– Lower stress caused by CTE mismatch, simple heat sink design.3. No module substrate– FPC itself can be folded back to form pads.
A 12V Input, 100A Output High Density VRM
0.8kW/[email protected]/100A 1kW/[email protected]/100A
1.6kw/[email protected]/100A
10mm*25mm*10mm
3-ph sync. buckFrom simulation:
≤97%@2.5MHz, ≤90%@10MHz
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Objective
Investigate new ultra thin ceramics (ThinStrate by ENrG, Inc.) for power electronics applications
OUTLINE• Wearable Power Electronics• Ultra-thin Flexible Ceramics• Electrical and Thermal Characterization of 3 mol% Yttria Stabilized
Zirconia (3YSZ)• Pre-stress analysis of 3YSZ substrate with thick copper layers• Circuits Topology design Corresponding to Specific Requirements• Applications in Power Electronics• Summary
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Wearable Power ElectronicsSi WBG power semiconductors (GaN, SiC)
• Higher Breakdown Voltage• Higher Operating Temperature• Higher Thermal Conductivity• Higher power density (smaller die)
• High Voltage Devices• Less heatsink volume• Less structural complexity• Smaller Size
Challenge of Wearable Power Electronics• Suitable Substrate with flexibility• Substrate with enough thermal conductivity
Possibility for Wearable Power Electronics Module
From Traditional to Wearable
Power Module
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Ultra-thin Ceramics3YSZ Ceramic Substrates with 40 µm & 20 µm Thickness
Properties of 3YSZ substrate
Thermal Conductivity
CTE (@RT) 8.2 ppm/°
Dielectric Constant 26-28
Breakdown Voltage 2.3kV (20µm)3.5kV (40µm)
Density 6.05 g/cm2
Surface Roughness: 24-26 nm (rms)
Poisson Ratio 0.32
Young's Modulus 207 GPa
Tensile Strength 248 MPa @RT
Bend Strength 1.2 GPa
• Suitable for Metallization• High tensile strength and bending strength• Good thermal conductivity compare with organic dielectric materials with
similar thickness• Light for lower weight profile
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Electrical Characterization – Leakage CurrentLeakage Current Measurement • Electrode by E-beam Deposition
• 200 nm Ti layer• Electrode Dia. 12 mm• 25 oC ~ 175 oC
High Voltage Setup for leakage current
measurement of power semiconductor devices
1.00E-09
1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
1.00E-03
0 500 1000 1500 2000 2500 3000 3500
40 micron 3YSZ Reverse Characterization
25C
75C
125C
175C
• Suitable for low temperature (< 100oC) and low voltage (< 100V) applications
• Wearable power electronics modules
Leak
age
curre
nt
Voltage
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Electrical Characterization –– Penn State
• Samples are loaded with stepped voltage
• Stopped when conduction path is observed in the sample
• No leakage current value can be obtained due to the setup
• Limitation of leakage current is ~ 1.3 mA connector
• 20 sample points are measured for each thickness
Weipull Plot to calculate the Breakdown Voltage
• Solid red lines represent the 95% confidence bounds
• Black lines stand for ideal breakdown strength distributions
• Dielectric Strength• 288 kV/mm for 20 µm• 196 kV/mm for 40 µm
240
250
260
270
280
290
300
310
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Die
lect
ric
Stre
ngth
, MV
/ m
Observation
0
50
100
150
200
250
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Die
lect
ric
Stre
ngth
, Mv
/ m
Observation
-4
-3
-2
-1
0
1
2
5.55 5.6 5.65 5.7 5.75
Ln(1
/(1-F
))
Ln(Breakdown Strength (MV / m))
-4
-3
-2
-1
0
1
2
5.05 5.1 5.15 5.2 5.25 5.3 5.35 5.4
Ln(1
/(1-F
))
Ln(Breakdown Strength (MV/ m))
25˚C, 40µm25˚C, 20µm
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Electrical Characterization –Dielectric Strength & Breakdown Voltage v. Temperature – Penn State
• Same measurement is applied at different temperature• Dielectric Strength and Breakdown Voltage decreased at higher temperature
(25 oC ~ 150 oC)
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Electrical Characterization – Dielectric Constant and Loss
• Measured from 100 Hz to 1 MHz• Temperature -65 oC ~ 250 oC• Dielectric loss increased at higher temperature, exceeded 1 at 75 oC• Dielectric constant increased at higher temperature, the difference
of curves for 20 µm and 40 µm is due thickness variations
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Thermal Characterization – 3-Omega MethodThermal Conductivity Measurements – 3-Omega Method V+ V-
I-I+
• Kelvin connection to GOLD line deposited on the ceramic
• Gold line length, 8mm, width 0.1mm• Define input current at different frequency• Measure output voltage at corresponding 3ω
frequency
3 12 / V (dR/ dT)dT V=3 21 / / (4 )K V dR DT lR=
Increase in temperature of heater line per unit
power vs frequencySimulation and
Experiment are very good
Thermal Conductivity decreases with higher temperature
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Thermal Characterization – TTR MethodThermal Conductivity Measurements – Transient Thermo-reflectance (TTR) method
Measurement Setup• Laser Beam A applied at the sample surface• Laser Beam B is applied to measure the transient thermal reflectance signal• Both beams are focused at the same spot on the sample surface• Si photodiode collects the reflected laser beam B• Oscilloscope records the reflected laser beam B after amplification• Si detector input the TTR signal into the Oscilloscope
The result by TTR method is 2.85 W/mK, verifying the measurement results by 3-omega method
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Thermal Characterization – Simulation
Parts Dimension / mm3
Heat Capacity/
J/KgK
Thermal Conductivity /
W/m·K
Thermal Resistance
/ oC/WSiC
Diode 4××4××0.4 690 250 1E-4
Solder 4××4××0.05 230 50.9 6.14E-5Cu
plate 12××12××0.127 385 383.8 2.30E-6
3YSZ 12××12××0.02 (0.04) 157 2.3 6.04E-5
12.08E-5Al2O3 12××12××0.254 880 23 7.67E-5AlN 12××12××0.254 780 170 1.04E-5
20µm – 3YSZ 40µm – 3YSZ
10mil - AlN 10mil – Al2O3
Substrate Junction Temperature / K
20µm – 3YSZ 346
40µm – 3YSZ 368
10mil - AlN 323
10mil – Al2O3 355
• Bottom Temperature is fixed at 25 oC• Power density on the device surface is defined as 1000 W/cm2
Simulation comparison between 3YSZ ThinStrate v. traditional power substrate for 2 kV applications
Thermal impedance of 3YSZ is comparable to AlN and Al2O3 for 2 kV applications
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Mechanical Analysis - Pre-stress analysis
• ¼ symmetric applied to improve calc efficiency• Sn63Pb37 Solder Paste was set as 50 µm thick• Anand Constitutive Model was applied to describe
the viscoplastic behavior of solder paste
Copper Layer
SiC diode
Solder Paste
Ceramic
Temperature profile for soldering process, region between two red lines are for pre-stress analysis
Young’s Modulus
/Gpa
CTE/
10-6/oC
PoissonRatio
Heat Capacit
y/
J/
Density / Kg/m3
ThermalConductivity
/W/
SiC 450 4.5 0.142 690 3210 250
Sn63Pb37
Temperature
dependent24.5
Temperature
dependent
230 8400 50.9
Cu 117
Time
dependent
0.34 385 8920 383.8
AlN 330 4.6 0.24 780 3260 170
Al2O3
300 8.1 0.21 880 3690 23
3YSZ 200 8.2 0.23 157 6090 2.7
Materials Parameters for Pre-stress Simulations
Simulation setup for comparison between 3YSZ ultra-thin substrate with traditional power substrate for 2 kV applications
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Mechanical Stress – Von Mises Stress Distribution
10mil AlN substrate 10mil Alumina substrate
20 µm 3YSZ substrate 40 µm 3YSZ substrate
Max Von Mises Stress• AlN – 141 Mpa• Alumina – 248 Mpa• 20 µm 3YSZ – 292 Mpa• 40 µm 3YSZ – 261 Mpa
Location• The interface between
Ceramic Layer and Copper Layer
Higher Stress concentration on the 3YSZ substrate• Small thickness• Large Stress gradient
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Mechanical Stress – Shear Stress in Solder Layer
10mil AlN substrate 10mil Alumina substrate
20 µm 3YSZ substrate 40 µm 3YSZ substrate
Shear Stress on solder layer• AlN – 0.3586 Mpa• Alumina – 0.2904 Mpa• 20 µm 3YSZ – 0.772 Mpa• 40 µm 3YSZ – 0.7612 Mpa
Location• The corner of SiC device• Front side for AlN and
Alumina Modules• Backside for 3YSZ
modules
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Mechanical Stress – Shear Stress Ceramic Layer
10mil AlN substrate 10mil Alumina substrate
20 µm 3YSZ substrate 40 µm 3YSZ substrate
Shear Stress on Ceramic layer• AlN – 33.8 Mpa• Alumina – 60.9 Mpa• 20 µm 3YSZ – 118 Mpa• 40 µm 3YSZ – 194 Mpa
Location• The corner of SiC device• Interface with Cu layers
Large shear stress in 3YSZ substrate, need to optimized metallization process for better stress management
Tensile stress of 3YSZ: 248 Mpa
Lower than the maximum allowed tensile stress
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Circuit Design for general wearable power electronics
Most general topologies for power electronics half-bridge configuration
Previous Work on single switch configuration for flexible power electronics applications
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
3D Layout design for wearable power electronics
3D concept layout based on ultra-thin 3YSZ substrateLeft: with switching node floating;
Right: with switching node sitting on the substrate
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Application Characterization for circuit selection
Properties of substrate required by different specific applications
2D – 2 dimensional 3D – 3 dimensionalHV – High Voltage HF – High FrequencyHC – High Current HP – High PowerHT – High Temperature
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Summary
• 3YSZ ultra-thin ceramic substrate was introduced for its potential application to wearable power electronics
• Electrical Characterization indicated that the substrate can withstand high voltage, but considering its higher leakage current under high temperature and high voltage, its potential application mainly focuses on lower voltage level and lower temperature
• Thermal Characterization results showed that the thermal conductivity remains high at lower temperatures, such as for wearables
• Thermal simulations showed that the thermal performance of ultra-thin 3YSZ substrate is comparable to traditional substrate AlN and Al2O3
• Pre-stress analysis indicated that the substrate suffered higher shear strength, which requires optimization of metallization process for better thermal management
• General topologies for phase leg configuration are introduced, together with former works done by PREES on flexible power switches based on 3YSZ ultra-thin flexible substrate
• Two 3D topologies for single switches are proposed• Requirements of flexible substrate materials for different specific applications are
summarized
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Acknowledgements
The authors would like to thank Texas Instruments for Laboratory support of such technical explorations, along with other PREES Sponsors, and ENrG for supplying materials.
Also, Haotao KE and Mingyu Yang for early design contributions.
PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS
2016 Electronics Packaging Symposium & Workshop
Thank youQuestions?
Douglas C. Hopkins, Ph.D.Director – PREES Laboratory, FREEDM System Center
North Carolina State University1791 Varsity Dr., Suite 100; Raleigh, NC 27606-7571
[email protected] www.prees.org919-513-5929