Characterization Techniques for High Speed Oversampled Data Converters

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Characterization Techniques for High SpeedOversampled Data Converters

Ankesh Jain and Shanthi Pavan

Abstract—Bench characterization of wide band oversampledconverters is a challenge due to the high data rate at the output ofthe modulator. We propose the use of a duobinary test interface toextend the frequency range over which reliable laboratory mea-surements become possible. We show that using such an interfaceeffectively randomizes the modulator output data and reduceshigh frequency content, thereby reducing the bandwidth demandsmade on the test equipment. It also reduces degradation of themodulator performance caused by package feedthrough effects.Experimental results from a test chip in 90 nm CMOS show thatthe proposed interface extends the upper sampling frequency limitof an existing single-bit CTDSM from 3.6 GHz to 4.4 GHz.

Index Terms—Analog-digital (A/D) conversion, bandwidth,delta sigma, duobinary coding, high speed integrated circuit mea-surement, oscilloscope, oversampling, partial response signalling.

I. INTRODUCTION

W IDEBAND oversampled converters in general, andcontinuous-time delta sigma modulators (CTDSM) in

particular have received significant attention recently for theirability to digitize signals with bandwidths even as high as 100MHz [1]. Characterization of such wide band CTDSMs in thelaboratory is a challenge. This is particularly so when singlebit modulators are used, as the oversampling ratio (OSR) (andthereby the clock frequency) needed to achieve the desiredresolution can be very high. The main reason that motivates asingle bit quantizer in the delta-sigma loop is that the quantizercan be realized in a power efficient manner. This reduces theoverall modulator power dissipation even though the samplingrate is higher. For example, the single bit CTDSM of [2] usesa 6 GHz sampling clock to achieve 60 dB dynamic range in a60 MHz signal bandwidth.Bench characterization of these modulators involves the fol-

lowing procedure. The CTDSM is excited with an inband sinu-soid, and the output bit stream is captured and processed off lineto infer the inband Signal to Noise Ratio (SNR). Several strate-gies can be used to accomplish the latter, and are listed below.To give a better feel for the numbers involved, we will assumethat we intend to characterize a single bit CTDSM operating at4 GS/s, with a targeted resolution of 14 bits (after decimation)in a 40 MHz bandwidth.1) Logic Analyzer: The easiest way to capture the modulatoroutput sequence is by using a logic analyzer. However, a

Manuscript received September 11, 2013; revised January 03, 2014; acceptedJanuary 24, 2014. This work was supported in part by a grant from the Depart-ment of Information Technology, Government of India through the Center forAnalog and Mixed Signal Design at IIT Madras, Chennai, India.The authors are with the Indian Institute of Technology, Madras 600 036,

India (e-mail: [email protected]).Digital Object Identifier 10.1109/TCSI.2014.2309895

wideband design such as ours necessitates a high speedlogic analyzer, which are expensive.

2) On-chip Deserializer and External Logic Analyzer: A costeffective way to circumvent the problem described in theprevious strategy is to deserialize the 4 GS/s stream intoslower bitstreams using an on-chip deserializer, whichare inturn captured using a multichannel low speed logicanalyzer. However, this approach has several issues.Assuming that we deserialize by a factor of 20, the chipneeds to have 20 output pins, each toggling at 200 MS/s.This causes significant supply and ground bounce dueto package parasitics. Further, the outputs can couple(through the package) to the sensitive clock input pins,causing jitter in the sampling clock and degrade modulatorperformance. Apart from the design effort involved in thedeserializer, skews between the various bit streams on thetest board have to also be carefully accounted for.

3) On-chip Deserializer with LVDS buffers and ExternalLogic Analyzer: In order to reduce the supply and groundbounce, it is preferable to use an LVDS interface for eachof the deserialized bit streams. This doubles the number oftest pins needed. Further, since many logic analyzers canhandle only CMOS logic, level translators are needed onthe test board, further complicating its design.

4) On-chip Decimation Filter and External Logic Analyzer: Ifa high speed decimation filter is implemented together withthe modulator, the decimated output stream (which is at theNyquist rate) can be captured on a logic analyzer. In our ex-ample, the one bit modulator output at 4 GS/s is decimatedto 80 MS/s and requires 14 bits. The increased pin countnecessitates a larger package, compounding problems withrespect to coupling effects through the package. Further, itis difficult to isolate problems between the modulator andthe decimator in the case of poor measured performance(especially since the decimation filter is bound to be chal-lenging in its own right, due to the high speed of the inputstream).

5) Waveform capture on a High Speed Sampling Oscillo-scope: The modulator output bit stream is brought outthrough a high speed LVDS buffer and the analog wave-form is captured using a high speed sampling oscilloscope.The bit stream is inferred by processing the stored wave-form on the oscilloscope off line. This scheme is feasibledue to the ready availability of storage oscilloscopes thatare capable of sampling at very high speeds (several tensof GS/s). This is attractive due to the following. Only twotest pins are needed for the modulator output waveform.The on-chip test interface is straightforward, as onlymatched transmission lines (to interface to the 50 portsof the oscilloscope) are needed on the test board. Further,

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Fig. 1. Measuredmagnitude response of the Agilent 80204B realtime samplingoscilloscope. The 3 dB bandwidth is approximately 2 GHz. The instrument cansample at rates as high as 40 GS/s.

from a practical viewpoint, a high speed oscilloscope is amore versatile instrument than a logic analyzer, and mightbe more readily available.

From this discussion, it appears that scheme [e] is the mostattractive in terms of lab bench characterization. However, it hasthe following problems. Since the high speed stream is broughtout of the chip, finite bandwidth of the package and the boardcan limit the performance. Further, while storage oscilloscopescan sample at high rates (even those that are relatively less ex-pensive), their input signal bandwidth is limited. This limits themaximum bit rate at which the modulator output data can be re-liably captured. For example, the instrument used in this work(Agilent 80204B) can sample at rates as high as 40 GS/s, buthas a signal bandwidth of only 2 GHz, as shown in Fig. 1.The finite bandwidth of the package and scope together cause

severe inter-symbol interference (ISI) at high data rates. Fig. 2depicts the eye diagrams of the captured waveform using thisoscilloscope for various output data rates of the modulator. Theeye, which is widely open at 3 GS/s, is virtually shut at 4 GS/s.Reduction in the eye opening makes it virtually impossible tocorrectly determine the data bit (using a simple recovery al-gorithm). Random bit errors in the recovered stream cause thein-band noise floor of the CTDSM to increase, making it appearas if the modulator is not functioning properly. From the eye di-agrams in Fig. 2, we infer that data capture with this package,oscilloscope and test setup is not reliable beyond about 3.6 GS/s.

Another issue is finite package isolation (which decreasesdramatically with frequency). It causes feedthrough of theoutput stream as shown in Fig. 3. This can degrade the perfor-mance of the modulator in unpredictable ways—for example,corruption of the references can cause distortion. Feedthroughof the output stream onto the modulator’s input clock can causejitter, which results in an increased in-band noise floor.In this work, which is an extension of [3], we propose a test

technique that addresses these issues. The modulator output ismodified using duobinary coding [4], which is a form of partialresponse signalling used in data communication links. This notonly reduces the effective bandwidth of the output bit stream(making it more reliable to capture data on the oscilloscope),

Fig. 2. Eye diagram of modulator output captured using high speed oscillo-scope (DSO-80204B).

Fig. 3. Diagram of package showing coupling between the bondwires due tofinite package isolation.

but also effectively “randomizes” the output stream to mitigatethe issue of package feedthrough discussed above. The detailsof our approach and the demonstration of its effectiveness isthe subject of the rest of this paper, which is organized as fol-lows. Section II gives a brief overview of duobinary coding,well known in digital data transmission. We discuss its advan-tages, especially in the context of an oversampling converter.Section III gives simulation results showing the effect of limited


JAIN AND PAVAN: CHARACTERIZATION TECHNIQUES FOR HIGH SPEED OVERSAMPLED DATA CONVERTERS 3

Fig. 4. Development of duobinary coding (a) Using a 2-tap FIR filter at thetransmitter and its inverse at the receiver, leading to error propagation (b) Ad-dition of a precoder at transmitter input to avoid the propagation of errors.

channel bandwidth on the horizontal and vertical eye-openingwith binary and duobinary signalling. Circuit implementationdetails of the proposed test interface are given in Section IV.Section IV-A gives the simulation results of our modulator withaccounting for package parasitics, which hint at the improve-ments to be had by using a duobinary interface. Section V showsmeasurement results from a single bit modulator designed in a90 nm CMOS process [5], with and without duobinary coding.Thanks to the use of the duobinary coding, the modulator can bemeasured at clock speeds as high as 4.4 GHz (which is the sim-ulated limit of operation of the modulator), when compared toonly 3.6 GHz with the conventional LVDS interface. Section VIconcludes the paper.

II. DUOBINARY CODING

From the discussion in the previous section, we see that thechannel bandwidth (2 GHz) is not quite adequate to allow ISIfree transmission of modulator output data beyond about 3.6GS/s. This is a classical problem in data communication, andone approach to mitigating the effect of ISI is to use partial re-sponse signal. The basic idea behind this technique is as fol-lows. Since the channel bandwidth is limited, the bandwidth ofthe transmitted waveform is deliberately reduced (so as to belargely accommodated in the low bandwidth channel) using anFIR filter. Since the FIR filter (and thereby the deliberately in-troduced ISI in the transmitted waveform) is known a priori, itseffect can be undone at the receiver.Duobinary coding or signalling [4] is an example of partial

response signalling based on a one tap FIR filter with a transferfunction of . Since has a zero at ,it behaves like a low pass filter, resulting in waveform with asmaller transmission bandwidth. The zero of this filter at isparticularly attractive in our case (where sequence is the outputof an oversampled converter), as the notch occurs precisely atthe frequencywhere the spectral content of themodulator outputstream is high.Fig. 4 shows the development of duobinary coding. The se-

quence to be transmitted , (which in our case is the mod-ulator output) is given to a transmitter, which is a one tap FIRfilter and converts into a duobinary sequence given by

(1)

Channel impairments cause the received sequence to be .From (1), we see that can be recovered from using(Fig. 4)

(2)

As is evident from (2), the recovered bit depends on theprevious recovered bit . Thus, an error in a recoveredbit propagates to the next bit.Error propagation can be avoided if the transmitted bit de-

pends only on one sample of the received sequence. Since thetransmitted symbols are 0 and 1, the outputs of the FIR filter are0, 1, 2. The three values can be divided into two sets—

and . The output lies in if the current andprevious bits entering the FIR filter are the same, and in oth-erwise. To make the decoded sequence depend only on the cur-rently received sample, one could do the following (rather thandirectly excite the FIR filter with ). The current input bitto the FIR filter, denoted by , is chosen to be identical tothe previous one if , and the complement

if . Turning things upside down, if, causing the transmitted sequence to be a

‘1’. If , causing the transmittedsequence to be ‘2’ or ‘0’. In either case, at the receiver, the cur-rent sample influences the decision of only one transmitted bit,avoiding error propagation. It is clear, therefore, that mustbe related to and through

(3)

where denotes modulo-2 addition. is called the pre-coded sequence and Fig. 4(b) shows the signal chain. Noticethat the precoder (but for the modulo 2 addition) looks like anIIR filter—however, due to bounded nature of the modulo oper-ation, high frequency components are not boosted up, like in anIIR filter. The transmitted sequence, therefore, will have lowerbandwidth due to low pass filtering by the one tap FIR filter

(4)

Assuming the channel impairments to be negligible (thanksto the reduced bandwidth of the transmitted bit stream), the re-ceived sequence , thereby enabling the recovery ofthe transmitted bitstream.It can be shown mathematically that the transmitted bit

can be recovered from using a modulo-2 operation as givenbelow

(5)

Fig. 5 shows a practical implementation of the duobinarycoding scheme. The CTDSM output sequence can take onvalues 0 or 1. First, is precoded to generate , whichalso takes on values 0 or 1. The precoder output is then con-verted into bipolar form where maps to . The bipolaroutput is processed by the one tap FIR filter, and the output cantherefore take on values , 0 or 2. In order to limit the max-imum amplitude of output sequence to , it is passed through again block having a gain of 0.5. The sequence is then trans-mitted through the channel and the received sequence is denoted



Fig. 5. Practical implementation of the duobinary coding scheme.

TABLE IEXAMPLE SEQUENCES IN A DUOBINARY SYSTEM

Fig. 6. Output PSD of the raw (gray) and duobinary encoded sequences (blue).

by , from which the transmitted bit can be recovered usingthe rule

Table I shows some representative sequences in the duobi-nary system. Further, we note that• no direct transition can be made from the highest voltagelevel to the lowest voltage level or vice-versa, and

• the fastest transition from a to takes two bit inter-vals.

A transition from to and back again to needs atleast four bit intervals, which is twice the number when com-pared to the original uncoded sequence. This corresponds to abandwidth reduction by a factor of two, or a doubling of thedata rate possible for a given channel bandwidth. The latter isthe origin of the word duobinary—intended to mean twice therate of a binary sequence.Fig. 6 compares the power spectral densities (PSD) of the

modulator output sequence and the output sequence of theduobinary coder . The reduced spectral power of at halfthe sampling rate is apparent. Further, we see that thanks to pre-coding, the large sinusoidal signal in the modulator output hasbeen spread out. This whitening of the spectrum is useful as it

Fig. 7. Testbench used for simulating the effect of channel cutoff frequency onhorizontal and vertical eye openings of the received signal.

Fig. 8. Horizontal eye-opening (Hz-EO) and vertical eye-opening (Vt-EO) fordifferent channel cutoff frequencies with proposed (duobinary) signalling andconventional (binary) signalling.

prevents the input sinusoid from coupling to the reference volt-ages of the modulator through the package.

A. Characterization of Multibit Modulators

We digress briefly to discuss if similar techniques can beapplied to multibit modulators. A straightforward way of ex-tending our techniques to such designs is to use duobinary sig-naling on each data line of the multibit output. Assuming a fourbit modulator, a four channel oscilloscope would be necessary.Another method, needing only a single channel scope, wouldbe to use a 4 bit current steering DAC to convert the multibitsequence into a multilevel analog waveform. The DAC wouldneed the elements to match to about 6 bits for easy recovery ofthe binary sequence from the output.

III. EFFECT OF CHANNEL BANDWIDTH ON EYE OPENING

This section presents simulation results to explain the ef-fect of channel bandwidth on conventional (binary) and pro-posed (duobinary) signalling. Fig. 7 shows the testbench usedfor the simulations. The -Modulator used in these simu-lations is that described in [5]. A 20th order lowpass Butter-worth filter was used to model the bandwidth limitation of theoscilloscope—this is due to the practically “brickwall” natureof the oscilloscope transfer function as seen in Fig. 1. Fig. 8shows the plot of horizontal eye-opening (Hz-EO) and verticaleye-opening (Vt-EO) as a function of channel bandwidth (nor-malized to the bit rate) for binary and duobinary signalling. As-suming that one needs a horizontal eye opening of atleast 30%of the bit period for accurate data recovery, it is seen that binarysignaling needs about 50% more bandwidth than in the duobi-nary case.Fig. 9 shows the waveforms responsible for creating the min-

imum eye opening (shown in blue) in the case of binary andduobinary signalling. With binary signaling, the 1010 sequence(which is approximately a sinusoid at half the bit rate) definesthe eye opening. One can therefore expect that if the channelcutoff frequency is lower than half the bit rate, a closed eye will



Fig. 9. Eye diagrams for binary and duobinary signalling when channel band-width is lesser than the bit rate but greater than half the bitrate.

Fig. 10. Simplified schematic of the duobinary coding scheme with precoding.

result. With duobinary signaling, on the other hand, a 1010 se-quence at the input of the FIR filter will lead to an output wave-form which resembles a sinusoid at one fourth the bit rate—im-plying that the eye will still be open.

IV. CIRCUIT DESIGN AND PACKAGE SIMULATIONS

The precoder and duobinary encoder circuit were integratedwith an existing CTDSM [5], as shown in Fig. 10. The single bitmodulator uses an FIR feedback DAC, with an aim of achievinglow jitter sensitivity and high linearity, like in a multibit design.Due to the single bit quantizer, the sampling rate has to be in-creased (when compared to a multibit loop) to achieve the de-sired in band signal to quantization noise ratio (SQNR). Thenominal signal bandwidth and sampling rate of the converterare 36 MHz and 3.6 GS/s respectively, resulting in an over sam-pling ratio (OSR) of 50. The design is implemented in a 90 nmCMOS process. Simulations show that the modulator is func-tional for clock rates as high as 4.4 GS/s, though this could notbe established using measurements, due to the finite bandwidthof the test setup, as discussed earlier in this paper. This was oneof the main motivations for the investigations that form the sub-ject of this paper.The test interface consists of the precoder, implemented using

an XOR gate, and a D-flipflop, as shown in Fig. 10. The XORgate is implemented in standard CMOS logic. The layout ex-tracted version of the XOR gate successfully works upto 5 GHzacross all process corners in the 90 nm CMOS process used inthis work. The output of the XOR gate drives the duobinary

Fig. 11. Bondwire model used for package simulation, only two bond wiresare shown in this figure.

coder, where it is added with its delayed version. The addition ofthe outputs is done in the current domain in the LVDS buffers.The currents in each of these buffers is halved in relation to astandard buffer, so that the peak current remains the same as thatin a conventional LVDS buffer. It is thus seen that the proposedscheme can be easily implemented using a minimal amount ofextra hardware. The interface is configurable so that the duobi-nary mode can be bypassed, resulting in a conventional LVDSinterface. This enables comparison of the proposed interfacewith a conventional one.

A. Effect of Package Parasitics

The package can influence the measured performance of theCTDSM in several ways—the finite bandwidth of the packagecan severely attenuate the data stream, making it difficult to de-code the bit sequence. Duobinary coding helps in this aspect byreducing the effective bandwidth of the output data. Another im-portant aspect of the package is its finite isolation—this is due toinductive and capacitive coupling between bondwires. In gen-eral, isolation between two pins on the package can be expectedto decrease with frequency. Thus, the high speed bit stream cancouple through package parasitics, to the sensitive reference andclock inputs of the modulator. This leads to harmonic distortionand demodulation of shaped quantization noise into the signalband respectively. In the analysis to follow, we show that duobi-nary signalling also reduces the impact of package isolation onmeasured modulator performance.In this work, we used a 48 pin QFN (Quad Flat No lead)

package [6], for its low pin capacitance. Bondwire inductancefor the QFN-48 package is about 3 nH per pin [7], and mutualcapacitance between the bondwires is about 50 fF. Fig. 11 showsthe parasitic model of the package we used for simulations. Api-model is used to model the parasitics of each bond wire—the3 nH inductance is divided into two sections, is the mutualcapacitance between the bondwires. is the lead inductance.The mutual coupling coefficient between adjacent bondwires is

while that between lead inductances is .A transistor level model of the CTDSM and the test interface

is embedded in this package model and the modulator was sim-ulated with a sampling clock of 4.4 GHz. To amplify the effectof package coupling, simulations were run by placing the DACreference pins next to the output pins. (In practice, care is takento put them far away). Fig. 12 shows the inband output PSDusing the conventional and proposed test interface. It is seen thatthe second harmonic is about 18 dB lower when the duobinary



Fig. 12. Output spectrum using the conventional and proposed (duobinary) testinterface.

Fig. 13. Output spectrum using the conventional and proposed (duobinary) in-terfaces, with a decoupling capacitor of 500 pF between the references.

interface is used for characterization. The insets show the eyediagrams of the output bit streams in both cases. For these sim-ulations, we assumed that the oscilloscope bandwidth was verylarge. Clearly, finite bandwidth of the package has no role toplay in the poor inband SNDR obtained using the conventionalinterface. The increased distortion makes sense due to the fol-lowing. In the conventional interface, the input component inthe bit stream couples on the references through package para-sitics. The small feedthrough of the input on to the referencesmanifests as second harmonic distortion. With the duobinary in-terface, the output sequence does not consist of the input sinu-soid due to the randomizing action of the precoder, as seen inFig. 6.To confirm the observations made above, simulations were

run using different values of decoupling capacitors between theDAC reference voltages inside the chip. A large capacitor acrossthe references more effectively attenuates feedthrough on thereferences. Figs. 13 and 14 show the PSDs using the conven-tional and duobinary interfaces for 500 pF and 1 nF decouplingcapacitors. In the former case, we see that there using the con-ventional interface causes increased harmonic distortion. Whenthe capacitance is increased to 1 nF, the two spectra are virtuallythe same, indicating that the feedthrough has been attenuatedto a sufficiently large degree to be of little consequence. Fromthis, we see that with the duobinary interface, the degradationof CTDSM performance due to package feedthrough is smallerfor a given amount of on-chip decoupling capacitance.

Fig. 14. Output spectrum using the conventional and proposed (duobinary) in-terfaces, with a decoupling capacitor of 1 nF between the references.

Fig. 15. Simulation results showing the effect of the coupling between theoutput and the clock pin using conventional and proposed test interface.

Another cause of degradation of themodulator’s performanceis due to the coupling between the clock and modulator outputpins. Again, in order to amplify the effect of this coupling, clockpins are placed next to the output pins. Coupling of the outputbitstream on to the clock causes jitter, which manifests as anincrease in the inband noise floor. Fig. 15 shows the outputspectrum of the modulator when simulated with the packagemodel shown in the Fig. 11. Using the conventional test inter-face results in a higher noise floor and achieves a SNDR of 48dB while the duobinary interface results in a lower noise floor,and achieving an SNDR of 60 dB. This makes sense—the FIRfilter used in the duobinary coder has a zero at , which isprecisely the frequency where the shaped quantization noise ofthe CTDSM is maximum. Thus, the duobinary interface resultsin an output stream with reduced energy at high frequencies,thereby reducing jitter induced on the clock due to finite packageisolation.

V. MEASUREMENT RESULTS

A test chip was designed to verify the efficacy of the ideas de-scribed in this paper. The IC was fabricated in a 90 nm CMOSprocess through the Europractice program. The chip consistedof a fourth order single-bit CTDSM that can operate up to aclock rate of 4.4 GHz. The oversampling ratio is 50. The mod-ulator uses an FIR feedback DAC—the design details are de-scribed in [5]. The original design, as reported in [5], could onlybe tested up to 3.6 GS/s due to the limited bandwidth of thetest setup. The interface described in this paper was an effort to



Fig. 16. Chip layout and test board.

Fig. 17. Eye diagram of captured waveform of modulator output at 4.4 GHzusing conventional test interface.

enable measurement of the design of [5] at higher speeds andin a more robust manner. The test interface, therefore, consistsof a precoder and two LVDS drivers, whose outputs are addedin the current domain—effectively implementing a duobinarytransmitter. The chip also included a provision to modify thetest interface to a conventional one (without duobinary coding).Fig. 16 shows the chip layout and the test board used for char-acterization. The CTDSM occupies an active area of 0.14 mmwhile the duobinary interface occupies 0.006 mm . Adding theduobinary interface, therefore, adds a negligible power and areaoverhead.The differential output waveform is captured using a dig-

ital storage oscilloscope (Agilent DSO-80204B) whose analogbandwidth is 2 GHz. Fig. 17 shows the eye diagram of the cap-tured waveform of the modulator output at 4.4 GHz using theconventional test interface. From the Fig. 17 it is evident thateye is almost closed at the sampling instants resulting in deci-sion errors, which manifest as an increase in the inband noisefloor. The corresponding eye diagram with the duobinary inter-face is shown in Fig. 18. The two white horizontal lines corre-spond to threshold voltage levels, while the dotted white verticalline corresponds to the sampling instant. If the captured bit liesbetween the two threshold voltages, the recovered output bit isdeemed to be 1, and 0 otherwise. Notice the widely open eyeeven at 4.4 GS/s—demonstrating the efficacy of the duobinaryinterface.A 32K points Blackman-Harris window was used for spectral

estimation. For clock speeds up to 3.6 GHz, there was very littledifference between the SNDRsmeasured using the conventionaland duobinary interfaces. At higher speeds, the bits capturedusing the conventional interface become unreliable due to diffi-culties with data capture as explained before using eye diagrams

Fig. 18. Eye diagram of captured waveform of modulator output at 4.4 GHzusing proposed (duobinary) test interface.

Fig. 19. PSD of measured data without using duobinary coding at 4 GHz. Theincreased in-band noise floor is due to errors introduced in the data captureprocess.

Fig. 20. PSD of measured data using conventional and proposed (duobinary)test interface at 4.4 GHz.

shown in Figs. 17 and 18. The high bit error rate results in asignificantly increased inband noise floor, as shown in Fig. 19(where the clock frequency is 4 GHz). On the other hand, usingthe duobinary interface enables measurements up to 4.4 GHz, aspeed beyond which the modulator becomes unstable.Fig. 20 shows the output spectra of the modulator using the

conventional and the duobinary test interfaces at 4.4 GHz. Ascan be expected from the eye diagrams, using the latter enhancesthe range of frequencies over which reliable measurements be-come possible.The PSD of the recovered CTDSM output data sequence is

shown in blue in Fig. 21. A second harmonic is clearly visible.This is due to the rise-fall asymmetry of the modulator’s feed-back DAC. This is a problem that arises in high speed single-bit



Fig. 21. Modulator PSD obtained using the proposed interface at a clock rateof 4.4 GHz—with and without digital correction for feedback DAC rise-fallasymmetry.

Fig. 22. Measured SN(D)R as a function of signal amplitude at 4.4 GHz.

modulators, where rise and fall times can be a significant frac-tion of the clock period, as described in detail in [8]. As shownin that reference, this can be corrected in a post facto mannerby doing the following. Denoting the CTDSM output sequenceby is added to it, where is a smallnumber that can be obtained from the second harmonic distor-tion in . In our design, , which was estimated from mea-surements, was about . The PSD of the correctedsequence is shown in black in Fig. 21, and it is seen that thesecond harmonic distortion is eliminated and the in-band noisefloor is lower.Fig. 22 shows the measured SN(D)R plot of the modulator

with the proposed duobinary interface at 4.4 GHz. The CTDSMachieves SNDR/SNR/DR of 70.93 dB/71.21 dB/76 dB in a 44MHz signal bandwidth.

VI. CONCLUSION

We showed that incorporating an on-chip duobinary interfacewith precoding can significantly enhance the frequency rangeover which reliable CTDSM measurements become possible.Precoding whitens the CTDSM output spectrum and preventserror propagation during sequence recovery. Duobinary coding,by the virtue of introducing controlled ISI, reduces the effectivebandwidth of the precoded bit stream, relaxing speed require-ments of the measurement equipment. Precoding of the modu-lators output stream also spreads the input tone—and reducesharmonic distortion caused by the effect of input feedthrough(due to finite package isolation) on to the references. Measuredresults, which incorporated the interface onto an existing highspeed CTDSM test chip show that the maximum clock rate can

be increased from 3.6 GHz to 4.4 GHz. The single bit modu-lator achieves a dynamic range of 76 dB in a 44MHz bandwidthwhile sampling at 4.4 GHz. The 4.4 GHz limit is not imposedby the interface, but by the CTDSM design.

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Ankesh Jain received the B.Tech. degree in elec-tronics and communication engineering fromMotilalNehru National Institute of Technology, Allahabad,India, in 2007. He is currently working towards thePh.D. degree at the Indian Institute of Technology,Madras, India, where his focus is on high speed over-sampled data converters.From 2007 to 2009, he was with Freescale Semi-

conductor, Noida, where he worked on high speedPLLs and clock synthesizers. His research interestsare in the area of high speed analog and mixed signal.

Mr. Jain is the recipient of Best student paper award in IEEE InternationalSymposium on Circuits and Systems, ISCAS 2013.

Shanthi Pavan (SM’12) received the B.Tech. degreein electronics and communication engineering fromthe Indian Institute of Technology, Madras, India, in1995, and the M.S. and D.Sc. degrees from ColumbiaUniversity, New York, NY, USA, in 1997 and 1999,respectively.From 1997 to 2000, he was with Texas Instru-

ments, Warren, NJ, USA, where he was involvedwith high-speed analog filters and data converters.From 2000 to June 200, he worked on microwaveICs for data communication at Bigbear Networks,

Sunnyvale, CA, USA. Since July 2002, he has been with the Indian Instituteof Technology, Madras, India, where he is now a Professor of ElectricalEngineering. His research interests are in the areas of high-speed analog circuitdesign and signal processing.Dr. Pavan is a Fellow of the Indian National Academy of Engineering. He

is the recipient of the 2012 Shanti Swarup Bhatnagar Award in EngineeringSciences, the IEEE Circuits and Systems Society Darlington Best PaperAward (2009), the Swarnajayanthi Fellowship (from the Government of India),the Young Faculty Recognition Award from IIT Madras (for excellence inteaching), the Technomentor Award from the India Semiconductor Associ-ation and the Young Engineer Award from the Indian National Academy ofEngineering (2006). He is the Editor-in-Chief of the IEEE TRANSACTIONSON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS and served on the editorialboard of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESSBRIEFS from 2006 to 2007. He serves on the technical program committee ofthe International Solid State Circuits Conference.

Documents

Characterization Techniques for High Speed Oversampled Data Converters